1 /* SPDX-License-Identifier: GPL-2.0 */
3 * This file contains the 64-bit "server" PowerPC variant
4 * of the low level exception handling including exception
5 * vectors, exception return, part of the slb and stab
6 * handling and other fixed offset specific things.
8 * This file is meant to be #included from head_64.S due to
9 * position dependent assembly.
11 * Most of this originates from head_64.S and thus has the same
16 #include <asm/hw_irq.h>
17 #include <asm/exception-64s.h>
18 #include <asm/ptrace.h>
19 #include <asm/cpuidle.h>
20 #include <asm/head-64.h>
21 #include <asm/feature-fixups.h>
25 * There are a few constraints to be concerned with.
26 * - Real mode exceptions code/data must be located at their physical location.
27 * - Virtual mode exceptions must be mapped at their 0xc000... location.
28 * - Fixed location code must not call directly beyond the __end_interrupts
29 * area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence
31 * - LOAD_HANDLER targets must be within first 64K of physical 0 /
33 * - Conditional branch targets must be within +/-32K of caller.
35 * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and
36 * therefore don't have to run in physically located code or rfid to
37 * virtual mode kernel code. However on relocatable kernels they do have
38 * to branch to KERNELBASE offset because the rest of the kernel (outside
39 * the exception vectors) may be located elsewhere.
41 * Virtual exceptions correspond with physical, except their entry points
42 * are offset by 0xc000000000000000 and also tend to get an added 0x4000
43 * offset applied. Virtual exceptions are enabled with the Alternate
44 * Interrupt Location (AIL) bit set in the LPCR. However this does not
45 * guarantee they will be delivered virtually. Some conditions (see the ISA)
46 * cause exceptions to be delivered in real mode.
48 * It's impossible to receive interrupts below 0x300 via AIL.
50 * KVM: None of the virtual exceptions are from the guest. Anything that
51 * escalated to HV=1 from HV=0 is delivered via real mode handlers.
54 * We layout physical memory as follows:
55 * 0x0000 - 0x00ff : Secondary processor spin code
56 * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors
57 * 0x1900 - 0x3fff : Real mode trampolines
58 * 0x4000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors
59 * 0x5900 - 0x6fff : Relon mode trampolines
60 * 0x7000 - 0x7fff : FWNMI data area
61 * 0x8000 - .... : Common interrupt handlers, remaining early
62 * setup code, rest of kernel.
64 * We could reclaim 0x4000-0x42ff for real mode trampolines if the space
65 * is necessary. Until then it's more consistent to explicitly put VIRT_NONE
68 OPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900)
69 OPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x4000)
70 OPEN_FIXED_SECTION(virt_vectors, 0x4000, 0x5900)
71 OPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000)
73 #ifdef CONFIG_PPC_POWERNV
74 .globl start_real_trampolines
75 .globl end_real_trampolines
76 .globl start_virt_trampolines
77 .globl end_virt_trampolines
80 #if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV)
82 * Data area reserved for FWNMI option.
83 * This address (0x7000) is fixed by the RPA.
84 * pseries and powernv need to keep the whole page from
85 * 0x7000 to 0x8000 free for use by the firmware
87 ZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000)
88 OPEN_TEXT_SECTION(0x8000)
90 OPEN_TEXT_SECTION(0x7000)
93 USE_FIXED_SECTION(real_vectors)
96 * This is the start of the interrupt handlers for pSeries
97 * This code runs with relocation off.
98 * Code from here to __end_interrupts gets copied down to real
99 * address 0x100 when we are running a relocatable kernel.
100 * Therefore any relative branches in this section must only
101 * branch to labels in this section.
103 .globl __start_interrupts
106 /* No virt vectors corresponding with 0x0..0x100 */
107 EXC_VIRT_NONE(0x4000, 0x100)
110 EXC_REAL_BEGIN(system_reset, 0x100, 0x100)
112 EXCEPTION_PROLOG_0 PACA_EXNMI
114 /* This is EXCEPTION_PROLOG_1 with the idle feature section added */
115 OPT_SAVE_REG_TO_PACA(PACA_EXNMI+EX_PPR, r9, CPU_FTR_HAS_PPR)
116 OPT_SAVE_REG_TO_PACA(PACA_EXNMI+EX_CFAR, r10, CPU_FTR_CFAR)
118 SAVE_CTR(r10, PACA_EXNMI)
121 #ifdef CONFIG_PPC_P7_NAP
123 * If running native on arch 2.06 or later, check if we are waking up
124 * from nap/sleep/winkle, and branch to idle handler. This tests SRR1
125 * bits 46:47. A non-0 value indicates that we are coming from a power
126 * saving state. The idle wakeup handler initially runs in real mode,
127 * but we branch to the 0xc000... address so we can turn on relocation
132 rlwinm. r10,r10,47-31,30,31
136 bltlr cr1 /* no state loss, return to idle caller */
137 BRANCH_TO_C000(r10, system_reset_idle_common)
139 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
142 KVMTEST EXC_STD 0x100
143 std r11,PACA_EXNMI+EX_R11(r13)
144 std r12,PACA_EXNMI+EX_R12(r13)
146 std r10,PACA_EXNMI+EX_R13(r13)
148 EXCEPTION_PROLOG_2_REAL system_reset_common, EXC_STD, 0
150 * MSR_RI is not enabled, because PACA_EXNMI and nmi stack is
151 * being used, so a nested NMI exception would corrupt it.
154 EXC_REAL_END(system_reset, 0x100, 0x100)
155 EXC_VIRT_NONE(0x4100, 0x100)
156 TRAMP_KVM(PACA_EXNMI, 0x100)
158 #ifdef CONFIG_PPC_P7_NAP
159 EXC_COMMON_BEGIN(system_reset_idle_common)
161 * This must be a direct branch (without linker branch stub) because
162 * we can not use TOC at this point as r2 may not be restored yet.
164 b idle_return_gpr_loss
167 EXC_COMMON_BEGIN(system_reset_common)
169 * Increment paca->in_nmi then enable MSR_RI. SLB or MCE will be able
170 * to recover, but nested NMI will notice in_nmi and not recover
171 * because of the use of the NMI stack. in_nmi reentrancy is tested in
172 * system_reset_exception.
174 lhz r10,PACA_IN_NMI(r13)
176 sth r10,PACA_IN_NMI(r13)
181 ld r1,PACA_NMI_EMERG_SP(r13)
182 subi r1,r1,INT_FRAME_SIZE
183 EXCEPTION_COMMON_STACK(PACA_EXNMI, 0x100)
186 * Set IRQS_ALL_DISABLED unconditionally so arch_irqs_disabled does
187 * the right thing. We do not want to reconcile because that goes
188 * through irq tracing which we don't want in NMI.
190 * Save PACAIRQHAPPENED because some code will do a hard disable
191 * (e.g., xmon). So we want to restore this back to where it was
192 * when we return. DAR is unused in the stack, so save it there.
194 li r10,IRQS_ALL_DISABLED
195 stb r10,PACAIRQSOFTMASK(r13)
196 lbz r10,PACAIRQHAPPENED(r13)
199 addi r3,r1,STACK_FRAME_OVERHEAD
200 bl system_reset_exception
202 /* This (and MCE) can be simplified with mtmsrd L=1 */
203 /* Clear MSR_RI before setting SRR0 and SRR1. */
210 * MSR_RI is clear, now we can decrement paca->in_nmi.
212 lhz r10,PACA_IN_NMI(r13)
214 sth r10,PACA_IN_NMI(r13)
217 * Restore soft mask settings.
220 stb r10,PACAIRQHAPPENED(r13)
222 stb r10,PACAIRQSOFTMASK(r13)
225 * Keep below code in synch with MACHINE_CHECK_HANDLER_WINDUP.
226 * Should share common bits...
229 /* Move original SRR0 and SRR1 into the respective regs */
247 /* restore original r1. */
249 RFI_TO_USER_OR_KERNEL
251 #ifdef CONFIG_PPC_PSERIES
253 * Vectors for the FWNMI option. Share common code.
255 TRAMP_REAL_BEGIN(system_reset_fwnmi)
256 SET_SCRATCH0(r13) /* save r13 */
257 /* See comment at system_reset exception */
258 EXCEPTION_PROLOG_NORI(PACA_EXNMI, system_reset_common, EXC_STD,
260 #endif /* CONFIG_PPC_PSERIES */
263 EXC_REAL_BEGIN(machine_check, 0x200, 0x100)
264 /* This is moved out of line as it can be patched by FW, but
265 * some code path might still want to branch into the original
268 SET_SCRATCH0(r13) /* save r13 */
269 EXCEPTION_PROLOG_0 PACA_EXMC
271 b machine_check_common_early
273 b machine_check_pSeries_0
274 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
275 EXC_REAL_END(machine_check, 0x200, 0x100)
276 EXC_VIRT_NONE(0x4200, 0x100)
277 TRAMP_REAL_BEGIN(machine_check_common_early)
278 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXMC, 0, 0x200, 0
283 * Original R9 to R13 is saved on PACA_EXMC
285 * Switch to mc_emergency stack and handle re-entrancy (we limit
286 * the nested MCE upto level 4 to avoid stack overflow).
287 * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1
289 * We use paca->in_mce to check whether this is the first entry or
290 * nested machine check. We increment paca->in_mce to track nested
293 * If this is the first entry then set stack pointer to
294 * paca->mc_emergency_sp, otherwise r1 is already pointing to
295 * stack frame on mc_emergency stack.
297 * NOTE: We are here with MSR_ME=0 (off), which means we risk a
298 * checkstop if we get another machine check exception before we do
299 * rfid with MSR_ME=1.
301 * This interrupt can wake directly from idle. If that is the case,
302 * the machine check is handled then the idle wakeup code is called
305 mr r11,r1 /* Save r1 */
306 lhz r10,PACA_IN_MCE(r13)
307 cmpwi r10,0 /* Are we in nested machine check */
308 bne 0f /* Yes, we are. */
309 /* First machine check entry */
310 ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */
311 0: subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
312 addi r10,r10,1 /* increment paca->in_mce */
313 sth r10,PACA_IN_MCE(r13)
314 /* Limit nested MCE to level 4 to avoid stack overflow */
315 cmpwi r10,MAX_MCE_DEPTH
316 bgt 2f /* Check if we hit limit of 4 */
317 std r11,GPR1(r1) /* Save r1 on the stack. */
318 std r11,0(r1) /* make stack chain pointer */
319 mfspr r11,SPRN_SRR0 /* Save SRR0 */
321 mfspr r11,SPRN_SRR1 /* Save SRR1 */
323 mfspr r11,SPRN_DAR /* Save DAR */
325 mfspr r11,SPRN_DSISR /* Save DSISR */
327 std r9,_CCR(r1) /* Save CR in stackframe */
328 /* We don't touch AMR here, we never go to virtual mode */
329 /* Save r9 through r13 from EXMC save area to stack frame. */
330 EXCEPTION_PROLOG_COMMON_2(PACA_EXMC)
331 mfmsr r11 /* get MSR value */
333 ori r11,r11,MSR_ME /* turn on ME bit */
334 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
335 ori r11,r11,MSR_RI /* turn on RI bit */
336 LOAD_HANDLER(r12, machine_check_handle_early)
337 1: mtspr SPRN_SRR0,r12
340 b . /* prevent speculative execution */
342 /* Stack overflow. Stay on emergency stack and panic.
343 * Keep the ME bit off while panic-ing, so that if we hit
344 * another machine check we checkstop.
346 addi r1,r1,INT_FRAME_SIZE /* go back to previous stack frame */
348 LOAD_HANDLER(r12, unrecover_mce)
350 andc r11,r11,r10 /* Turn off MSR_ME */
352 b . /* prevent speculative execution */
354 TRAMP_REAL_BEGIN(machine_check_pSeries)
355 .globl machine_check_fwnmi
357 SET_SCRATCH0(r13) /* save r13 */
358 EXCEPTION_PROLOG_0 PACA_EXMC
360 b machine_check_common_early
361 END_FTR_SECTION_IFCLR(CPU_FTR_HVMODE)
362 machine_check_pSeries_0:
363 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXMC, 1, 0x200, 0
365 * MSR_RI is not enabled, because PACA_EXMC is being used, so a
366 * nested machine check corrupts it. machine_check_common enables
369 EXCEPTION_PROLOG_2_REAL machine_check_common, EXC_STD, 0
371 TRAMP_KVM_SKIP(PACA_EXMC, 0x200)
373 EXC_COMMON_BEGIN(machine_check_common)
375 * Machine check is different because we use a different
376 * save area: PACA_EXMC instead of PACA_EXGEN.
379 std r10,PACA_EXMC+EX_DAR(r13)
381 stw r10,PACA_EXMC+EX_DSISR(r13)
382 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
384 RECONCILE_IRQ_STATE(r10, r11)
385 ld r3,PACA_EXMC+EX_DAR(r13)
386 lwz r4,PACA_EXMC+EX_DSISR(r13)
387 /* Enable MSR_RI when finished with PACA_EXMC */
393 addi r3,r1,STACK_FRAME_OVERHEAD
394 bl machine_check_exception
397 #define MACHINE_CHECK_HANDLER_WINDUP \
398 /* Clear MSR_RI before setting SRR0 and SRR1. */\
400 mfmsr r9; /* get MSR value */ \
402 mtmsrd r9,1; /* Clear MSR_RI */ \
403 /* Move original SRR0 and SRR1 into the respective regs */ \
405 mtspr SPRN_SRR1,r9; \
407 mtspr SPRN_SRR0,r3; \
419 /* Decrement paca->in_mce. */ \
420 lhz r12,PACA_IN_MCE(r13); \
422 sth r12,PACA_IN_MCE(r13); \
424 REST_2GPRS(12, r1); \
425 /* restore original r1. */ \
428 #ifdef CONFIG_PPC_P7_NAP
430 * This is an idle wakeup. Low level machine check has already been
431 * done. Queue the event then call the idle code to do the wake up.
433 EXC_COMMON_BEGIN(machine_check_idle_common)
434 bl machine_check_queue_event
437 * We have not used any non-volatile GPRs here, and as a rule
438 * most exception code including machine check does not.
439 * Therefore PACA_NAPSTATELOST does not need to be set. Idle
440 * wakeup will restore volatile registers.
442 * Load the original SRR1 into r3 for pnv_powersave_wakeup_mce.
444 * Then decrement MCE nesting after finishing with the stack.
449 lhz r11,PACA_IN_MCE(r13)
451 sth r11,PACA_IN_MCE(r13)
454 rlwinm r10,r3,47-31,30,31
456 bltlr cr1 /* no state loss, return to idle caller */
457 b idle_return_gpr_loss
460 * Handle machine check early in real mode. We come here with
461 * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack.
463 EXC_COMMON_BEGIN(machine_check_handle_early)
464 std r0,GPR0(r1) /* Save r0 */
465 EXCEPTION_PROLOG_COMMON_3(0x200)
467 addi r3,r1,STACK_FRAME_OVERHEAD
468 bl machine_check_early
469 std r3,RESULT(r1) /* Save result */
473 END_FTR_SECTION_IFCLR(CPU_FTR_HVMODE)
475 #ifdef CONFIG_PPC_P7_NAP
477 * Check if thread was in power saving mode. We come here when any
478 * of the following is true:
479 * a. thread wasn't in power saving mode
480 * b. thread was in power saving mode with no state loss,
481 * supervisor state loss or hypervisor state loss.
483 * Go back to nap/sleep/winkle mode again if (b) is true.
486 rlwinm. r11,r12,47-31,30,31
487 bne machine_check_idle_common
488 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
492 * Check if we are coming from hypervisor userspace. If yes then we
493 * continue in host kernel in V mode to deliver the MC event.
495 rldicl. r11,r12,4,63 /* See if MC hit while in HV mode. */
497 4: andi. r11,r12,MSR_PR /* See if coming from user. */
498 bne 9f /* continue in V mode if we are. */
501 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
504 * We are coming from kernel context. Check if we are coming from
505 * guest. if yes, then we can continue. We will fall through
506 * do_kvm_200->kvmppc_interrupt to deliver the MC event to guest.
508 lbz r11,HSTATE_IN_GUEST(r13)
509 cmpwi r11,0 /* Check if coming from guest */
510 bne 9f /* continue if we are. */
511 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
514 * At this point we are not sure about what context we come from.
515 * Queue up the MCE event and return from the interrupt.
516 * But before that, check if this is an un-recoverable exception.
517 * If yes, then stay on emergency stack and panic.
521 1: mfspr r11,SPRN_SRR0
522 LOAD_HANDLER(r10,unrecover_mce)
526 * We are going down. But there are chances that we might get hit by
527 * another MCE during panic path and we may run into unstable state
528 * with no way out. Hence, turn ME bit off while going down, so that
529 * when another MCE is hit during panic path, system will checkstop
530 * and hypervisor will get restarted cleanly by SP.
533 andc r10,r10,r3 /* Turn off MSR_ME */
539 * Check if we have successfully handled/recovered from error, if not
540 * then stay on emergency stack and panic.
542 ld r3,RESULT(r1) /* Load result */
543 cmpdi r3,0 /* see if we handled MCE successfully */
545 beq 1b /* if !handled then panic */
548 * Return from MC interrupt.
549 * Queue up the MCE event so that we can log it later, while
550 * returning from kernel or opal call.
552 bl machine_check_queue_event
553 MACHINE_CHECK_HANDLER_WINDUP
554 RFI_TO_USER_OR_KERNEL
557 * pSeries: Return from MC interrupt. Before that stay on emergency
558 * stack and call machine_check_exception to log the MCE event.
560 LOAD_HANDLER(r10,mce_return)
566 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
568 /* Deliver the machine check to host kernel in V mode. */
569 MACHINE_CHECK_HANDLER_WINDUP
570 SET_SCRATCH0(r13) /* save r13 */
571 EXCEPTION_PROLOG_0 PACA_EXMC
572 b machine_check_pSeries_0
574 EXC_COMMON_BEGIN(unrecover_mce)
575 /* Invoke machine_check_exception to print MCE event and panic. */
576 addi r3,r1,STACK_FRAME_OVERHEAD
577 bl machine_check_exception
579 * We will not reach here. Even if we did, there is no way out. Call
580 * unrecoverable_exception and die.
582 1: addi r3,r1,STACK_FRAME_OVERHEAD
583 bl unrecoverable_exception
586 EXC_COMMON_BEGIN(mce_return)
587 /* Invoke machine_check_exception to print MCE event and return. */
588 addi r3,r1,STACK_FRAME_OVERHEAD
589 bl machine_check_exception
590 MACHINE_CHECK_HANDLER_WINDUP
594 EXC_REAL_BEGIN(data_access, 0x300, 0x80)
595 SET_SCRATCH0(r13) /* save r13 */
596 EXCEPTION_PROLOG_0 PACA_EXGEN
597 b tramp_real_data_access
598 EXC_REAL_END(data_access, 0x300, 0x80)
600 TRAMP_REAL_BEGIN(tramp_real_data_access)
601 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x300, 0
603 * DAR/DSISR must be read before setting MSR[RI], because
604 * a d-side MCE will clobber those registers so is not
605 * recoverable if they are live.
609 std r10,PACA_EXGEN+EX_DAR(r13)
610 stw r11,PACA_EXGEN+EX_DSISR(r13)
611 EXCEPTION_PROLOG_2_REAL data_access_common, EXC_STD, 1
613 EXC_VIRT_BEGIN(data_access, 0x4300, 0x80)
614 SET_SCRATCH0(r13) /* save r13 */
615 EXCEPTION_PROLOG_0 PACA_EXGEN
616 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, 0x300, 0
619 std r10,PACA_EXGEN+EX_DAR(r13)
620 stw r11,PACA_EXGEN+EX_DSISR(r13)
621 EXCEPTION_PROLOG_2_VIRT data_access_common, EXC_STD
622 EXC_VIRT_END(data_access, 0x4300, 0x80)
624 TRAMP_KVM_SKIP(PACA_EXGEN, 0x300)
626 EXC_COMMON_BEGIN(data_access_common)
628 * Here r13 points to the paca, r9 contains the saved CR,
629 * SRR0 and SRR1 are saved in r11 and r12,
630 * r9 - r13 are saved in paca->exgen.
631 * EX_DAR and EX_DSISR have saved DAR/DSISR
633 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
634 RECONCILE_IRQ_STATE(r10, r11)
636 ld r3,PACA_EXGEN+EX_DAR(r13)
637 lwz r4,PACA_EXGEN+EX_DSISR(r13)
641 BEGIN_MMU_FTR_SECTION
642 b do_hash_page /* Try to handle as hpte fault */
645 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
648 EXC_REAL_BEGIN(data_access_slb, 0x380, 0x80)
649 SET_SCRATCH0(r13) /* save r13 */
650 EXCEPTION_PROLOG_0 PACA_EXSLB
651 b tramp_real_data_access_slb
652 EXC_REAL_END(data_access_slb, 0x380, 0x80)
654 TRAMP_REAL_BEGIN(tramp_real_data_access_slb)
655 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXSLB, 1, 0x380, 0
657 std r10,PACA_EXSLB+EX_DAR(r13)
658 EXCEPTION_PROLOG_2_REAL data_access_slb_common, EXC_STD, 1
660 EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80)
661 SET_SCRATCH0(r13) /* save r13 */
662 EXCEPTION_PROLOG_0 PACA_EXSLB
663 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXSLB, 0, 0x380, 0
665 std r10,PACA_EXSLB+EX_DAR(r13)
666 EXCEPTION_PROLOG_2_VIRT data_access_slb_common, EXC_STD
667 EXC_VIRT_END(data_access_slb, 0x4380, 0x80)
669 TRAMP_KVM_SKIP(PACA_EXSLB, 0x380)
671 EXC_COMMON_BEGIN(data_access_slb_common)
672 EXCEPTION_PROLOG_COMMON(0x380, PACA_EXSLB)
673 ld r4,PACA_EXSLB+EX_DAR(r13)
675 addi r3,r1,STACK_FRAME_OVERHEAD
676 BEGIN_MMU_FTR_SECTION
677 /* HPT case, do SLB fault */
681 b fast_exception_return
684 /* Radix case, access is outside page table range */
686 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
689 RECONCILE_IRQ_STATE(r10, r11)
692 addi r3,r1,STACK_FRAME_OVERHEAD
697 EXC_REAL(instruction_access, 0x400, 0x80)
698 EXC_VIRT(instruction_access, 0x4400, 0x80, 0x400)
699 TRAMP_KVM(PACA_EXGEN, 0x400)
701 EXC_COMMON_BEGIN(instruction_access_common)
702 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
703 RECONCILE_IRQ_STATE(r10, r11)
706 andis. r4,r12,DSISR_SRR1_MATCH_64S@h
710 BEGIN_MMU_FTR_SECTION
711 b do_hash_page /* Try to handle as hpte fault */
714 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
717 EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x80)
718 EXCEPTION_PROLOG(PACA_EXSLB, instruction_access_slb_common, EXC_STD, 1, 0x480);
719 EXC_REAL_END(instruction_access_slb, 0x480, 0x80)
721 EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x80)
722 EXCEPTION_RELON_PROLOG(PACA_EXSLB, instruction_access_slb_common, EXC_STD, 0, 0x480);
723 EXC_VIRT_END(instruction_access_slb, 0x4480, 0x80)
725 TRAMP_KVM(PACA_EXSLB, 0x480)
727 EXC_COMMON_BEGIN(instruction_access_slb_common)
728 EXCEPTION_PROLOG_COMMON(0x480, PACA_EXSLB)
730 addi r3,r1,STACK_FRAME_OVERHEAD
731 BEGIN_MMU_FTR_SECTION
732 /* HPT case, do SLB fault */
736 b fast_exception_return
739 /* Radix case, access is outside page table range */
741 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
744 RECONCILE_IRQ_STATE(r10, r11)
747 addi r3,r1,STACK_FRAME_OVERHEAD
752 EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x100)
753 .globl hardware_interrupt_hv;
754 hardware_interrupt_hv:
756 MASKABLE_EXCEPTION_HV(0x500, hardware_interrupt_common, IRQS_DISABLED)
758 MASKABLE_EXCEPTION(0x500, hardware_interrupt_common, IRQS_DISABLED)
759 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
760 EXC_REAL_END(hardware_interrupt, 0x500, 0x100)
762 EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x100)
763 .globl hardware_interrupt_relon_hv;
764 hardware_interrupt_relon_hv:
766 MASKABLE_RELON_EXCEPTION_HV(0x500, hardware_interrupt_common,
769 __MASKABLE_RELON_EXCEPTION(0x500, hardware_interrupt_common,
770 EXC_STD, 1, IRQS_DISABLED)
771 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
772 EXC_VIRT_END(hardware_interrupt, 0x4500, 0x100)
774 TRAMP_KVM(PACA_EXGEN, 0x500)
775 TRAMP_KVM_HV(PACA_EXGEN, 0x500)
776 EXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ)
779 EXC_REAL_BEGIN(alignment, 0x600, 0x100)
780 SET_SCRATCH0(r13) /* save r13 */
781 EXCEPTION_PROLOG_0 PACA_EXGEN
782 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x600, 0
785 std r10,PACA_EXGEN+EX_DAR(r13)
786 stw r11,PACA_EXGEN+EX_DSISR(r13)
787 EXCEPTION_PROLOG_2_REAL alignment_common, EXC_STD, 1
788 EXC_REAL_END(alignment, 0x600, 0x100)
790 EXC_VIRT_BEGIN(alignment, 0x4600, 0x100)
791 SET_SCRATCH0(r13) /* save r13 */
792 EXCEPTION_PROLOG_0 PACA_EXGEN
793 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, 0x600, 0
796 std r10,PACA_EXGEN+EX_DAR(r13)
797 stw r11,PACA_EXGEN+EX_DSISR(r13)
798 EXCEPTION_PROLOG_2_VIRT alignment_common, EXC_STD
799 EXC_VIRT_END(alignment, 0x4600, 0x100)
801 TRAMP_KVM(PACA_EXGEN, 0x600)
802 EXC_COMMON_BEGIN(alignment_common)
803 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
804 ld r3,PACA_EXGEN+EX_DAR(r13)
805 lwz r4,PACA_EXGEN+EX_DSISR(r13)
809 RECONCILE_IRQ_STATE(r10, r11)
810 addi r3,r1,STACK_FRAME_OVERHEAD
811 bl alignment_exception
815 EXC_REAL(program_check, 0x700, 0x100)
816 EXC_VIRT(program_check, 0x4700, 0x100, 0x700)
817 TRAMP_KVM(PACA_EXGEN, 0x700)
818 EXC_COMMON_BEGIN(program_check_common)
820 * It's possible to receive a TM Bad Thing type program check with
821 * userspace register values (in particular r1), but with SRR1 reporting
822 * that we came from the kernel. Normally that would confuse the bad
823 * stack logic, and we would report a bad kernel stack pointer. Instead
824 * we switch to the emergency stack if we're taking a TM Bad Thing from
827 li r10,MSR_PR /* Build a mask of MSR_PR .. */
828 oris r10,r10,0x200000@h /* .. and SRR1_PROGTM */
829 and r10,r10,r12 /* Mask SRR1 with that. */
830 srdi r10,r10,8 /* Shift it so we can compare */
831 cmpldi r10,(0x200000 >> 8) /* .. with an immediate. */
832 bne 1f /* If != go to normal path. */
834 /* SRR1 had PR=0 and SRR1_PROGTM=1, so use the emergency stack */
835 andi. r10,r12,MSR_PR; /* Set CR0 correctly for label */
836 /* 3 in EXCEPTION_PROLOG_COMMON */
837 mr r10,r1 /* Save r1 */
838 ld r1,PACAEMERGSP(r13) /* Use emergency stack */
839 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
840 b 3f /* Jump into the macro !! */
841 1: EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
843 RECONCILE_IRQ_STATE(r10, r11)
844 addi r3,r1,STACK_FRAME_OVERHEAD
845 bl program_check_exception
849 EXC_REAL(fp_unavailable, 0x800, 0x100)
850 EXC_VIRT(fp_unavailable, 0x4800, 0x100, 0x800)
851 TRAMP_KVM(PACA_EXGEN, 0x800)
852 EXC_COMMON_BEGIN(fp_unavailable_common)
853 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
854 bne 1f /* if from user, just load it up */
856 RECONCILE_IRQ_STATE(r10, r11)
857 addi r3,r1,STACK_FRAME_OVERHEAD
858 bl kernel_fp_unavailable_exception
861 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
863 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
864 * transaction), go do TM stuff
866 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
868 END_FTR_SECTION_IFSET(CPU_FTR_TM)
871 b fast_exception_return
872 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
873 2: /* User process was in a transaction */
875 RECONCILE_IRQ_STATE(r10, r11)
876 addi r3,r1,STACK_FRAME_OVERHEAD
882 EXC_REAL_OOL_MASKABLE(decrementer, 0x900, 0x80, IRQS_DISABLED)
883 EXC_VIRT_MASKABLE(decrementer, 0x4900, 0x80, 0x900, IRQS_DISABLED)
884 TRAMP_KVM(PACA_EXGEN, 0x900)
885 EXC_COMMON_ASYNC(decrementer_common, 0x900, timer_interrupt)
888 EXC_REAL_HV(hdecrementer, 0x980, 0x80)
889 EXC_VIRT_HV(hdecrementer, 0x4980, 0x80, 0x980)
890 TRAMP_KVM_HV(PACA_EXGEN, 0x980)
891 EXC_COMMON(hdecrementer_common, 0x980, hdec_interrupt)
894 EXC_REAL_MASKABLE(doorbell_super, 0xa00, 0x100, IRQS_DISABLED)
895 EXC_VIRT_MASKABLE(doorbell_super, 0x4a00, 0x100, 0xa00, IRQS_DISABLED)
896 TRAMP_KVM(PACA_EXGEN, 0xa00)
897 #ifdef CONFIG_PPC_DOORBELL
898 EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, doorbell_exception)
900 EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, unknown_exception)
904 EXC_REAL(trap_0b, 0xb00, 0x100)
905 EXC_VIRT(trap_0b, 0x4b00, 0x100, 0xb00)
906 TRAMP_KVM(PACA_EXGEN, 0xb00)
907 EXC_COMMON(trap_0b_common, 0xb00, unknown_exception)
910 * system call / hypercall (0xc00, 0x4c00)
912 * The system call exception is invoked with "sc 0" and does not alter HV bit.
913 * There is support for kernel code to invoke system calls but there are no
916 * The hypercall is invoked with "sc 1" and sets HV=1.
918 * In HPT, sc 1 always goes to 0xc00 real mode. In RADIX, sc 1 can go to
919 * 0x4c00 virtual mode.
923 * syscall register convention is in Documentation/powerpc/syscall64-abi.txt
925 * For hypercalls, the register convention is as follows:
928 * r3 volatile parameter and return value for status
929 * r4-r10 volatile input and output value
930 * r11 volatile hypercall number and output value
931 * r12 volatile input and output value
932 * r13-r31 nonvolatile
936 * CR0-1 CR5-7 volatile
938 * Other registers nonvolatile
940 * The intersection of volatile registers that don't contain possible
941 * inputs is: cr0, xer, ctr. We may use these as scratch regs upon entry
942 * without saving, though xer is not a good idea to use, as hardware may
943 * interpret some bits so it may be costly to change them.
945 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
947 * There is a little bit of juggling to get syscall and hcall
948 * working well. Save r13 in ctr to avoid using SPRG scratch
951 * Userspace syscalls have already saved the PPR, hcalls must save
952 * it before setting HMT_MEDIUM.
954 #define SYSCALL_KVMTEST \
957 std r10,PACA_EXGEN+EX_R10(r13); \
958 INTERRUPT_TO_KERNEL; \
959 KVMTEST EXC_STD 0xc00 ; /* uses r10, branch to do_kvm_0xc00_system_call */ \
964 #define SYSCALL_KVMTEST \
971 #define LOAD_SYSCALL_HANDLER(reg) \
972 __LOAD_HANDLER(reg, system_call_common)
975 * After SYSCALL_KVMTEST, we reach here with PACA in r13, r13 in r9,
978 #define SYSCALL_REAL \
979 mfspr r11,SPRN_SRR0 ; \
980 mfspr r12,SPRN_SRR1 ; \
981 LOAD_SYSCALL_HANDLER(r10) ; \
982 mtspr SPRN_SRR0,r10 ; \
983 ld r10,PACAKMSR(r13) ; \
984 mtspr SPRN_SRR1,r10 ; \
986 b . ; /* prevent speculative execution */
988 #ifdef CONFIG_PPC_FAST_ENDIAN_SWITCH
989 #define SYSCALL_FASTENDIAN_TEST \
993 END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) \
995 #define SYSCALL_FASTENDIAN \
996 /* Fast LE/BE switch system call */ \
997 1: mfspr r12,SPRN_SRR1 ; \
998 xori r12,r12,MSR_LE ; \
999 mtspr SPRN_SRR1,r12 ; \
1001 RFI_TO_USER ; /* return to userspace */ \
1002 b . ; /* prevent speculative execution */
1004 #define SYSCALL_FASTENDIAN_TEST
1005 #define SYSCALL_FASTENDIAN
1006 #endif /* CONFIG_PPC_FAST_ENDIAN_SWITCH */
1008 #if defined(CONFIG_RELOCATABLE)
1010 * We can't branch directly so we do it via the CTR which
1011 * is volatile across system calls.
1013 #define SYSCALL_VIRT \
1014 LOAD_SYSCALL_HANDLER(r10) ; \
1016 mfspr r11,SPRN_SRR0 ; \
1017 mfspr r12,SPRN_SRR1 ; \
1022 /* We can branch directly */
1023 #define SYSCALL_VIRT \
1024 mfspr r11,SPRN_SRR0 ; \
1025 mfspr r12,SPRN_SRR1 ; \
1027 mtmsrd r10,1 ; /* Set RI (EE=0) */ \
1028 b system_call_common ;
1031 EXC_REAL_BEGIN(system_call, 0xc00, 0x100)
1032 SYSCALL_KVMTEST /* loads PACA into r13, and saves r13 to r9 */
1033 SYSCALL_FASTENDIAN_TEST
1036 EXC_REAL_END(system_call, 0xc00, 0x100)
1038 EXC_VIRT_BEGIN(system_call, 0x4c00, 0x100)
1039 SYSCALL_KVMTEST /* loads PACA into r13, and saves r13 to r9 */
1040 SYSCALL_FASTENDIAN_TEST
1043 EXC_VIRT_END(system_call, 0x4c00, 0x100)
1045 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
1047 * This is a hcall, so register convention is as above, with these
1051 * orig r10 saved in PACA
1053 TRAMP_KVM_BEGIN(do_kvm_0xc00)
1055 * Save the PPR (on systems that support it) before changing to
1056 * HMT_MEDIUM. That allows the KVM code to save that value into the
1057 * guest state (it is the guest's PPR value).
1059 OPT_GET_SPR(r10, SPRN_PPR, CPU_FTR_HAS_PPR)
1061 OPT_SAVE_REG_TO_PACA(PACA_EXGEN+EX_PPR, r10, CPU_FTR_HAS_PPR)
1064 std r9,PACA_EXGEN+EX_R9(r13)
1066 KVM_HANDLER PACA_EXGEN, EXC_STD, 0xc00, 0
1070 EXC_REAL(single_step, 0xd00, 0x100)
1071 EXC_VIRT(single_step, 0x4d00, 0x100, 0xd00)
1072 TRAMP_KVM(PACA_EXGEN, 0xd00)
1073 EXC_COMMON(single_step_common, 0xd00, single_step_exception)
1075 EXC_REAL_OOL_HV(h_data_storage, 0xe00, 0x20)
1076 EXC_VIRT_OOL_HV(h_data_storage, 0x4e00, 0x20, 0xe00)
1077 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0xe00)
1078 EXC_COMMON_BEGIN(h_data_storage_common)
1080 std r10,PACA_EXGEN+EX_DAR(r13)
1081 mfspr r10,SPRN_HDSISR
1082 stw r10,PACA_EXGEN+EX_DSISR(r13)
1083 EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN)
1085 RECONCILE_IRQ_STATE(r10, r11)
1086 addi r3,r1,STACK_FRAME_OVERHEAD
1087 BEGIN_MMU_FTR_SECTION
1088 ld r4,PACA_EXGEN+EX_DAR(r13)
1089 lwz r5,PACA_EXGEN+EX_DSISR(r13)
1094 MMU_FTR_SECTION_ELSE
1095 bl unknown_exception
1096 ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_TYPE_RADIX)
1100 EXC_REAL_OOL_HV(h_instr_storage, 0xe20, 0x20)
1101 EXC_VIRT_OOL_HV(h_instr_storage, 0x4e20, 0x20, 0xe20)
1102 TRAMP_KVM_HV(PACA_EXGEN, 0xe20)
1103 EXC_COMMON(h_instr_storage_common, 0xe20, unknown_exception)
1106 EXC_REAL_OOL_HV(emulation_assist, 0xe40, 0x20)
1107 EXC_VIRT_OOL_HV(emulation_assist, 0x4e40, 0x20, 0xe40)
1108 TRAMP_KVM_HV(PACA_EXGEN, 0xe40)
1109 EXC_COMMON(emulation_assist_common, 0xe40, emulation_assist_interrupt)
1113 * hmi_exception trampoline is a special case. It jumps to hmi_exception_early
1114 * first, and then eventaully from there to the trampoline to get into virtual
1117 __EXC_REAL_OOL_HV_DIRECT(hmi_exception, 0xe60, 0x20, hmi_exception_early)
1118 __TRAMP_REAL_OOL_MASKABLE_HV(hmi_exception, 0xe60, IRQS_DISABLED)
1119 EXC_VIRT_NONE(0x4e60, 0x20)
1120 TRAMP_KVM_HV(PACA_EXGEN, 0xe60)
1121 TRAMP_REAL_BEGIN(hmi_exception_early)
1122 EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, 0xe60, 0
1123 mr r10,r1 /* Save r1 */
1124 ld r1,PACAEMERGSP(r13) /* Use emergency stack for realmode */
1125 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
1126 mfspr r11,SPRN_HSRR0 /* Save HSRR0 */
1127 mfspr r12,SPRN_HSRR1 /* Save HSRR1 */
1128 EXCEPTION_PROLOG_COMMON_1()
1129 /* We don't touch AMR here, we never go to virtual mode */
1130 EXCEPTION_PROLOG_COMMON_2(PACA_EXGEN)
1131 EXCEPTION_PROLOG_COMMON_3(0xe60)
1132 addi r3,r1,STACK_FRAME_OVERHEAD
1133 BRANCH_LINK_TO_FAR(DOTSYM(hmi_exception_realmode)) /* Function call ABI */
1136 /* Windup the stack. */
1137 /* Move original HSRR0 and HSRR1 into the respective regs */
1157 HRFI_TO_USER_OR_KERNEL
1164 * Go to virtual mode and pull the HMI event information from
1167 .globl hmi_exception_after_realmode
1168 hmi_exception_after_realmode:
1170 EXCEPTION_PROLOG_0 PACA_EXGEN
1171 b tramp_real_hmi_exception
1173 EXC_COMMON_BEGIN(hmi_exception_common)
1174 EXCEPTION_COMMON(PACA_EXGEN, 0xe60)
1177 RECONCILE_IRQ_STATE(r10, r11)
1179 addi r3,r1,STACK_FRAME_OVERHEAD
1180 bl handle_hmi_exception
1183 EXC_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80, 0x20, IRQS_DISABLED)
1184 EXC_VIRT_OOL_MASKABLE_HV(h_doorbell, 0x4e80, 0x20, 0xe80, IRQS_DISABLED)
1185 TRAMP_KVM_HV(PACA_EXGEN, 0xe80)
1186 #ifdef CONFIG_PPC_DOORBELL
1187 EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, doorbell_exception)
1189 EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, unknown_exception)
1193 EXC_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0, 0x20, IRQS_DISABLED)
1194 EXC_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0x4ea0, 0x20, 0xea0, IRQS_DISABLED)
1195 TRAMP_KVM_HV(PACA_EXGEN, 0xea0)
1196 EXC_COMMON_ASYNC(h_virt_irq_common, 0xea0, do_IRQ)
1199 EXC_REAL_NONE(0xec0, 0x20)
1200 EXC_VIRT_NONE(0x4ec0, 0x20)
1201 EXC_REAL_NONE(0xee0, 0x20)
1202 EXC_VIRT_NONE(0x4ee0, 0x20)
1205 EXC_REAL_OOL_MASKABLE(performance_monitor, 0xf00, 0x20, IRQS_PMI_DISABLED)
1206 EXC_VIRT_OOL_MASKABLE(performance_monitor, 0x4f00, 0x20, 0xf00, IRQS_PMI_DISABLED)
1207 TRAMP_KVM(PACA_EXGEN, 0xf00)
1208 EXC_COMMON_ASYNC(performance_monitor_common, 0xf00, performance_monitor_exception)
1211 EXC_REAL_OOL(altivec_unavailable, 0xf20, 0x20)
1212 EXC_VIRT_OOL(altivec_unavailable, 0x4f20, 0x20, 0xf20)
1213 TRAMP_KVM(PACA_EXGEN, 0xf20)
1214 EXC_COMMON_BEGIN(altivec_unavailable_common)
1215 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN)
1216 #ifdef CONFIG_ALTIVEC
1219 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1220 BEGIN_FTR_SECTION_NESTED(69)
1221 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
1222 * transaction), go do TM stuff
1224 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
1226 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
1229 b fast_exception_return
1230 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1231 2: /* User process was in a transaction */
1233 RECONCILE_IRQ_STATE(r10, r11)
1234 addi r3,r1,STACK_FRAME_OVERHEAD
1235 bl altivec_unavailable_tm
1239 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1242 RECONCILE_IRQ_STATE(r10, r11)
1243 addi r3,r1,STACK_FRAME_OVERHEAD
1244 bl altivec_unavailable_exception
1248 EXC_REAL_OOL(vsx_unavailable, 0xf40, 0x20)
1249 EXC_VIRT_OOL(vsx_unavailable, 0x4f40, 0x20, 0xf40)
1250 TRAMP_KVM(PACA_EXGEN, 0xf40)
1251 EXC_COMMON_BEGIN(vsx_unavailable_common)
1252 EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN)
1256 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1257 BEGIN_FTR_SECTION_NESTED(69)
1258 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
1259 * transaction), go do TM stuff
1261 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
1263 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
1266 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1267 2: /* User process was in a transaction */
1269 RECONCILE_IRQ_STATE(r10, r11)
1270 addi r3,r1,STACK_FRAME_OVERHEAD
1271 bl vsx_unavailable_tm
1275 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
1278 RECONCILE_IRQ_STATE(r10, r11)
1279 addi r3,r1,STACK_FRAME_OVERHEAD
1280 bl vsx_unavailable_exception
1284 EXC_REAL_OOL(facility_unavailable, 0xf60, 0x20)
1285 EXC_VIRT_OOL(facility_unavailable, 0x4f60, 0x20, 0xf60)
1286 TRAMP_KVM(PACA_EXGEN, 0xf60)
1287 EXC_COMMON(facility_unavailable_common, 0xf60, facility_unavailable_exception)
1290 EXC_REAL_OOL_HV(h_facility_unavailable, 0xf80, 0x20)
1291 EXC_VIRT_OOL_HV(h_facility_unavailable, 0x4f80, 0x20, 0xf80)
1292 TRAMP_KVM_HV(PACA_EXGEN, 0xf80)
1293 EXC_COMMON(h_facility_unavailable_common, 0xf80, facility_unavailable_exception)
1296 EXC_REAL_NONE(0xfa0, 0x20)
1297 EXC_VIRT_NONE(0x4fa0, 0x20)
1298 EXC_REAL_NONE(0xfc0, 0x20)
1299 EXC_VIRT_NONE(0x4fc0, 0x20)
1300 EXC_REAL_NONE(0xfe0, 0x20)
1301 EXC_VIRT_NONE(0x4fe0, 0x20)
1303 EXC_REAL_NONE(0x1000, 0x100)
1304 EXC_VIRT_NONE(0x5000, 0x100)
1305 EXC_REAL_NONE(0x1100, 0x100)
1306 EXC_VIRT_NONE(0x5100, 0x100)
1308 #ifdef CONFIG_CBE_RAS
1309 EXC_REAL_HV(cbe_system_error, 0x1200, 0x100)
1310 EXC_VIRT_NONE(0x5200, 0x100)
1311 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1200)
1312 EXC_COMMON(cbe_system_error_common, 0x1200, cbe_system_error_exception)
1313 #else /* CONFIG_CBE_RAS */
1314 EXC_REAL_NONE(0x1200, 0x100)
1315 EXC_VIRT_NONE(0x5200, 0x100)
1319 EXC_REAL(instruction_breakpoint, 0x1300, 0x100)
1320 EXC_VIRT(instruction_breakpoint, 0x5300, 0x100, 0x1300)
1321 TRAMP_KVM_SKIP(PACA_EXGEN, 0x1300)
1322 EXC_COMMON(instruction_breakpoint_common, 0x1300, instruction_breakpoint_exception)
1324 EXC_REAL_NONE(0x1400, 0x100)
1325 EXC_VIRT_NONE(0x5400, 0x100)
1327 EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x100)
1328 mtspr SPRN_SPRG_HSCRATCH0,r13
1329 EXCEPTION_PROLOG_0 PACA_EXGEN
1330 EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 0, 0x1500, 0
1332 #ifdef CONFIG_PPC_DENORMALISATION
1333 mfspr r10,SPRN_HSRR1
1334 andis. r10,r10,(HSRR1_DENORM)@h /* denorm? */
1338 KVMTEST EXC_HV 0x1500
1339 EXCEPTION_PROLOG_2_REAL denorm_common, EXC_HV, 1
1340 EXC_REAL_END(denorm_exception_hv, 0x1500, 0x100)
1342 #ifdef CONFIG_PPC_DENORMALISATION
1343 EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x100)
1344 b exc_real_0x1500_denorm_exception_hv
1345 EXC_VIRT_END(denorm_exception, 0x5500, 0x100)
1347 EXC_VIRT_NONE(0x5500, 0x100)
1350 TRAMP_KVM_HV(PACA_EXGEN, 0x1500)
1352 #ifdef CONFIG_PPC_DENORMALISATION
1353 TRAMP_REAL_BEGIN(denorm_assist)
1356 * To denormalise we need to move a copy of the register to itself.
1357 * For POWER6 do that here for all FP regs.
1360 ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1)
1361 xori r10,r10,(MSR_FE0|MSR_FE1)
1365 #define FMR2(n) fmr (n), (n) ; fmr n+1, n+1
1366 #define FMR4(n) FMR2(n) ; FMR2(n+2)
1367 #define FMR8(n) FMR4(n) ; FMR4(n+4)
1368 #define FMR16(n) FMR8(n) ; FMR8(n+8)
1369 #define FMR32(n) FMR16(n) ; FMR16(n+16)
1374 * To denormalise we need to move a copy of the register to itself.
1375 * For POWER7 do that here for the first 32 VSX registers only.
1378 oris r10,r10,MSR_VSX@h
1382 #define XVCPSGNDP2(n) XVCPSGNDP(n,n,n) ; XVCPSGNDP(n+1,n+1,n+1)
1383 #define XVCPSGNDP4(n) XVCPSGNDP2(n) ; XVCPSGNDP2(n+2)
1384 #define XVCPSGNDP8(n) XVCPSGNDP4(n) ; XVCPSGNDP4(n+4)
1385 #define XVCPSGNDP16(n) XVCPSGNDP8(n) ; XVCPSGNDP8(n+8)
1386 #define XVCPSGNDP32(n) XVCPSGNDP16(n) ; XVCPSGNDP16(n+16)
1389 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206)
1393 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
1395 * To denormalise we need to move a copy of the register to itself.
1396 * For POWER8 we need to do that for all 64 VSX registers
1400 mfspr r11,SPRN_HSRR0
1402 mtspr SPRN_HSRR0,r11
1404 ld r9,PACA_EXGEN+EX_R9(r13)
1405 RESTORE_PPR_PACA(PACA_EXGEN, r10)
1407 ld r10,PACA_EXGEN+EX_CFAR(r13)
1409 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1410 ld r10,PACA_EXGEN+EX_R10(r13)
1411 ld r11,PACA_EXGEN+EX_R11(r13)
1412 ld r12,PACA_EXGEN+EX_R12(r13)
1413 ld r13,PACA_EXGEN+EX_R13(r13)
1418 EXC_COMMON(denorm_common, 0x1500, unknown_exception)
1421 #ifdef CONFIG_CBE_RAS
1422 EXC_REAL_HV(cbe_maintenance, 0x1600, 0x100)
1423 EXC_VIRT_NONE(0x5600, 0x100)
1424 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1600)
1425 EXC_COMMON(cbe_maintenance_common, 0x1600, cbe_maintenance_exception)
1426 #else /* CONFIG_CBE_RAS */
1427 EXC_REAL_NONE(0x1600, 0x100)
1428 EXC_VIRT_NONE(0x5600, 0x100)
1432 EXC_REAL(altivec_assist, 0x1700, 0x100)
1433 EXC_VIRT(altivec_assist, 0x5700, 0x100, 0x1700)
1434 TRAMP_KVM(PACA_EXGEN, 0x1700)
1435 #ifdef CONFIG_ALTIVEC
1436 EXC_COMMON(altivec_assist_common, 0x1700, altivec_assist_exception)
1438 EXC_COMMON(altivec_assist_common, 0x1700, unknown_exception)
1442 #ifdef CONFIG_CBE_RAS
1443 EXC_REAL_HV(cbe_thermal, 0x1800, 0x100)
1444 EXC_VIRT_NONE(0x5800, 0x100)
1445 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1800)
1446 EXC_COMMON(cbe_thermal_common, 0x1800, cbe_thermal_exception)
1447 #else /* CONFIG_CBE_RAS */
1448 EXC_REAL_NONE(0x1800, 0x100)
1449 EXC_VIRT_NONE(0x5800, 0x100)
1452 #ifdef CONFIG_PPC_WATCHDOG
1454 #define MASKED_DEC_HANDLER_LABEL 3f
1456 #define MASKED_DEC_HANDLER(_H) \
1458 std r12,PACA_EXGEN+EX_R12(r13); \
1459 GET_SCRATCH0(r10); \
1460 std r10,PACA_EXGEN+EX_R13(r13); \
1461 EXCEPTION_PROLOG_2_REAL soft_nmi_common, _H, 1
1464 * Branch to soft_nmi_interrupt using the emergency stack. The emergency
1465 * stack is one that is usable by maskable interrupts so long as MSR_EE
1466 * remains off. It is used for recovery when something has corrupted the
1467 * normal kernel stack, for example. The "soft NMI" must not use the process
1468 * stack because we want irq disabled sections to avoid touching the stack
1469 * at all (other than PMU interrupts), so use the emergency stack for this,
1470 * and run it entirely with interrupts hard disabled.
1472 EXC_COMMON_BEGIN(soft_nmi_common)
1474 ld r1,PACAEMERGSP(r13)
1475 subi r1,r1,INT_FRAME_SIZE
1476 EXCEPTION_COMMON_STACK(PACA_EXGEN, 0x900)
1478 RECONCILE_IRQ_STATE(r10, r11)
1479 addi r3,r1,STACK_FRAME_OVERHEAD
1480 bl soft_nmi_interrupt
1483 #else /* CONFIG_PPC_WATCHDOG */
1484 #define MASKED_DEC_HANDLER_LABEL 2f /* normal return */
1485 #define MASKED_DEC_HANDLER(_H)
1486 #endif /* CONFIG_PPC_WATCHDOG */
1489 * An interrupt came in while soft-disabled. We set paca->irq_happened, then:
1490 * - If it was a decrementer interrupt, we bump the dec to max and and return.
1491 * - If it was a doorbell we return immediately since doorbells are edge
1492 * triggered and won't automatically refire.
1493 * - If it was a HMI we return immediately since we handled it in realmode
1494 * and it won't refire.
1495 * - Else it is one of PACA_IRQ_MUST_HARD_MASK, so hard disable and return.
1496 * This is called with r10 containing the value to OR to the paca field.
1498 .macro MASKED_INTERRUPT hsrr
1504 std r11,PACA_EXGEN+EX_R11(r13)
1505 lbz r11,PACAIRQHAPPENED(r13)
1507 stb r11,PACAIRQHAPPENED(r13)
1508 cmpwi r10,PACA_IRQ_DEC
1513 b MASKED_DEC_HANDLER_LABEL
1514 1: andi. r10,r10,PACA_IRQ_MUST_HARD_MASK
1517 mfspr r10,SPRN_HSRR1
1518 xori r10,r10,MSR_EE /* clear MSR_EE */
1519 mtspr SPRN_HSRR1,r10
1522 xori r10,r10,MSR_EE /* clear MSR_EE */
1525 ori r11,r11,PACA_IRQ_HARD_DIS
1526 stb r11,PACAIRQHAPPENED(r13)
1530 ld r9,PACA_EXGEN+EX_R9(r13)
1531 ld r10,PACA_EXGEN+EX_R10(r13)
1532 ld r11,PACA_EXGEN+EX_R11(r13)
1533 /* returns to kernel where r13 must be set up, so don't restore it */
1540 MASKED_DEC_HANDLER(\hsrr\())
1543 TRAMP_REAL_BEGIN(stf_barrier_fallback)
1544 std r9,PACA_EXRFI+EX_R9(r13)
1545 std r10,PACA_EXRFI+EX_R10(r13)
1547 ld r9,PACA_EXRFI+EX_R9(r13)
1548 ld r10,PACA_EXRFI+EX_R10(r13)
1556 TRAMP_REAL_BEGIN(rfi_flush_fallback)
1559 std r1,PACA_EXRFI+EX_R12(r13)
1560 ld r1,PACAKSAVE(r13)
1561 std r9,PACA_EXRFI+EX_R9(r13)
1562 std r10,PACA_EXRFI+EX_R10(r13)
1563 std r11,PACA_EXRFI+EX_R11(r13)
1565 ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13)
1566 ld r11,PACA_L1D_FLUSH_SIZE(r13)
1567 srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */
1569 DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */
1571 /* order ld/st prior to dcbt stop all streams with flushing */
1575 * The load adresses are at staggered offsets within cachelines,
1576 * which suits some pipelines better (on others it should not
1580 ld r11,(0x80 + 8)*0(r10)
1581 ld r11,(0x80 + 8)*1(r10)
1582 ld r11,(0x80 + 8)*2(r10)
1583 ld r11,(0x80 + 8)*3(r10)
1584 ld r11,(0x80 + 8)*4(r10)
1585 ld r11,(0x80 + 8)*5(r10)
1586 ld r11,(0x80 + 8)*6(r10)
1587 ld r11,(0x80 + 8)*7(r10)
1592 ld r9,PACA_EXRFI+EX_R9(r13)
1593 ld r10,PACA_EXRFI+EX_R10(r13)
1594 ld r11,PACA_EXRFI+EX_R11(r13)
1595 ld r1,PACA_EXRFI+EX_R12(r13)
1599 TRAMP_REAL_BEGIN(hrfi_flush_fallback)
1602 std r1,PACA_EXRFI+EX_R12(r13)
1603 ld r1,PACAKSAVE(r13)
1604 std r9,PACA_EXRFI+EX_R9(r13)
1605 std r10,PACA_EXRFI+EX_R10(r13)
1606 std r11,PACA_EXRFI+EX_R11(r13)
1608 ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13)
1609 ld r11,PACA_L1D_FLUSH_SIZE(r13)
1610 srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */
1612 DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */
1614 /* order ld/st prior to dcbt stop all streams with flushing */
1618 * The load adresses are at staggered offsets within cachelines,
1619 * which suits some pipelines better (on others it should not
1623 ld r11,(0x80 + 8)*0(r10)
1624 ld r11,(0x80 + 8)*1(r10)
1625 ld r11,(0x80 + 8)*2(r10)
1626 ld r11,(0x80 + 8)*3(r10)
1627 ld r11,(0x80 + 8)*4(r10)
1628 ld r11,(0x80 + 8)*5(r10)
1629 ld r11,(0x80 + 8)*6(r10)
1630 ld r11,(0x80 + 8)*7(r10)
1635 ld r9,PACA_EXRFI+EX_R9(r13)
1636 ld r10,PACA_EXRFI+EX_R10(r13)
1637 ld r11,PACA_EXRFI+EX_R11(r13)
1638 ld r1,PACA_EXRFI+EX_R12(r13)
1643 * Real mode exceptions actually use this too, but alternate
1644 * instruction code patches (which end up in the common .text area)
1645 * cannot reach these if they are put there.
1647 USE_FIXED_SECTION(virt_trampolines)
1648 MASKED_INTERRUPT EXC_STD
1649 MASKED_INTERRUPT EXC_HV
1651 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
1652 TRAMP_REAL_BEGIN(kvmppc_skip_interrupt)
1654 * Here all GPRs are unchanged from when the interrupt happened
1655 * except for r13, which is saved in SPRG_SCRATCH0.
1657 mfspr r13, SPRN_SRR0
1659 mtspr SPRN_SRR0, r13
1664 TRAMP_REAL_BEGIN(kvmppc_skip_Hinterrupt)
1666 * Here all GPRs are unchanged from when the interrupt happened
1667 * except for r13, which is saved in SPRG_SCRATCH0.
1669 mfspr r13, SPRN_HSRR0
1671 mtspr SPRN_HSRR0, r13
1678 * Ensure that any handlers that get invoked from the exception prologs
1679 * above are below the first 64KB (0x10000) of the kernel image because
1680 * the prologs assemble the addresses of these handlers using the
1681 * LOAD_HANDLER macro, which uses an ori instruction.
1684 /*** Common interrupt handlers ***/
1688 * Relocation-on interrupts: A subset of the interrupts can be delivered
1689 * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering
1690 * it. Addresses are the same as the original interrupt addresses, but
1691 * offset by 0xc000000000004000.
1692 * It's impossible to receive interrupts below 0x300 via this mechanism.
1693 * KVM: None of these traps are from the guest ; anything that escalated
1694 * to HV=1 from HV=0 is delivered via real mode handlers.
1698 * This uses the standard macro, since the original 0x300 vector
1699 * only has extra guff for STAB-based processors -- which never
1703 EXC_COMMON_BEGIN(ppc64_runlatch_on_trampoline)
1704 b __ppc64_runlatch_on
1706 USE_FIXED_SECTION(virt_trampolines)
1708 * The __end_interrupts marker must be past the out-of-line (OOL)
1709 * handlers, so that they are copied to real address 0x100 when running
1710 * a relocatable kernel. This ensures they can be reached from the short
1711 * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch
1712 * directly, without using LOAD_HANDLER().
1715 .globl __end_interrupts
1717 DEFINE_FIXED_SYMBOL(__end_interrupts)
1719 #ifdef CONFIG_PPC_970_NAP
1720 EXC_COMMON_BEGIN(power4_fixup_nap)
1722 std r9,TI_LOCAL_FLAGS(r11)
1723 ld r10,_LINK(r1) /* make idle task do the */
1724 std r10,_NIP(r1) /* equivalent of a blr */
1728 CLOSE_FIXED_SECTION(real_vectors);
1729 CLOSE_FIXED_SECTION(real_trampolines);
1730 CLOSE_FIXED_SECTION(virt_vectors);
1731 CLOSE_FIXED_SECTION(virt_trampolines);
1738 .balign IFETCH_ALIGN_BYTES
1740 #ifdef CONFIG_PPC_BOOK3S_64
1741 lis r0,(DSISR_BAD_FAULT_64S | DSISR_DABRMATCH | DSISR_KEYFAULT)@h
1742 ori r0,r0,DSISR_BAD_FAULT_64S@l
1743 and. r0,r4,r0 /* weird error? */
1744 bne- handle_page_fault /* if not, try to insert a HPTE */
1745 ld r11, PACA_THREAD_INFO(r13)
1746 lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */
1747 andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */
1748 bne 77f /* then don't call hash_page now */
1751 * r3 contains the faulting address
1753 * r5 contains the trap number
1756 * at return r3 = 0 for success, 1 for page fault, negative for error
1760 bl __hash_page /* build HPTE if possible */
1761 cmpdi r3,0 /* see if __hash_page succeeded */
1764 beq fast_exc_return_irq /* Return from exception on success */
1769 /* Reload DSISR into r4 for the DABR check below */
1771 #endif /* CONFIG_PPC_BOOK3S_64 */
1773 /* Here we have a page fault that hash_page can't handle. */
1775 11: andis. r0,r4,DSISR_DABRMATCH@h
1776 bne- handle_dabr_fault
1779 addi r3,r1,STACK_FRAME_OVERHEAD
1782 beq+ ret_from_except_lite
1785 addi r3,r1,STACK_FRAME_OVERHEAD
1790 /* We have a data breakpoint exception - handle it */
1795 addi r3,r1,STACK_FRAME_OVERHEAD
1798 * do_break() may have changed the NV GPRS while handling a breakpoint.
1799 * If so, we need to restore them with their updated values. Don't use
1800 * ret_from_except_lite here.
1805 #ifdef CONFIG_PPC_BOOK3S_64
1806 /* We have a page fault that hash_page could handle but HV refused
1811 addi r3,r1,STACK_FRAME_OVERHEAD
1818 * We come here as a result of a DSI at a point where we don't want
1819 * to call hash_page, such as when we are accessing memory (possibly
1820 * user memory) inside a PMU interrupt that occurred while interrupts
1821 * were soft-disabled. We want to invoke the exception handler for
1822 * the access, or panic if there isn't a handler.
1826 addi r3,r1,STACK_FRAME_OVERHEAD
1832 * Here we have detected that the kernel stack pointer is bad.
1833 * R9 contains the saved CR, r13 points to the paca,
1834 * r10 contains the (bad) kernel stack pointer,
1835 * r11 and r12 contain the saved SRR0 and SRR1.
1836 * We switch to using an emergency stack, save the registers there,
1837 * and call kernel_bad_stack(), which panics.
1840 ld r1,PACAEMERGSP(r13)
1841 subi r1,r1,64+INT_FRAME_SIZE
1847 mfspr r12,SPRN_DSISR
1873 std r10,ORIG_GPR3(r1)
1874 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1877 lhz r12,PACA_TRAP_SAVE(r13)
1879 addi r11,r1,INT_FRAME_SIZE
1884 ld r11,exception_marker@toc(r2)
1886 std r11,STACK_FRAME_OVERHEAD-16(r1)
1887 1: addi r3,r1,STACK_FRAME_OVERHEAD
1890 _ASM_NOKPROBE_SYMBOL(bad_stack);
1893 * When doorbell is triggered from system reset wakeup, the message is
1894 * not cleared, so it would fire again when EE is enabled.
1896 * When coming from local_irq_enable, there may be the same problem if
1897 * we were hard disabled.
1899 * Execute msgclr to clear pending exceptions before handling it.
1901 h_doorbell_common_msgclr:
1902 LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36))
1906 doorbell_super_common_msgclr:
1907 LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36))
1909 b doorbell_super_common
1912 * Called from arch_local_irq_enable when an interrupt needs
1913 * to be resent. r3 contains 0x500, 0x900, 0xa00 or 0xe80 to indicate
1914 * which kind of interrupt. MSR:EE is already off. We generate a
1915 * stackframe like if a real interrupt had happened.
1917 * Note: While MSR:EE is off, we need to make sure that _MSR
1918 * in the generated frame has EE set to 1 or the exception
1919 * handler will not properly re-enable them.
1921 * Note that we don't specify LR as the NIP (return address) for
1922 * the interrupt because that would unbalance the return branch
1925 _GLOBAL(__replay_interrupt)
1926 /* We are going to jump to the exception common code which
1927 * will retrieve various register values from the PACA which
1928 * we don't give a damn about, so we don't bother storing them.
1931 LOAD_REG_ADDR(r11, replay_interrupt_return)
1935 beq decrementer_common
1938 beq h_virt_irq_common
1940 beq hardware_interrupt_common
1941 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_300)
1943 beq performance_monitor_common
1946 beq h_doorbell_common_msgclr
1948 beq hmi_exception_common
1951 beq doorbell_super_common_msgclr
1952 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
1953 replay_interrupt_return:
1956 _ASM_NOKPROBE_SYMBOL(__replay_interrupt)