3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
6 * Adapted for Power Macintosh by Paul Mackerras.
7 * Low-level exception handlers and MMU support
8 * rewritten by Paul Mackerras.
9 * Copyright (C) 1996 Paul Mackerras.
10 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 * This file contains the system call entry code, context switch
13 * code, and exception/interrupt return code for PowerPC.
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
21 #include <linux/errno.h>
22 #include <linux/err.h>
23 #include <asm/unistd.h>
24 #include <asm/processor.h>
27 #include <asm/thread_info.h>
28 #include <asm/code-patching-asm.h>
29 #include <asm/ppc_asm.h>
30 #include <asm/asm-offsets.h>
31 #include <asm/cputable.h>
32 #include <asm/firmware.h>
34 #include <asm/ptrace.h>
35 #include <asm/irqflags.h>
36 #include <asm/hw_irq.h>
37 #include <asm/context_tracking.h>
39 #include <asm/ppc-opcode.h>
40 #include <asm/barrier.h>
41 #include <asm/export.h>
42 #include <asm/asm-compat.h>
43 #ifdef CONFIG_PPC_BOOK3S
44 #include <asm/exception-64s.h>
46 #include <asm/exception-64e.h>
48 #include <asm/feature-fixups.h>
55 .tc sys_call_table[TC],sys_call_table
57 /* This value is used to mark exception frames on the stack. */
59 .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER
64 .globl system_call_common
66 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
68 extrdi. r10, r12, 1, (63-MSR_TS_T_LG) /* transaction active? */
70 END_FTR_SECTION_IFSET(CPU_FTR_TM)
74 addi r1,r1,-INT_FRAME_SIZE
82 beq 2f /* if from kernel mode */
83 ACCOUNT_CPU_USER_ENTRY(r13, r10, r11)
102 * This clears CR0.SO (bit 28), which is the error indication on
103 * return from this system call.
105 rldimi r2,r11,28,(63-28)
112 addi r9,r1,STACK_FRAME_OVERHEAD
113 ld r11,exception_marker@toc(r2)
114 std r11,-16(r9) /* "regshere" marker */
115 #if defined(CONFIG_VIRT_CPU_ACCOUNTING_NATIVE) && defined(CONFIG_PPC_SPLPAR)
118 /* if from user, see if there are any DTL entries to process */
119 ld r10,PACALPPACAPTR(r13) /* get ptr to VPA */
120 ld r11,PACA_DTL_RIDX(r13) /* get log read index */
121 addi r10,r10,LPPACA_DTLIDX
122 LDX_BE r10,0,r10 /* get log write index */
125 bl accumulate_stolen_time
129 addi r9,r1,STACK_FRAME_OVERHEAD
131 END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
132 #endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE && CONFIG_PPC_SPLPAR */
135 * A syscall should always be called with interrupts enabled
136 * so we just unconditionally hard-enable here. When some kind
137 * of irq tracing is used, we additionally check that condition
140 #if defined(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG) && defined(CONFIG_BUG)
141 lbz r10,PACAIRQSOFTMASK(r13)
142 1: tdnei r10,IRQS_ENABLED
143 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
146 #ifdef CONFIG_PPC_BOOK3E
152 #endif /* CONFIG_PPC_BOOK3E */
154 system_call: /* label this so stack traces look sane */
155 /* We do need to set SOFTE in the stack frame or the return
156 * from interrupt will be painful
161 CURRENT_THREAD_INFO(r11, r1)
163 andi. r11,r10,_TIF_SYSCALL_DOTRACE
164 bne .Lsyscall_dotrace /* does not return */
165 cmpldi 0,r0,NR_syscalls
166 bge- .Lsyscall_enosys
170 * Need to vector to 32 Bit or default sys_call_table here,
171 * based on caller's run-mode / personality.
173 ld r11,SYS_CALL_TABLE@toc(2)
174 andis. r10,r10,_TIF_32BIT@h
176 addi r11,r11,8 /* use 32-bit syscall entries */
188 * Prevent the load of the handler below (based on the user-passed
189 * system call number) being speculatively executed until the test
190 * against NR_syscalls and branch to .Lsyscall_enosys above has
194 ldx r12,r11,r0 /* Fetch system call handler [ptr] */
196 bctrl /* Call handler */
201 #ifdef CONFIG_DEBUG_RSEQ
202 /* Check whether the syscall is issued inside a restartable sequence */
203 addi r3,r1,STACK_FRAME_OVERHEAD
208 CURRENT_THREAD_INFO(r12, r1)
211 #ifdef CONFIG_PPC_BOOK3S
212 /* No MSR:RI on BookE */
214 beq- .Lunrecov_restore
218 * This is a few instructions into the actual syscall exit path (which actually
219 * starts at .Lsyscall_exit) to cater to kprobe blacklisting and to reduce the
220 * number of visible symbols for profiling purposes.
222 * We can probe from system_call until this point as MSR_RI is set. But once it
223 * is cleared below, we won't be able to take a trap.
225 * This is blacklisted from kprobes further below with _ASM_NOKPROBE_SYMBOL().
229 * Disable interrupts so current_thread_info()->flags can't change,
230 * and so that we don't get interrupted after loading SRR0/1.
232 #ifdef CONFIG_PPC_BOOK3E
236 * For performance reasons we clear RI the same time that we
237 * clear EE. We only need to clear RI just before we restore r13
238 * below, but batching it with EE saves us one expensive mtmsrd call.
239 * We have to be careful to restore RI if we branch anywhere from
240 * here (eg syscall_exit_work).
244 #endif /* CONFIG_PPC_BOOK3E */
248 andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
249 bne- .Lsyscall_exit_work
253 #ifdef CONFIG_ALTIVEC
254 andis. r0,r8,MSR_VEC@h
257 2: addi r3,r1,STACK_FRAME_OVERHEAD
258 #ifdef CONFIG_PPC_BOOK3S
260 mtmsrd r10,1 /* Restore RI */
263 #ifdef CONFIG_PPC_BOOK3S
274 .Lsyscall_error_cont:
277 stdcx. r0,0,r1 /* to clear the reservation */
278 END_FTR_SECTION_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
283 ACCOUNT_CPU_USER_EXIT(r13, r11, r12)
287 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
289 ld r13,GPR13(r1) /* only restore r13 if returning to usermode */
297 b . /* prevent speculative execution */
307 b . /* prevent speculative execution */
310 oris r5,r5,0x1000 /* Set SO bit in CR */
313 b .Lsyscall_error_cont
315 /* Traced system call support */
318 addi r3,r1,STACK_FRAME_OVERHEAD
319 bl do_syscall_trace_enter
322 * We use the return value of do_syscall_trace_enter() as the syscall
323 * number. If the syscall was rejected for any reason do_syscall_trace_enter()
324 * returns an invalid syscall number and the test below against
325 * NR_syscalls will fail.
329 /* Restore argument registers just clobbered and/or possibly changed. */
337 /* Repopulate r9 and r10 for the syscall path */
338 addi r9,r1,STACK_FRAME_OVERHEAD
339 CURRENT_THREAD_INFO(r10, r1)
342 cmpldi r0,NR_syscalls
345 /* Return code is already in r3 thanks to do_syscall_trace_enter() */
354 #ifdef CONFIG_PPC_BOOK3S
356 mtmsrd r10,1 /* Restore RI */
358 /* If TIF_RESTOREALL is set, don't scribble on either r3 or ccr.
359 If TIF_NOERROR is set, just save r3 as it is. */
361 andi. r0,r9,_TIF_RESTOREALL
365 0: cmpld r3,r11 /* r11 is -MAX_ERRNO */
367 andi. r0,r9,_TIF_NOERROR
371 oris r5,r5,0x1000 /* Set SO bit in CR */
374 2: andi. r0,r9,(_TIF_PERSYSCALL_MASK)
377 /* Clear per-syscall TIF flags if any are set. */
379 li r11,_TIF_PERSYSCALL_MASK
380 addi r12,r12,TI_FLAGS
385 subi r12,r12,TI_FLAGS
387 4: /* Anything else left to do? */
389 lis r3,DEFAULT_PPR@highest /* Set default PPR */
390 sldi r3,r3,32 /* bits 11-13 are used for ppr */
392 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
394 andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP)
395 beq ret_from_except_lite
397 /* Re-enable interrupts */
398 #ifdef CONFIG_PPC_BOOK3E
404 #endif /* CONFIG_PPC_BOOK3E */
407 addi r3,r1,STACK_FRAME_OVERHEAD
408 bl do_syscall_trace_leave
411 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
413 /* Firstly we need to enable TM in the kernel */
416 rldimi r10, r9, MSR_TM_LG, 63-MSR_TM_LG
419 /* tabort, this dooms the transaction, nothing else */
420 li r9, (TM_CAUSE_SYSCALL|TM_CAUSE_PERSISTENT)
424 * Return directly to userspace. We have corrupted user register state,
425 * but userspace will never see that register state. Execution will
426 * resume after the tbegin of the aborted transaction with the
427 * checkpointed register state.
435 b . /* prevent speculative execution */
437 _ASM_NOKPROBE_SYMBOL(system_call_common);
438 _ASM_NOKPROBE_SYMBOL(system_call_exit);
440 /* Save non-volatile GPRs, if not already saved. */
449 _ASM_NOKPROBE_SYMBOL(save_nvgprs);
453 * The sigsuspend and rt_sigsuspend system calls can call do_signal
454 * and thus put the process into the stopped state where we might
455 * want to examine its user state with ptrace. Therefore we need
456 * to save all the nonvolatile registers (r14 - r31) before calling
457 * the C code. Similarly, fork, vfork and clone need the full
458 * register state on the stack so that it can be copied to the child.
476 _GLOBAL(ppc32_swapcontext)
478 bl compat_sys_swapcontext
481 _GLOBAL(ppc64_swapcontext)
486 _GLOBAL(ppc_switch_endian)
491 _GLOBAL(ret_from_fork)
497 _GLOBAL(ret_from_kernel_thread)
502 #ifdef PPC64_ELF_ABI_v2
509 #ifdef CONFIG_PPC_BOOK3S_64
511 #define FLUSH_COUNT_CACHE \
513 patch_site 1b, patch__call_flush_count_cache
516 #define BCCTR_FLUSH .long 0x4c400420
525 .global flush_count_cache
527 /* Save LR into r9 */
545 patch_site 2b patch__flush_count_cache_return
557 #define FLUSH_COUNT_CACHE
558 #endif /* CONFIG_PPC_BOOK3S_64 */
561 * This routine switches between two different tasks. The process
562 * state of one is saved on its kernel stack. Then the state
563 * of the other is restored from its kernel stack. The memory
564 * management hardware is updated to the second process's state.
565 * Finally, we can return to the second process, via ret_from_except.
566 * On entry, r3 points to the THREAD for the current task, r4
567 * points to the THREAD for the new task.
569 * Note: there are two ways to get to the "going out" portion
570 * of this code; either by coming in via the entry (_switch)
571 * or via "fork" which must set up an environment equivalent
572 * to the "_switch" path. If you change this you'll have to change
573 * the fork code also.
575 * The code which creates the new task context is in 'copy_thread'
576 * in arch/powerpc/kernel/process.c
582 stdu r1,-SWITCH_FRAME_SIZE(r1)
583 /* r3-r13 are caller saved -- Cort */
586 std r0,_NIP(r1) /* Return to switch caller */
589 std r1,KSP(r3) /* Set old stack pointer */
594 * On SMP kernels, care must be taken because a task may be
595 * scheduled off CPUx and on to CPUy. Memory ordering must be
598 * Cacheable stores on CPUx will be visible when the task is
599 * scheduled on CPUy by virtue of the core scheduler barriers
600 * (see "Notes on Program-Order guarantees on SMP systems." in
601 * kernel/sched/core.c).
603 * Uncacheable stores in the case of involuntary preemption must
604 * be taken care of. The smp_mb__before_spin_lock() in __schedule()
605 * is implemented as hwsync on powerpc, which orders MMIO too. So
606 * long as there is an hwsync in the context switch path, it will
607 * be executed on the source CPU after the task has performed
608 * all MMIO ops on that CPU, and on the destination CPU before the
609 * task performs any MMIO ops there.
613 * The kernel context switch path must contain a spin_lock,
614 * which contains larx/stcx, which will clear any reservation
615 * of the task being switched.
617 #ifdef CONFIG_PPC_BOOK3S
618 /* Cancel all explict user streams as they will have no use after context
619 * switch and will stop the HW from creating streams itself
621 DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r6)
624 addi r6,r4,-THREAD /* Convert THREAD to 'current' */
625 std r6,PACACURRENT(r13) /* Set new 'current' */
626 #if defined(CONFIG_STACKPROTECTOR)
627 ld r6, TASK_CANARY(r6)
628 std r6, PACA_CANARY(r13)
631 ld r8,KSP(r4) /* new stack pointer */
632 #ifdef CONFIG_PPC_BOOK3S_64
633 BEGIN_MMU_FTR_SECTION
635 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
637 clrrdi r6,r8,28 /* get its ESID */
638 clrrdi r9,r1,28 /* get current sp ESID */
640 clrrdi r6,r8,40 /* get its 1T ESID */
641 clrrdi r9,r1,40 /* get current sp 1T ESID */
642 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_1T_SEGMENT)
643 clrldi. r0,r6,2 /* is new ESID c00000000? */
644 cmpd cr1,r6,r9 /* or is new ESID the same as current ESID? */
646 beq 2f /* if yes, don't slbie it */
648 /* Bolt in the new stack SLB entry */
649 ld r7,KSP_VSID(r4) /* Get new stack's VSID */
650 oris r0,r6,(SLB_ESID_V)@h
651 ori r0,r0,(SLB_NUM_BOLTED-1)@l
653 li r9,MMU_SEGSIZE_1T /* insert B field */
654 oris r6,r6,(MMU_SEGSIZE_1T << SLBIE_SSIZE_SHIFT)@h
655 rldimi r7,r9,SLB_VSID_SSIZE_SHIFT,0
656 END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
658 /* Update the last bolted SLB. No write barriers are needed
659 * here, provided we only update the current CPU's SLB shadow
662 ld r9,PACA_SLBSHADOWPTR(r13)
664 std r12,SLBSHADOW_STACKESID(r9) /* Clear ESID */
665 li r12,SLBSHADOW_STACKVSID
666 STDX_BE r7,r12,r9 /* Save VSID */
667 li r12,SLBSHADOW_STACKESID
668 STDX_BE r0,r12,r9 /* Save ESID */
670 /* No need to check for MMU_FTR_NO_SLBIE_B here, since when
671 * we have 1TB segments, the only CPUs known to have the errata
672 * only support less than 1TB of system memory and we'll never
673 * actually hit this code path.
679 slbie r6 /* Workaround POWER5 < DD2.1 issue */
680 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
684 #endif /* CONFIG_PPC_BOOK3S_64 */
686 CURRENT_THREAD_INFO(r7, r8) /* base of new stack */
687 /* Note: this uses SWITCH_FRAME_SIZE rather than INT_FRAME_SIZE
688 because we don't need to leave the 288-byte ABI gap at the
689 top of the kernel stack. */
690 addi r7,r7,THREAD_SIZE-SWITCH_FRAME_SIZE
693 * PMU interrupts in radix may come in here. They will use r1, not
694 * PACAKSAVE, so this stack switch will not cause a problem. They
695 * will store to the process stack, which may then be migrated to
696 * another CPU. However the rq lock release on this CPU paired with
697 * the rq lock acquire on the new CPU before the stack becomes
698 * active on the new CPU, will order those stores.
700 mr r1,r8 /* start using new stack pointer */
701 std r7,PACAKSAVE(r13)
706 /* r3-r13 are destroyed -- Cort */
710 /* convert old thread to its task_struct for return value */
712 ld r7,_NIP(r1) /* Return to _switch caller in new task */
714 addi r1,r1,SWITCH_FRAME_SIZE
718 _GLOBAL(ret_from_except)
721 bne ret_from_except_lite
724 _GLOBAL(ret_from_except_lite)
726 * Disable interrupts so that current_thread_info()->flags
727 * can't change between when we test it and when we return
728 * from the interrupt.
730 #ifdef CONFIG_PPC_BOOK3E
734 mtmsrd r10,1 /* Update machine state */
735 #endif /* CONFIG_PPC_BOOK3E */
737 CURRENT_THREAD_INFO(r9, r1)
739 #ifdef CONFIG_PPC_BOOK3E
740 ld r10,PACACURRENT(r13)
741 #endif /* CONFIG_PPC_BOOK3E */
745 #ifdef CONFIG_PPC_BOOK3E
746 lwz r3,(THREAD+THREAD_DBCR0)(r10)
747 #endif /* CONFIG_PPC_BOOK3E */
749 /* Check current_thread_info()->flags */
750 andi. r0,r4,_TIF_USER_WORK_MASK
752 #ifdef CONFIG_PPC_BOOK3E
754 * Check to see if the dbcr0 register is set up to debug.
755 * Use the internal debug mode bit to do this.
757 andis. r0,r3,DBCR0_IDM@h
760 rlwinm r0,r0,0,~MSR_DE /* Clear MSR.DE */
767 addi r3,r1,STACK_FRAME_OVERHEAD
771 1: andi. r0,r4,_TIF_NEED_RESCHED
773 bl restore_interrupts
775 b ret_from_except_lite
777 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
778 andi. r0,r4,_TIF_USER_WORK_MASK & ~_TIF_RESTORE_TM
779 bne 3f /* only restore TM if nothing else to do */
780 addi r3,r1,STACK_FRAME_OVERHEAD
787 * Use a non volatile GPR to save and restore our thread_info flags
788 * across the call to restore_interrupts.
791 bl restore_interrupts
793 addi r3,r1,STACK_FRAME_OVERHEAD
798 /* check current_thread_info, _TIF_EMULATE_STACK_STORE */
799 andis. r8,r4,_TIF_EMULATE_STACK_STORE@h
802 addi r8,r1,INT_FRAME_SIZE /* Get the kprobed function entry */
805 subi r3,r3,INT_FRAME_SIZE /* dst: Allocate a trampoline exception frame */
806 mr r4,r1 /* src: current exception frame */
807 mr r1,r3 /* Reroute the trampoline frame to r1 */
809 /* Copy from the original to the trampoline. */
810 li r5,INT_FRAME_SIZE/8 /* size: INT_FRAME_SIZE */
811 li r6,0 /* start offset: 0 */
818 /* Do real store operation to complete stdu */
822 /* Clear _TIF_EMULATE_STACK_STORE flag */
823 lis r11,_TIF_EMULATE_STACK_STORE@h
831 #ifdef CONFIG_PREEMPT
832 /* Check if we need to preempt */
833 andi. r0,r4,_TIF_NEED_RESCHED
835 /* Check that preempt_count() == 0 and interrupts are enabled */
836 lwz r8,TI_PREEMPT(r9)
840 andi. r0,r0,IRQS_DISABLED
844 * Here we are preempting the current task. We want to make
845 * sure we are soft-disabled first and reconcile irq state.
847 RECONCILE_IRQ_STATE(r3,r4)
848 1: bl preempt_schedule_irq
850 /* Re-test flags and eventually loop */
851 CURRENT_THREAD_INFO(r9, r1)
853 andi. r0,r4,_TIF_NEED_RESCHED
857 * arch_local_irq_restore() from preempt_schedule_irq above may
858 * enable hard interrupt but we really should disable interrupts
859 * when we return from the interrupt, and so that we don't get
860 * interrupted after loading SRR0/1.
862 #ifdef CONFIG_PPC_BOOK3E
866 mtmsrd r10,1 /* Update machine state */
867 #endif /* CONFIG_PPC_BOOK3E */
868 #endif /* CONFIG_PREEMPT */
870 .globl fast_exc_return_irq
874 * This is the main kernel exit path. First we check if we
875 * are about to re-enable interrupts
878 lbz r6,PACAIRQSOFTMASK(r13)
879 andi. r5,r5,IRQS_DISABLED
880 bne .Lrestore_irq_off
882 /* We are enabling, were we already enabled ? Yes, just return */
883 andi. r6,r6,IRQS_DISABLED
887 * We are about to soft-enable interrupts (we are hard disabled
888 * at this point). We check if there's anything that needs to
891 lbz r0,PACAIRQHAPPENED(r13)
893 bne- .Lrestore_check_irq_replay
896 * Get here when nothing happened while soft-disabled, just
897 * soft-enable and move-on. We will hard-enable as a side
903 stb r0,PACAIRQSOFTMASK(r13);
906 * Final return path. BookE is handled in a different file
909 #ifdef CONFIG_PPC_BOOK3E
910 b exception_return_book3e
913 * Clear the reservation. If we know the CPU tracks the address of
914 * the reservation then we can potentially save some cycles and use
915 * a larx. On POWER6 and POWER7 this is significantly faster.
918 stdcx. r0,0,r1 /* to clear the reservation */
921 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
924 * Some code path such as load_up_fpu or altivec return directly
925 * here. They run entirely hard disabled and do not alter the
926 * interrupt state. They also don't use lwarx/stwcx. and thus
927 * are known not to leave dangling reservations.
929 .globl fast_exception_return
930 fast_exception_return:
942 beq- .Lunrecov_restore
945 * Clear RI before restoring r13. If we are returning to
946 * userspace and we take an exception after restoring r13,
947 * we end up corrupting the userspace r13 value.
952 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
954 std r3, PACATMSCRATCH(r13) /* Stash returned-to MSR */
957 * r13 is our per cpu area, only restore it if we are returning to
958 * userspace the value stored in the stack frame may belong to
967 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
968 ACCOUNT_CPU_USER_EXIT(r13, r2, r4)
984 b . /* prevent speculative execution */
986 1: mtspr SPRN_SRR1,r3
999 b . /* prevent speculative execution */
1001 #endif /* CONFIG_PPC_BOOK3E */
1004 * We are returning to a context with interrupts soft disabled.
1006 * However, we may also about to hard enable, so we need to
1007 * make sure that in this case, we also clear PACA_IRQ_HARD_DIS
1008 * or that bit can get out of sync and bad things will happen
1012 lbz r7,PACAIRQHAPPENED(r13)
1015 rlwinm r7,r7,0,~PACA_IRQ_HARD_DIS
1016 stb r7,PACAIRQHAPPENED(r13)
1018 #if defined(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG) && defined(CONFIG_BUG)
1019 /* The interrupt should not have soft enabled. */
1020 lbz r7,PACAIRQSOFTMASK(r13)
1021 1: tdeqi r7,IRQS_ENABLED
1022 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
1027 * Something did happen, check if a re-emit is needed
1028 * (this also clears paca->irq_happened)
1030 .Lrestore_check_irq_replay:
1031 /* XXX: We could implement a fast path here where we check
1032 * for irq_happened being just 0x01, in which case we can
1033 * clear it and return. That means that we would potentially
1034 * miss a decrementer having wrapped all the way around.
1036 * Still, this might be useful for things like hash_page
1038 bl __check_irq_replay
1040 beq .Lrestore_no_replay
1043 * We need to re-emit an interrupt. We do so by re-using our
1044 * existing exception frame. We first change the trap value,
1045 * but we need to ensure we preserve the low nibble of it
1053 * PACA_IRQ_HARD_DIS won't always be set here, so set it now
1054 * to reconcile the IRQ state. Tracing is already accounted for.
1056 lbz r4,PACAIRQHAPPENED(r13)
1057 ori r4,r4,PACA_IRQ_HARD_DIS
1058 stb r4,PACAIRQHAPPENED(r13)
1061 * Then find the right handler and call it. Interrupts are
1062 * still soft-disabled and we keep them that way.
1066 addi r3,r1,STACK_FRAME_OVERHEAD;
1069 1: cmpwi cr0,r3,0xf00
1071 addi r3,r1,STACK_FRAME_OVERHEAD;
1072 bl performance_monitor_exception
1074 1: cmpwi cr0,r3,0xe60
1076 addi r3,r1,STACK_FRAME_OVERHEAD;
1077 bl handle_hmi_exception
1079 1: cmpwi cr0,r3,0x900
1081 addi r3,r1,STACK_FRAME_OVERHEAD;
1084 #ifdef CONFIG_PPC_DOORBELL
1086 #ifdef CONFIG_PPC_BOOK3E
1090 #endif /* CONFIG_PPC_BOOK3E */
1092 addi r3,r1,STACK_FRAME_OVERHEAD;
1093 bl doorbell_exception
1094 #endif /* CONFIG_PPC_DOORBELL */
1095 1: b ret_from_except /* What else to do here ? */
1098 addi r3,r1,STACK_FRAME_OVERHEAD
1099 bl unrecoverable_exception
1102 _ASM_NOKPROBE_SYMBOL(ret_from_except);
1103 _ASM_NOKPROBE_SYMBOL(ret_from_except_lite);
1104 _ASM_NOKPROBE_SYMBOL(resume_kernel);
1105 _ASM_NOKPROBE_SYMBOL(fast_exc_return_irq);
1106 _ASM_NOKPROBE_SYMBOL(restore);
1107 _ASM_NOKPROBE_SYMBOL(fast_exception_return);
1110 #ifdef CONFIG_PPC_RTAS
1112 * On CHRP, the Run-Time Abstraction Services (RTAS) have to be
1113 * called with the MMU off.
1115 * In addition, we need to be in 32b mode, at least for now.
1117 * Note: r3 is an input parameter to rtas, so don't trash it...
1122 stdu r1,-SWITCH_FRAME_SIZE(r1) /* Save SP and create stack space. */
1124 /* Because RTAS is running in 32b mode, it clobbers the high order half
1125 * of all registers that it saves. We therefore save those registers
1126 * RTAS might touch to the stack. (r0, r3-r13 are caller saved)
1128 SAVE_GPR(2, r1) /* Save the TOC */
1129 SAVE_GPR(13, r1) /* Save paca */
1130 SAVE_8GPRS(14, r1) /* Save the non-volatiles */
1131 SAVE_10GPRS(22, r1) /* ditto */
1144 /* Temporary workaround to clear CR until RTAS can be modified to
1151 /* There is no way it is acceptable to get here with interrupts enabled,
1152 * check it with the asm equivalent of WARN_ON
1154 lbz r0,PACAIRQSOFTMASK(r13)
1155 1: tdeqi r0,IRQS_ENABLED
1156 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
1159 /* Hard-disable interrupts */
1165 /* Unfortunately, the stack pointer and the MSR are also clobbered,
1166 * so they are saved in the PACA which allows us to restore
1167 * our original state after RTAS returns.
1170 std r6,PACASAVEDMSR(r13)
1172 /* Setup our real return addr */
1173 LOAD_REG_ADDR(r4,rtas_return_loc)
1174 clrldi r4,r4,2 /* convert to realmode address */
1178 ori r0,r0,MSR_EE|MSR_SE|MSR_BE|MSR_RI
1182 rldicr r9,r9,MSR_SF_LG,(63-MSR_SF_LG)
1183 ori r9,r9,MSR_IR|MSR_DR|MSR_FE0|MSR_FE1|MSR_FP|MSR_RI|MSR_LE
1187 sync /* disable interrupts so SRR0/1 */
1188 mtmsrd r0 /* don't get trashed */
1190 LOAD_REG_ADDR(r4, rtas)
1191 ld r5,RTASENTRY(r4) /* get the rtas->entry value */
1192 ld r4,RTASBASE(r4) /* get the rtas->base value */
1197 b . /* prevent speculative execution */
1203 * Clear RI and set SF before anything.
1208 sldi r0,r0,(MSR_SF_LG - MSR_RI_LG)
1213 /* relocation is off at this point */
1215 clrldi r4,r4,2 /* convert to realmode address */
1219 ld r3,(1f-0b)(r3) /* get &rtas_restore_regs */
1221 ld r1,PACAR1(r4) /* Restore our SP */
1222 ld r4,PACASAVEDMSR(r4) /* Restore our MSR */
1227 b . /* prevent speculative execution */
1228 _ASM_NOKPROBE_SYMBOL(__enter_rtas)
1229 _ASM_NOKPROBE_SYMBOL(rtas_return_loc)
1232 1: .8byte rtas_restore_regs
1235 /* relocation is on at this point */
1236 REST_GPR(2, r1) /* Restore the TOC */
1237 REST_GPR(13, r1) /* Restore paca */
1238 REST_8GPRS(14, r1) /* Restore the non-volatiles */
1239 REST_10GPRS(22, r1) /* ditto */
1254 addi r1,r1,SWITCH_FRAME_SIZE /* Unstack our frame */
1255 ld r0,16(r1) /* get return address */
1258 blr /* return to caller */
1260 #endif /* CONFIG_PPC_RTAS */
1265 stdu r1,-SWITCH_FRAME_SIZE(r1) /* Save SP and create stack space */
1267 /* Because PROM is running in 32b mode, it clobbers the high order half
1268 * of all registers that it saves. We therefore save those registers
1269 * PROM might touch to the stack. (r0, r3-r13 are caller saved)
1280 /* Put PROM address in SRR0 */
1283 /* Setup our trampoline return addr in LR */
1286 addi r4,r4,(1f - 0b)
1289 /* Prepare a 32-bit mode big endian MSR
1291 #ifdef CONFIG_PPC_BOOK3E
1292 rlwinm r11,r11,0,1,31
1295 #else /* CONFIG_PPC_BOOK3E */
1296 LOAD_REG_IMMEDIATE(r12, MSR_SF | MSR_ISF | MSR_LE)
1300 #endif /* CONFIG_PPC_BOOK3E */
1302 1: /* Return from OF */
1305 /* Just make sure that r1 top 32 bits didn't get
1310 /* Restore the MSR (back to 64 bits) */
1315 /* Restore other registers */
1323 addi r1,r1,SWITCH_FRAME_SIZE