3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
6 * Adapted for Power Macintosh by Paul Mackerras.
7 * Low-level exception handlers and MMU support
8 * rewritten by Paul Mackerras.
9 * Copyright (C) 1996 Paul Mackerras.
10 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 * This file contains the system call entry code, context switch
13 * code, and exception/interrupt return code for PowerPC.
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
21 #include <linux/errno.h>
22 #include <linux/err.h>
23 #include <asm/unistd.h>
24 #include <asm/processor.h>
27 #include <asm/thread_info.h>
28 #include <asm/ppc_asm.h>
29 #include <asm/asm-offsets.h>
30 #include <asm/cputable.h>
31 #include <asm/firmware.h>
33 #include <asm/ptrace.h>
34 #include <asm/irqflags.h>
35 #include <asm/hw_irq.h>
36 #include <asm/context_tracking.h>
38 #include <asm/ppc-opcode.h>
39 #include <asm/barrier.h>
40 #include <asm/export.h>
41 #ifdef CONFIG_PPC_BOOK3S
42 #include <asm/exception-64s.h>
44 #include <asm/exception-64e.h>
52 .tc sys_call_table[TC],sys_call_table
54 /* This value is used to mark exception frames on the stack. */
56 .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER
61 .globl system_call_common
63 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
65 extrdi. r10, r12, 1, (63-MSR_TS_T_LG) /* transaction active? */
67 END_FTR_SECTION_IFSET(CPU_FTR_TM)
71 addi r1,r1,-INT_FRAME_SIZE
79 beq 2f /* if from kernel mode */
80 ACCOUNT_CPU_USER_ENTRY(r13, r10, r11)
99 * This clears CR0.SO (bit 28), which is the error indication on
100 * return from this system call.
102 rldimi r2,r11,28,(63-28)
109 addi r9,r1,STACK_FRAME_OVERHEAD
110 ld r11,exception_marker@toc(r2)
111 std r11,-16(r9) /* "regshere" marker */
112 #if defined(CONFIG_VIRT_CPU_ACCOUNTING_NATIVE) && defined(CONFIG_PPC_SPLPAR)
115 /* if from user, see if there are any DTL entries to process */
116 ld r10,PACALPPACAPTR(r13) /* get ptr to VPA */
117 ld r11,PACA_DTL_RIDX(r13) /* get log read index */
118 addi r10,r10,LPPACA_DTLIDX
119 LDX_BE r10,0,r10 /* get log write index */
122 bl accumulate_stolen_time
126 addi r9,r1,STACK_FRAME_OVERHEAD
128 END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
129 #endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE && CONFIG_PPC_SPLPAR */
132 * A syscall should always be called with interrupts enabled
133 * so we just unconditionally hard-enable here. When some kind
134 * of irq tracing is used, we additionally check that condition
137 #if defined(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG) && defined(CONFIG_BUG)
138 lbz r10,PACAIRQSOFTMASK(r13)
139 1: tdnei r10,IRQS_ENABLED
140 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
143 #ifdef CONFIG_PPC_BOOK3E
149 #endif /* CONFIG_PPC_BOOK3E */
151 system_call: /* label this so stack traces look sane */
152 /* We do need to set SOFTE in the stack frame or the return
153 * from interrupt will be painful
158 CURRENT_THREAD_INFO(r11, r1)
160 andi. r11,r10,_TIF_SYSCALL_DOTRACE
161 bne .Lsyscall_dotrace /* does not return */
162 cmpldi 0,r0,NR_syscalls
163 bge- .Lsyscall_enosys
167 * Need to vector to 32 Bit or default sys_call_table here,
168 * based on caller's run-mode / personality.
170 ld r11,SYS_CALL_TABLE@toc(2)
171 andi. r10,r10,_TIF_32BIT
173 addi r11,r11,8 /* use 32-bit syscall entries */
185 * Prevent the load of the handler below (based on the user-passed
186 * system call number) being speculatively executed until the test
187 * against NR_syscalls and branch to .Lsyscall_enosys above has
191 ldx r12,r11,r0 /* Fetch system call handler [ptr] */
193 bctrl /* Call handler */
198 #ifdef CONFIG_DEBUG_RSEQ
199 /* Check whether the syscall is issued inside a restartable sequence */
200 addi r3,r1,STACK_FRAME_OVERHEAD
205 CURRENT_THREAD_INFO(r12, r1)
208 #ifdef CONFIG_PPC_BOOK3S
209 /* No MSR:RI on BookE */
211 beq- .Lunrecov_restore
215 * This is a few instructions into the actual syscall exit path (which actually
216 * starts at .Lsyscall_exit) to cater to kprobe blacklisting and to reduce the
217 * number of visible symbols for profiling purposes.
219 * We can probe from system_call until this point as MSR_RI is set. But once it
220 * is cleared below, we won't be able to take a trap.
222 * This is blacklisted from kprobes further below with _ASM_NOKPROBE_SYMBOL().
226 * Disable interrupts so current_thread_info()->flags can't change,
227 * and so that we don't get interrupted after loading SRR0/1.
229 #ifdef CONFIG_PPC_BOOK3E
233 * For performance reasons we clear RI the same time that we
234 * clear EE. We only need to clear RI just before we restore r13
235 * below, but batching it with EE saves us one expensive mtmsrd call.
236 * We have to be careful to restore RI if we branch anywhere from
237 * here (eg syscall_exit_work).
241 #endif /* CONFIG_PPC_BOOK3E */
245 andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
246 bne- .Lsyscall_exit_work
250 #ifdef CONFIG_ALTIVEC
251 andis. r0,r8,MSR_VEC@h
254 2: addi r3,r1,STACK_FRAME_OVERHEAD
255 #ifdef CONFIG_PPC_BOOK3S
257 mtmsrd r10,1 /* Restore RI */
260 #ifdef CONFIG_PPC_BOOK3S
271 .Lsyscall_error_cont:
274 stdcx. r0,0,r1 /* to clear the reservation */
275 END_FTR_SECTION_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
280 ACCOUNT_CPU_USER_EXIT(r13, r11, r12)
284 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
286 ld r13,GPR13(r1) /* only restore r13 if returning to usermode */
294 b . /* prevent speculative execution */
304 b . /* prevent speculative execution */
307 oris r5,r5,0x1000 /* Set SO bit in CR */
310 b .Lsyscall_error_cont
312 /* Traced system call support */
315 addi r3,r1,STACK_FRAME_OVERHEAD
316 bl do_syscall_trace_enter
319 * We use the return value of do_syscall_trace_enter() as the syscall
320 * number. If the syscall was rejected for any reason do_syscall_trace_enter()
321 * returns an invalid syscall number and the test below against
322 * NR_syscalls will fail.
326 /* Restore argument registers just clobbered and/or possibly changed. */
334 /* Repopulate r9 and r10 for the syscall path */
335 addi r9,r1,STACK_FRAME_OVERHEAD
336 CURRENT_THREAD_INFO(r10, r1)
339 cmpldi r0,NR_syscalls
342 /* Return code is already in r3 thanks to do_syscall_trace_enter() */
351 #ifdef CONFIG_PPC_BOOK3S
353 mtmsrd r10,1 /* Restore RI */
355 /* If TIF_RESTOREALL is set, don't scribble on either r3 or ccr.
356 If TIF_NOERROR is set, just save r3 as it is. */
358 andi. r0,r9,_TIF_RESTOREALL
362 0: cmpld r3,r11 /* r11 is -MAX_ERRNO */
364 andi. r0,r9,_TIF_NOERROR
368 oris r5,r5,0x1000 /* Set SO bit in CR */
371 2: andi. r0,r9,(_TIF_PERSYSCALL_MASK)
374 /* Clear per-syscall TIF flags if any are set. */
376 li r11,_TIF_PERSYSCALL_MASK
377 addi r12,r12,TI_FLAGS
382 subi r12,r12,TI_FLAGS
384 4: /* Anything else left to do? */
386 lis r3,INIT_PPR@highest /* Set thread.ppr = 3 */
387 ld r10,PACACURRENT(r13)
388 sldi r3,r3,32 /* bits 11-13 are used for ppr */
389 std r3,TASKTHREADPPR(r10)
390 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
392 andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP)
393 beq ret_from_except_lite
395 /* Re-enable interrupts */
396 #ifdef CONFIG_PPC_BOOK3E
402 #endif /* CONFIG_PPC_BOOK3E */
405 addi r3,r1,STACK_FRAME_OVERHEAD
406 bl do_syscall_trace_leave
409 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
411 /* Firstly we need to enable TM in the kernel */
414 rldimi r10, r9, MSR_TM_LG, 63-MSR_TM_LG
417 /* tabort, this dooms the transaction, nothing else */
418 li r9, (TM_CAUSE_SYSCALL|TM_CAUSE_PERSISTENT)
422 * Return directly to userspace. We have corrupted user register state,
423 * but userspace will never see that register state. Execution will
424 * resume after the tbegin of the aborted transaction with the
425 * checkpointed register state.
433 b . /* prevent speculative execution */
435 _ASM_NOKPROBE_SYMBOL(system_call_common);
436 _ASM_NOKPROBE_SYMBOL(system_call_exit);
438 /* Save non-volatile GPRs, if not already saved. */
447 _ASM_NOKPROBE_SYMBOL(save_nvgprs);
451 * The sigsuspend and rt_sigsuspend system calls can call do_signal
452 * and thus put the process into the stopped state where we might
453 * want to examine its user state with ptrace. Therefore we need
454 * to save all the nonvolatile registers (r14 - r31) before calling
455 * the C code. Similarly, fork, vfork and clone need the full
456 * register state on the stack so that it can be copied to the child.
474 _GLOBAL(ppc32_swapcontext)
476 bl compat_sys_swapcontext
479 _GLOBAL(ppc64_swapcontext)
484 _GLOBAL(ppc_switch_endian)
489 _GLOBAL(ret_from_fork)
495 _GLOBAL(ret_from_kernel_thread)
500 #ifdef PPC64_ELF_ABI_v2
508 * This routine switches between two different tasks. The process
509 * state of one is saved on its kernel stack. Then the state
510 * of the other is restored from its kernel stack. The memory
511 * management hardware is updated to the second process's state.
512 * Finally, we can return to the second process, via ret_from_except.
513 * On entry, r3 points to the THREAD for the current task, r4
514 * points to the THREAD for the new task.
516 * Note: there are two ways to get to the "going out" portion
517 * of this code; either by coming in via the entry (_switch)
518 * or via "fork" which must set up an environment equivalent
519 * to the "_switch" path. If you change this you'll have to change
520 * the fork code also.
522 * The code which creates the new task context is in 'copy_thread'
523 * in arch/powerpc/kernel/process.c
529 stdu r1,-SWITCH_FRAME_SIZE(r1)
530 /* r3-r13 are caller saved -- Cort */
533 std r0,_NIP(r1) /* Return to switch caller */
536 std r1,KSP(r3) /* Set old stack pointer */
539 * On SMP kernels, care must be taken because a task may be
540 * scheduled off CPUx and on to CPUy. Memory ordering must be
543 * Cacheable stores on CPUx will be visible when the task is
544 * scheduled on CPUy by virtue of the core scheduler barriers
545 * (see "Notes on Program-Order guarantees on SMP systems." in
546 * kernel/sched/core.c).
548 * Uncacheable stores in the case of involuntary preemption must
549 * be taken care of. The smp_mb__before_spin_lock() in __schedule()
550 * is implemented as hwsync on powerpc, which orders MMIO too. So
551 * long as there is an hwsync in the context switch path, it will
552 * be executed on the source CPU after the task has performed
553 * all MMIO ops on that CPU, and on the destination CPU before the
554 * task performs any MMIO ops there.
558 * The kernel context switch path must contain a spin_lock,
559 * which contains larx/stcx, which will clear any reservation
560 * of the task being switched.
562 #ifdef CONFIG_PPC_BOOK3S
563 /* Cancel all explict user streams as they will have no use after context
564 * switch and will stop the HW from creating streams itself
566 DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r6)
569 addi r6,r4,-THREAD /* Convert THREAD to 'current' */
570 std r6,PACACURRENT(r13) /* Set new 'current' */
572 ld r8,KSP(r4) /* new stack pointer */
573 #ifdef CONFIG_PPC_BOOK3S_64
574 BEGIN_MMU_FTR_SECTION
576 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
578 clrrdi r6,r8,28 /* get its ESID */
579 clrrdi r9,r1,28 /* get current sp ESID */
581 clrrdi r6,r8,40 /* get its 1T ESID */
582 clrrdi r9,r1,40 /* get current sp 1T ESID */
583 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_1T_SEGMENT)
584 clrldi. r0,r6,2 /* is new ESID c00000000? */
585 cmpd cr1,r6,r9 /* or is new ESID the same as current ESID? */
587 beq 2f /* if yes, don't slbie it */
589 /* Bolt in the new stack SLB entry */
590 ld r7,KSP_VSID(r4) /* Get new stack's VSID */
591 oris r0,r6,(SLB_ESID_V)@h
592 ori r0,r0,(SLB_NUM_BOLTED-1)@l
594 li r9,MMU_SEGSIZE_1T /* insert B field */
595 oris r6,r6,(MMU_SEGSIZE_1T << SLBIE_SSIZE_SHIFT)@h
596 rldimi r7,r9,SLB_VSID_SSIZE_SHIFT,0
597 END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
599 /* Update the last bolted SLB. No write barriers are needed
600 * here, provided we only update the current CPU's SLB shadow
603 ld r9,PACA_SLBSHADOWPTR(r13)
605 std r12,SLBSHADOW_STACKESID(r9) /* Clear ESID */
606 li r12,SLBSHADOW_STACKVSID
607 STDX_BE r7,r12,r9 /* Save VSID */
608 li r12,SLBSHADOW_STACKESID
609 STDX_BE r0,r12,r9 /* Save ESID */
611 /* No need to check for MMU_FTR_NO_SLBIE_B here, since when
612 * we have 1TB segments, the only CPUs known to have the errata
613 * only support less than 1TB of system memory and we'll never
614 * actually hit this code path.
619 slbie r6 /* Workaround POWER5 < DD2.1 issue */
623 #endif /* CONFIG_PPC_BOOK3S_64 */
625 CURRENT_THREAD_INFO(r7, r8) /* base of new stack */
626 /* Note: this uses SWITCH_FRAME_SIZE rather than INT_FRAME_SIZE
627 because we don't need to leave the 288-byte ABI gap at the
628 top of the kernel stack. */
629 addi r7,r7,THREAD_SIZE-SWITCH_FRAME_SIZE
632 * PMU interrupts in radix may come in here. They will use r1, not
633 * PACAKSAVE, so this stack switch will not cause a problem. They
634 * will store to the process stack, which may then be migrated to
635 * another CPU. However the rq lock release on this CPU paired with
636 * the rq lock acquire on the new CPU before the stack becomes
637 * active on the new CPU, will order those stores.
639 mr r1,r8 /* start using new stack pointer */
640 std r7,PACAKSAVE(r13)
645 /* r3-r13 are destroyed -- Cort */
649 /* convert old thread to its task_struct for return value */
651 ld r7,_NIP(r1) /* Return to _switch caller in new task */
653 addi r1,r1,SWITCH_FRAME_SIZE
657 _GLOBAL(ret_from_except)
660 bne ret_from_except_lite
663 _GLOBAL(ret_from_except_lite)
665 * Disable interrupts so that current_thread_info()->flags
666 * can't change between when we test it and when we return
667 * from the interrupt.
669 #ifdef CONFIG_PPC_BOOK3E
673 mtmsrd r10,1 /* Update machine state */
674 #endif /* CONFIG_PPC_BOOK3E */
676 CURRENT_THREAD_INFO(r9, r1)
678 #ifdef CONFIG_PPC_BOOK3E
679 ld r10,PACACURRENT(r13)
680 #endif /* CONFIG_PPC_BOOK3E */
684 #ifdef CONFIG_PPC_BOOK3E
685 lwz r3,(THREAD+THREAD_DBCR0)(r10)
686 #endif /* CONFIG_PPC_BOOK3E */
688 /* Check current_thread_info()->flags */
689 andi. r0,r4,_TIF_USER_WORK_MASK
691 #ifdef CONFIG_PPC_BOOK3E
693 * Check to see if the dbcr0 register is set up to debug.
694 * Use the internal debug mode bit to do this.
696 andis. r0,r3,DBCR0_IDM@h
699 rlwinm r0,r0,0,~MSR_DE /* Clear MSR.DE */
706 addi r3,r1,STACK_FRAME_OVERHEAD
710 1: andi. r0,r4,_TIF_NEED_RESCHED
712 bl restore_interrupts
714 b ret_from_except_lite
716 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
717 andi. r0,r4,_TIF_USER_WORK_MASK & ~_TIF_RESTORE_TM
718 bne 3f /* only restore TM if nothing else to do */
719 addi r3,r1,STACK_FRAME_OVERHEAD
726 * Use a non volatile GPR to save and restore our thread_info flags
727 * across the call to restore_interrupts.
730 bl restore_interrupts
732 addi r3,r1,STACK_FRAME_OVERHEAD
737 /* check current_thread_info, _TIF_EMULATE_STACK_STORE */
738 andis. r8,r4,_TIF_EMULATE_STACK_STORE@h
741 addi r8,r1,INT_FRAME_SIZE /* Get the kprobed function entry */
744 subi r3,r3,INT_FRAME_SIZE /* dst: Allocate a trampoline exception frame */
745 mr r4,r1 /* src: current exception frame */
746 mr r1,r3 /* Reroute the trampoline frame to r1 */
748 /* Copy from the original to the trampoline. */
749 li r5,INT_FRAME_SIZE/8 /* size: INT_FRAME_SIZE */
750 li r6,0 /* start offset: 0 */
757 /* Do real store operation to complete stdu */
761 /* Clear _TIF_EMULATE_STACK_STORE flag */
762 lis r11,_TIF_EMULATE_STACK_STORE@h
770 #ifdef CONFIG_PREEMPT
771 /* Check if we need to preempt */
772 andi. r0,r4,_TIF_NEED_RESCHED
774 /* Check that preempt_count() == 0 and interrupts are enabled */
775 lwz r8,TI_PREEMPT(r9)
779 andi. r0,r0,IRQS_DISABLED
783 * Here we are preempting the current task. We want to make
784 * sure we are soft-disabled first and reconcile irq state.
786 RECONCILE_IRQ_STATE(r3,r4)
787 1: bl preempt_schedule_irq
789 /* Re-test flags and eventually loop */
790 CURRENT_THREAD_INFO(r9, r1)
792 andi. r0,r4,_TIF_NEED_RESCHED
796 * arch_local_irq_restore() from preempt_schedule_irq above may
797 * enable hard interrupt but we really should disable interrupts
798 * when we return from the interrupt, and so that we don't get
799 * interrupted after loading SRR0/1.
801 #ifdef CONFIG_PPC_BOOK3E
805 mtmsrd r10,1 /* Update machine state */
806 #endif /* CONFIG_PPC_BOOK3E */
807 #endif /* CONFIG_PREEMPT */
809 .globl fast_exc_return_irq
813 * This is the main kernel exit path. First we check if we
814 * are about to re-enable interrupts
817 lbz r6,PACAIRQSOFTMASK(r13)
818 andi. r5,r5,IRQS_DISABLED
819 bne .Lrestore_irq_off
821 /* We are enabling, were we already enabled ? Yes, just return */
822 andi. r6,r6,IRQS_DISABLED
826 * We are about to soft-enable interrupts (we are hard disabled
827 * at this point). We check if there's anything that needs to
830 lbz r0,PACAIRQHAPPENED(r13)
832 bne- .Lrestore_check_irq_replay
835 * Get here when nothing happened while soft-disabled, just
836 * soft-enable and move-on. We will hard-enable as a side
842 stb r0,PACAIRQSOFTMASK(r13);
845 * Final return path. BookE is handled in a different file
848 #ifdef CONFIG_PPC_BOOK3E
849 b exception_return_book3e
852 * Clear the reservation. If we know the CPU tracks the address of
853 * the reservation then we can potentially save some cycles and use
854 * a larx. On POWER6 and POWER7 this is significantly faster.
857 stdcx. r0,0,r1 /* to clear the reservation */
860 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
863 * Some code path such as load_up_fpu or altivec return directly
864 * here. They run entirely hard disabled and do not alter the
865 * interrupt state. They also don't use lwarx/stwcx. and thus
866 * are known not to leave dangling reservations.
868 .globl fast_exception_return
869 fast_exception_return:
881 beq- .Lunrecov_restore
883 /* Load PPR from thread struct before we clear MSR:RI */
885 ld r2,PACACURRENT(r13)
886 ld r2,TASKTHREADPPR(r2)
887 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
890 * Clear RI before restoring r13. If we are returning to
891 * userspace and we take an exception after restoring r13,
892 * we end up corrupting the userspace r13 value.
897 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
899 std r3, PACATMSCRATCH(r13) /* Stash returned-to MSR */
902 * r13 is our per cpu area, only restore it if we are returning to
903 * userspace the value stored in the stack frame may belong to
909 mtspr SPRN_PPR,r2 /* Restore PPR */
910 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
911 ACCOUNT_CPU_USER_EXIT(r13, r2, r4)
927 b . /* prevent speculative execution */
929 1: mtspr SPRN_SRR1,r3
942 b . /* prevent speculative execution */
944 #endif /* CONFIG_PPC_BOOK3E */
947 * We are returning to a context with interrupts soft disabled.
949 * However, we may also about to hard enable, so we need to
950 * make sure that in this case, we also clear PACA_IRQ_HARD_DIS
951 * or that bit can get out of sync and bad things will happen
955 lbz r7,PACAIRQHAPPENED(r13)
958 rlwinm r7,r7,0,~PACA_IRQ_HARD_DIS
959 stb r7,PACAIRQHAPPENED(r13)
961 #if defined(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG) && defined(CONFIG_BUG)
962 /* The interrupt should not have soft enabled. */
963 lbz r7,PACAIRQSOFTMASK(r13)
964 1: tdeqi r7,IRQS_ENABLED
965 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
970 * Something did happen, check if a re-emit is needed
971 * (this also clears paca->irq_happened)
973 .Lrestore_check_irq_replay:
974 /* XXX: We could implement a fast path here where we check
975 * for irq_happened being just 0x01, in which case we can
976 * clear it and return. That means that we would potentially
977 * miss a decrementer having wrapped all the way around.
979 * Still, this might be useful for things like hash_page
981 bl __check_irq_replay
983 beq .Lrestore_no_replay
986 * We need to re-emit an interrupt. We do so by re-using our
987 * existing exception frame. We first change the trap value,
988 * but we need to ensure we preserve the low nibble of it
996 * Then find the right handler and call it. Interrupts are
997 * still soft-disabled and we keep them that way.
1001 addi r3,r1,STACK_FRAME_OVERHEAD;
1004 1: cmpwi cr0,r3,0xf00
1006 addi r3,r1,STACK_FRAME_OVERHEAD;
1007 bl performance_monitor_exception
1009 1: cmpwi cr0,r3,0xe60
1011 addi r3,r1,STACK_FRAME_OVERHEAD;
1012 bl handle_hmi_exception
1014 1: cmpwi cr0,r3,0x900
1016 addi r3,r1,STACK_FRAME_OVERHEAD;
1019 #ifdef CONFIG_PPC_DOORBELL
1021 #ifdef CONFIG_PPC_BOOK3E
1025 #endif /* CONFIG_PPC_BOOK3E */
1027 addi r3,r1,STACK_FRAME_OVERHEAD;
1028 bl doorbell_exception
1029 #endif /* CONFIG_PPC_DOORBELL */
1030 1: b ret_from_except /* What else to do here ? */
1033 addi r3,r1,STACK_FRAME_OVERHEAD
1034 bl unrecoverable_exception
1037 _ASM_NOKPROBE_SYMBOL(ret_from_except);
1038 _ASM_NOKPROBE_SYMBOL(ret_from_except_lite);
1039 _ASM_NOKPROBE_SYMBOL(resume_kernel);
1040 _ASM_NOKPROBE_SYMBOL(fast_exc_return_irq);
1041 _ASM_NOKPROBE_SYMBOL(restore);
1042 _ASM_NOKPROBE_SYMBOL(fast_exception_return);
1045 #ifdef CONFIG_PPC_RTAS
1047 * On CHRP, the Run-Time Abstraction Services (RTAS) have to be
1048 * called with the MMU off.
1050 * In addition, we need to be in 32b mode, at least for now.
1052 * Note: r3 is an input parameter to rtas, so don't trash it...
1057 stdu r1,-RTAS_FRAME_SIZE(r1) /* Save SP and create stack space. */
1059 /* Because RTAS is running in 32b mode, it clobbers the high order half
1060 * of all registers that it saves. We therefore save those registers
1061 * RTAS might touch to the stack. (r0, r3-r13 are caller saved)
1063 SAVE_GPR(2, r1) /* Save the TOC */
1064 SAVE_GPR(13, r1) /* Save paca */
1065 SAVE_8GPRS(14, r1) /* Save the non-volatiles */
1066 SAVE_10GPRS(22, r1) /* ditto */
1079 /* Temporary workaround to clear CR until RTAS can be modified to
1086 /* There is no way it is acceptable to get here with interrupts enabled,
1087 * check it with the asm equivalent of WARN_ON
1089 lbz r0,PACAIRQSOFTMASK(r13)
1090 1: tdeqi r0,IRQS_ENABLED
1091 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
1094 /* Hard-disable interrupts */
1100 /* Unfortunately, the stack pointer and the MSR are also clobbered,
1101 * so they are saved in the PACA which allows us to restore
1102 * our original state after RTAS returns.
1105 std r6,PACASAVEDMSR(r13)
1107 /* Setup our real return addr */
1108 LOAD_REG_ADDR(r4,rtas_return_loc)
1109 clrldi r4,r4,2 /* convert to realmode address */
1113 ori r0,r0,MSR_EE|MSR_SE|MSR_BE|MSR_RI
1117 rldicr r9,r9,MSR_SF_LG,(63-MSR_SF_LG)
1118 ori r9,r9,MSR_IR|MSR_DR|MSR_FE0|MSR_FE1|MSR_FP|MSR_RI|MSR_LE
1122 sync /* disable interrupts so SRR0/1 */
1123 mtmsrd r0 /* don't get trashed */
1125 LOAD_REG_ADDR(r4, rtas)
1126 ld r5,RTASENTRY(r4) /* get the rtas->entry value */
1127 ld r4,RTASBASE(r4) /* get the rtas->base value */
1132 b . /* prevent speculative execution */
1138 * Clear RI and set SF before anything.
1143 sldi r0,r0,(MSR_SF_LG - MSR_RI_LG)
1148 /* relocation is off at this point */
1150 clrldi r4,r4,2 /* convert to realmode address */
1154 ld r3,(1f-0b)(r3) /* get &rtas_restore_regs */
1156 ld r1,PACAR1(r4) /* Restore our SP */
1157 ld r4,PACASAVEDMSR(r4) /* Restore our MSR */
1162 b . /* prevent speculative execution */
1163 _ASM_NOKPROBE_SYMBOL(__enter_rtas)
1164 _ASM_NOKPROBE_SYMBOL(rtas_return_loc)
1167 1: .8byte rtas_restore_regs
1170 /* relocation is on at this point */
1171 REST_GPR(2, r1) /* Restore the TOC */
1172 REST_GPR(13, r1) /* Restore paca */
1173 REST_8GPRS(14, r1) /* Restore the non-volatiles */
1174 REST_10GPRS(22, r1) /* ditto */
1189 addi r1,r1,RTAS_FRAME_SIZE /* Unstack our frame */
1190 ld r0,16(r1) /* get return address */
1193 blr /* return to caller */
1195 #endif /* CONFIG_PPC_RTAS */
1200 stdu r1,-PROM_FRAME_SIZE(r1) /* Save SP and create stack space */
1202 /* Because PROM is running in 32b mode, it clobbers the high order half
1203 * of all registers that it saves. We therefore save those registers
1204 * PROM might touch to the stack. (r0, r3-r13 are caller saved)
1215 /* Put PROM address in SRR0 */
1218 /* Setup our trampoline return addr in LR */
1221 addi r4,r4,(1f - 0b)
1224 /* Prepare a 32-bit mode big endian MSR
1226 #ifdef CONFIG_PPC_BOOK3E
1227 rlwinm r11,r11,0,1,31
1230 #else /* CONFIG_PPC_BOOK3E */
1231 LOAD_REG_IMMEDIATE(r12, MSR_SF | MSR_ISF | MSR_LE)
1235 #endif /* CONFIG_PPC_BOOK3E */
1237 1: /* Return from OF */
1240 /* Just make sure that r1 top 32 bits didn't get
1245 /* Restore the MSR (back to 64 bits) */
1250 /* Restore other registers */
1258 addi r1,r1,PROM_FRAME_SIZE