1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * The file intends to implement PE based on the information from
4 * platforms. Basically, there have 3 types of PEs: PHB/Bus/Device.
5 * All the PEs should be organized as hierarchy tree. The first level
6 * of the tree will be associated to existing PHBs since the particular
7 * PE is only meaningful in one PHB domain.
9 * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2012.
12 #include <linux/delay.h>
13 #include <linux/export.h>
14 #include <linux/gfp.h>
15 #include <linux/kernel.h>
16 #include <linux/pci.h>
17 #include <linux/string.h>
19 #include <asm/pci-bridge.h>
20 #include <asm/ppc-pci.h>
22 static int eeh_pe_aux_size = 0;
23 static LIST_HEAD(eeh_phb_pe);
26 * eeh_set_pe_aux_size - Set PE auxillary data size
27 * @size: PE auxillary data size
29 * Set PE auxillary data size
31 void eeh_set_pe_aux_size(int size)
36 eeh_pe_aux_size = size;
40 * eeh_pe_alloc - Allocate PE
41 * @phb: PCI controller
44 * Allocate PE instance dynamically.
46 static struct eeh_pe *eeh_pe_alloc(struct pci_controller *phb, int type)
51 alloc_size = sizeof(struct eeh_pe);
52 if (eeh_pe_aux_size) {
53 alloc_size = ALIGN(alloc_size, cache_line_size());
54 alloc_size += eeh_pe_aux_size;
58 pe = kzalloc(alloc_size, GFP_KERNEL);
61 /* Initialize PHB PE */
64 INIT_LIST_HEAD(&pe->child_list);
65 INIT_LIST_HEAD(&pe->edevs);
67 pe->data = (void *)pe + ALIGN(sizeof(struct eeh_pe),
73 * eeh_phb_pe_create - Create PHB PE
74 * @phb: PCI controller
76 * The function should be called while the PHB is detected during
77 * system boot or PCI hotplug in order to create PHB PE.
79 int eeh_phb_pe_create(struct pci_controller *phb)
84 pe = eeh_pe_alloc(phb, EEH_PE_PHB);
86 pr_err("%s: out of memory!\n", __func__);
90 /* Put it into the list */
91 list_add_tail(&pe->child, &eeh_phb_pe);
93 pr_debug("EEH: Add PE for PHB#%x\n", phb->global_number);
99 * eeh_wait_state - Wait for PE state
101 * @max_wait: maximal period in millisecond
103 * Wait for the state of associated PE. It might take some time
104 * to retrieve the PE's state.
106 int eeh_wait_state(struct eeh_pe *pe, int max_wait)
112 * According to PAPR, the state of PE might be temporarily
113 * unavailable. Under the circumstance, we have to wait
114 * for indicated time determined by firmware. The maximal
115 * wait time is 5 minutes, which is acquired from the original
116 * EEH implementation. Also, the original implementation
117 * also defined the minimal wait time as 1 second.
119 #define EEH_STATE_MIN_WAIT_TIME (1000)
120 #define EEH_STATE_MAX_WAIT_TIME (300 * 1000)
123 ret = eeh_ops->get_state(pe, &mwait);
125 if (ret != EEH_STATE_UNAVAILABLE)
129 pr_warn("%s: Timeout when getting PE's state (%d)\n",
131 return EEH_STATE_NOT_SUPPORT;
134 if (mwait < EEH_STATE_MIN_WAIT_TIME) {
135 pr_warn("%s: Firmware returned bad wait value %d\n",
137 mwait = EEH_STATE_MIN_WAIT_TIME;
138 } else if (mwait > EEH_STATE_MAX_WAIT_TIME) {
139 pr_warn("%s: Firmware returned too long wait value %d\n",
141 mwait = EEH_STATE_MAX_WAIT_TIME;
144 msleep(min(mwait, max_wait));
150 * eeh_phb_pe_get - Retrieve PHB PE based on the given PHB
151 * @phb: PCI controller
153 * The overall PEs form hierarchy tree. The first layer of the
154 * hierarchy tree is composed of PHB PEs. The function is used
155 * to retrieve the corresponding PHB PE according to the given PHB.
157 struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb)
161 list_for_each_entry(pe, &eeh_phb_pe, child) {
163 * Actually, we needn't check the type since
164 * the PE for PHB has been determined when that
167 if ((pe->type & EEH_PE_PHB) && pe->phb == phb)
175 * eeh_pe_next - Retrieve the next PE in the tree
179 * The function is used to retrieve the next PE in the
182 struct eeh_pe *eeh_pe_next(struct eeh_pe *pe, struct eeh_pe *root)
184 struct list_head *next = pe->child_list.next;
186 if (next == &pe->child_list) {
190 next = pe->child.next;
191 if (next != &pe->parent->child_list)
197 return list_entry(next, struct eeh_pe, child);
201 * eeh_pe_traverse - Traverse PEs in the specified PHB
204 * @flag: extra parameter to callback
206 * The function is used to traverse the specified PE and its
207 * child PEs. The traversing is to be terminated once the
208 * callback returns something other than NULL, or no more PEs
211 void *eeh_pe_traverse(struct eeh_pe *root,
212 eeh_pe_traverse_func fn, void *flag)
217 eeh_for_each_pe(root, pe) {
226 * eeh_pe_dev_traverse - Traverse the devices from the PE
228 * @fn: function callback
229 * @flag: extra parameter to callback
231 * The function is used to traverse the devices of the specified
232 * PE and its child PEs.
234 void *eeh_pe_dev_traverse(struct eeh_pe *root,
235 eeh_edev_traverse_func fn, void *flag)
238 struct eeh_dev *edev, *tmp;
242 pr_warn("%s: Invalid PE %p\n",
247 /* Traverse root PE */
248 eeh_for_each_pe(root, pe) {
249 eeh_pe_for_each_dev(pe, edev, tmp) {
250 ret = fn(edev, flag);
260 * __eeh_pe_get - Check the PE address
264 * For one particular PE, it can be identified by PE address
265 * or tranditional BDF address. BDF address is composed of
266 * Bus/Device/Function number. The extra data referred by flag
267 * indicates which type of address should be used.
269 struct eeh_pe_get_flag {
274 static void *__eeh_pe_get(struct eeh_pe *pe, void *flag)
276 struct eeh_pe_get_flag *tmp = (struct eeh_pe_get_flag *) flag;
278 /* Unexpected PHB PE */
279 if (pe->type & EEH_PE_PHB)
283 * We prefer PE address. For most cases, we should
284 * have non-zero PE address
286 if (eeh_has_flag(EEH_VALID_PE_ZERO)) {
287 if (tmp->pe_no == pe->addr)
291 (tmp->pe_no == pe->addr))
295 /* Try BDF address */
296 if (tmp->config_addr &&
297 (tmp->config_addr == pe->config_addr))
304 * eeh_pe_get - Search PE based on the given address
305 * @phb: PCI controller
307 * @config_addr: Config address
309 * Search the corresponding PE based on the specified address which
310 * is included in the eeh device. The function is used to check if
311 * the associated PE has been created against the PE address. It's
312 * notable that the PE address has 2 format: traditional PE address
313 * which is composed of PCI bus/device/function number, or unified
316 struct eeh_pe *eeh_pe_get(struct pci_controller *phb,
317 int pe_no, int config_addr)
319 struct eeh_pe *root = eeh_phb_pe_get(phb);
320 struct eeh_pe_get_flag tmp = { pe_no, config_addr };
323 pe = eeh_pe_traverse(root, __eeh_pe_get, &tmp);
329 * eeh_pe_get_parent - Retrieve the parent PE
332 * The whole PEs existing in the system are organized as hierarchy
333 * tree. The function is used to retrieve the parent PE according
334 * to the parent EEH device.
336 static struct eeh_pe *eeh_pe_get_parent(struct eeh_dev *edev)
338 struct eeh_dev *parent;
339 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
342 * It might have the case for the indirect parent
343 * EEH device already having associated PE, but
344 * the direct parent EEH device doesn't have yet.
347 pdn = pci_get_pdn(edev->physfn);
349 pdn = pdn ? pdn->parent : NULL;
351 /* We're poking out of PCI territory */
352 parent = pdn_to_eeh_dev(pdn);
366 * eeh_add_to_parent_pe - Add EEH device to parent PE
369 * Add EEH device to the parent PE. If the parent PE already
370 * exists, the PE type will be changed to EEH_PE_BUS. Otherwise,
371 * we have to create new PE to hold the EEH device and the new
372 * PE will be linked to its parent PE as well.
374 int eeh_add_to_parent_pe(struct eeh_dev *edev)
376 struct eeh_pe *pe, *parent;
377 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
378 int config_addr = (pdn->busno << 8) | (pdn->devfn);
380 /* Check if the PE number is valid */
381 if (!eeh_has_flag(EEH_VALID_PE_ZERO) && !edev->pe_config_addr) {
382 pr_err("%s: Invalid PE#0 for edev 0x%x on PHB#%x\n",
383 __func__, config_addr, pdn->phb->global_number);
388 * Search the PE has been existing or not according
389 * to the PE address. If that has been existing, the
390 * PE should be composed of PCI bus and its subordinate
393 pe = eeh_pe_get(pdn->phb, edev->pe_config_addr, config_addr);
394 if (pe && !(pe->type & EEH_PE_INVALID)) {
395 /* Mark the PE as type of PCI bus */
396 pe->type = EEH_PE_BUS;
399 /* Put the edev to PE */
400 list_add_tail(&edev->entry, &pe->edevs);
401 pr_debug("EEH: Add %04x:%02x:%02x.%01x to Bus PE#%x\n",
402 pdn->phb->global_number,
404 PCI_SLOT(pdn->devfn),
405 PCI_FUNC(pdn->devfn),
408 } else if (pe && (pe->type & EEH_PE_INVALID)) {
409 list_add_tail(&edev->entry, &pe->edevs);
412 * We're running to here because of PCI hotplug caused by
413 * EEH recovery. We need clear EEH_PE_INVALID until the top.
417 if (!(parent->type & EEH_PE_INVALID))
419 parent->type &= ~EEH_PE_INVALID;
420 parent = parent->parent;
423 pr_debug("EEH: Add %04x:%02x:%02x.%01x to Device "
424 "PE#%x, Parent PE#%x\n",
425 pdn->phb->global_number,
427 PCI_SLOT(pdn->devfn),
428 PCI_FUNC(pdn->devfn),
429 pe->addr, pe->parent->addr);
433 /* Create a new EEH PE */
435 pe = eeh_pe_alloc(pdn->phb, EEH_PE_VF);
437 pe = eeh_pe_alloc(pdn->phb, EEH_PE_DEVICE);
439 pr_err("%s: out of memory!\n", __func__);
442 pe->addr = edev->pe_config_addr;
443 pe->config_addr = config_addr;
446 * Put the new EEH PE into hierarchy tree. If the parent
447 * can't be found, the newly created PE will be attached
448 * to PHB directly. Otherwise, we have to associate the
449 * PE with its parent.
451 parent = eeh_pe_get_parent(edev);
453 parent = eeh_phb_pe_get(pdn->phb);
455 pr_err("%s: No PHB PE is found (PHB Domain=%d)\n",
456 __func__, pdn->phb->global_number);
465 * Put the newly created PE into the child list and
466 * link the EEH device accordingly.
468 list_add_tail(&pe->child, &parent->child_list);
469 list_add_tail(&edev->entry, &pe->edevs);
471 pr_debug("EEH: Add %04x:%02x:%02x.%01x to "
472 "Device PE#%x, Parent PE#%x\n",
473 pdn->phb->global_number,
475 PCI_SLOT(pdn->devfn),
476 PCI_FUNC(pdn->devfn),
477 pe->addr, pe->parent->addr);
483 * eeh_rmv_from_parent_pe - Remove one EEH device from the associated PE
486 * The PE hierarchy tree might be changed when doing PCI hotplug.
487 * Also, the PCI devices or buses could be removed from the system
488 * during EEH recovery. So we have to call the function remove the
489 * corresponding PE accordingly if necessary.
491 int eeh_rmv_from_parent_pe(struct eeh_dev *edev)
493 struct eeh_pe *pe, *parent, *child;
495 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
497 pe = eeh_dev_to_pe(edev);
499 pr_debug("%s: No PE found for device %04x:%02x:%02x.%01x\n",
500 __func__, pdn->phb->global_number,
502 PCI_SLOT(pdn->devfn),
503 PCI_FUNC(pdn->devfn));
507 /* Remove the EEH device */
509 list_del(&edev->entry);
512 * Check if the parent PE includes any EEH devices.
513 * If not, we should delete that. Also, we should
514 * delete the parent PE if it doesn't have associated
515 * child PEs and EEH devices.
519 if (pe->type & EEH_PE_PHB)
522 if (!(pe->state & EEH_PE_KEEP)) {
523 if (list_empty(&pe->edevs) &&
524 list_empty(&pe->child_list)) {
525 list_del(&pe->child);
531 if (list_empty(&pe->edevs)) {
533 list_for_each_entry(child, &pe->child_list, child) {
534 if (!(child->type & EEH_PE_INVALID)) {
541 pe->type |= EEH_PE_INVALID;
554 * eeh_pe_update_time_stamp - Update PE's frozen time stamp
557 * We have time stamp for each PE to trace its time of getting
558 * frozen in last hour. The function should be called to update
559 * the time stamp on first error of the specific PE. On the other
560 * handle, we needn't account for errors happened in last hour.
562 void eeh_pe_update_time_stamp(struct eeh_pe *pe)
568 if (pe->freeze_count <= 0) {
569 pe->freeze_count = 0;
570 pe->tstamp = ktime_get_seconds();
572 tstamp = ktime_get_seconds();
573 if (tstamp - pe->tstamp > 3600) {
575 pe->freeze_count = 0;
581 * eeh_pe_state_mark - Mark specified state for PE and its associated device
584 * EEH error affects the current PE and its child PEs. The function
585 * is used to mark appropriate state for the affected PEs and the
586 * associated devices.
588 void eeh_pe_state_mark(struct eeh_pe *root, int state)
592 eeh_for_each_pe(root, pe)
593 if (!(pe->state & EEH_PE_REMOVED))
596 EXPORT_SYMBOL_GPL(eeh_pe_state_mark);
599 * eeh_pe_mark_isolated
602 * Record that a PE has been isolated by marking the PE and it's children as
603 * EEH_PE_ISOLATED (and EEH_PE_CFG_BLOCKED, if required) and their PCI devices
604 * as pci_channel_io_frozen.
606 void eeh_pe_mark_isolated(struct eeh_pe *root)
609 struct eeh_dev *edev;
610 struct pci_dev *pdev;
612 eeh_pe_state_mark(root, EEH_PE_ISOLATED);
613 eeh_for_each_pe(root, pe) {
614 list_for_each_entry(edev, &pe->edevs, entry) {
615 pdev = eeh_dev_to_pci_dev(edev);
617 pdev->error_state = pci_channel_io_frozen;
619 /* Block PCI config access if required */
620 if (pe->state & EEH_PE_CFG_RESTRICTED)
621 pe->state |= EEH_PE_CFG_BLOCKED;
624 EXPORT_SYMBOL_GPL(eeh_pe_mark_isolated);
626 static void *__eeh_pe_dev_mode_mark(struct eeh_dev *edev, void *flag)
628 int mode = *((int *)flag);
636 * eeh_pe_dev_state_mark - Mark state for all device under the PE
639 * Mark specific state for all child devices of the PE.
641 void eeh_pe_dev_mode_mark(struct eeh_pe *pe, int mode)
643 eeh_pe_dev_traverse(pe, __eeh_pe_dev_mode_mark, &mode);
647 * eeh_pe_state_clear - Clear state for the PE
650 * @include_passed: include passed-through devices?
652 * The function is used to clear the indicated state from the
653 * given PE. Besides, we also clear the check count of the PE
656 void eeh_pe_state_clear(struct eeh_pe *root, int state, bool include_passed)
659 struct eeh_dev *edev, *tmp;
660 struct pci_dev *pdev;
662 eeh_for_each_pe(root, pe) {
663 /* Keep the state of permanently removed PE intact */
664 if (pe->state & EEH_PE_REMOVED)
667 if (!include_passed && eeh_pe_passed(pe))
673 * Special treatment on clearing isolated state. Clear
674 * check count since last isolation and put all affected
675 * devices to normal state.
677 if (!(state & EEH_PE_ISOLATED))
681 eeh_pe_for_each_dev(pe, edev, tmp) {
682 pdev = eeh_dev_to_pci_dev(edev);
686 pdev->error_state = pci_channel_io_normal;
689 /* Unblock PCI config access if required */
690 if (pe->state & EEH_PE_CFG_RESTRICTED)
691 pe->state &= ~EEH_PE_CFG_BLOCKED;
696 * Some PCI bridges (e.g. PLX bridges) have primary/secondary
697 * buses assigned explicitly by firmware, and we probably have
698 * lost that after reset. So we have to delay the check until
699 * the PCI-CFG registers have been restored for the parent
702 * Don't use normal PCI-CFG accessors, which probably has been
703 * blocked on normal path during the stage. So we need utilize
704 * eeh operations, which is always permitted.
706 static void eeh_bridge_check_link(struct eeh_dev *edev)
708 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
714 * We only check root port and downstream ports of
717 if (!(edev->mode & (EEH_DEV_ROOT_PORT | EEH_DEV_DS_PORT)))
720 pr_debug("%s: Check PCIe link for %04x:%02x:%02x.%01x ...\n",
721 __func__, pdn->phb->global_number,
723 PCI_SLOT(pdn->devfn),
724 PCI_FUNC(pdn->devfn));
726 /* Check slot status */
727 cap = edev->pcie_cap;
728 eeh_ops->read_config(pdn, cap + PCI_EXP_SLTSTA, 2, &val);
729 if (!(val & PCI_EXP_SLTSTA_PDS)) {
730 pr_debug(" No card in the slot (0x%04x) !\n", val);
734 /* Check power status if we have the capability */
735 eeh_ops->read_config(pdn, cap + PCI_EXP_SLTCAP, 2, &val);
736 if (val & PCI_EXP_SLTCAP_PCP) {
737 eeh_ops->read_config(pdn, cap + PCI_EXP_SLTCTL, 2, &val);
738 if (val & PCI_EXP_SLTCTL_PCC) {
739 pr_debug(" In power-off state, power it on ...\n");
740 val &= ~(PCI_EXP_SLTCTL_PCC | PCI_EXP_SLTCTL_PIC);
741 val |= (0x0100 & PCI_EXP_SLTCTL_PIC);
742 eeh_ops->write_config(pdn, cap + PCI_EXP_SLTCTL, 2, val);
748 eeh_ops->read_config(pdn, cap + PCI_EXP_LNKCTL, 2, &val);
749 val &= ~PCI_EXP_LNKCTL_LD;
750 eeh_ops->write_config(pdn, cap + PCI_EXP_LNKCTL, 2, val);
753 eeh_ops->read_config(pdn, cap + PCI_EXP_LNKCAP, 4, &val);
754 if (!(val & PCI_EXP_LNKCAP_DLLLARC)) {
755 pr_debug(" No link reporting capability (0x%08x) \n", val);
760 /* Wait the link is up until timeout (5s) */
762 while (timeout < 5000) {
766 eeh_ops->read_config(pdn, cap + PCI_EXP_LNKSTA, 2, &val);
767 if (val & PCI_EXP_LNKSTA_DLLLA)
771 if (val & PCI_EXP_LNKSTA_DLLLA)
772 pr_debug(" Link up (%s)\n",
773 (val & PCI_EXP_LNKSTA_CLS_2_5GB) ? "2.5GB" : "5GB");
775 pr_debug(" Link not ready (0x%04x)\n", val);
778 #define BYTE_SWAP(OFF) (8*((OFF)/4)+3-(OFF))
779 #define SAVED_BYTE(OFF) (((u8 *)(edev->config_space))[BYTE_SWAP(OFF)])
781 static void eeh_restore_bridge_bars(struct eeh_dev *edev)
783 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
787 * Device BARs: 0x10 - 0x18
788 * Bus numbers and windows: 0x18 - 0x30
790 for (i = 4; i < 13; i++)
791 eeh_ops->write_config(pdn, i*4, 4, edev->config_space[i]);
793 eeh_ops->write_config(pdn, 14*4, 4, edev->config_space[14]);
795 /* Cache line & Latency timer: 0xC 0xD */
796 eeh_ops->write_config(pdn, PCI_CACHE_LINE_SIZE, 1,
797 SAVED_BYTE(PCI_CACHE_LINE_SIZE));
798 eeh_ops->write_config(pdn, PCI_LATENCY_TIMER, 1,
799 SAVED_BYTE(PCI_LATENCY_TIMER));
800 /* Max latency, min grant, interrupt ping and line: 0x3C */
801 eeh_ops->write_config(pdn, 15*4, 4, edev->config_space[15]);
803 /* PCI Command: 0x4 */
804 eeh_ops->write_config(pdn, PCI_COMMAND, 4, edev->config_space[1] |
805 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
807 /* Check the PCIe link is ready */
808 eeh_bridge_check_link(edev);
811 static void eeh_restore_device_bars(struct eeh_dev *edev)
813 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
817 for (i = 4; i < 10; i++)
818 eeh_ops->write_config(pdn, i*4, 4, edev->config_space[i]);
819 /* 12 == Expansion ROM Address */
820 eeh_ops->write_config(pdn, 12*4, 4, edev->config_space[12]);
822 eeh_ops->write_config(pdn, PCI_CACHE_LINE_SIZE, 1,
823 SAVED_BYTE(PCI_CACHE_LINE_SIZE));
824 eeh_ops->write_config(pdn, PCI_LATENCY_TIMER, 1,
825 SAVED_BYTE(PCI_LATENCY_TIMER));
827 /* max latency, min grant, interrupt pin and line */
828 eeh_ops->write_config(pdn, 15*4, 4, edev->config_space[15]);
831 * Restore PERR & SERR bits, some devices require it,
832 * don't touch the other command bits
834 eeh_ops->read_config(pdn, PCI_COMMAND, 4, &cmd);
835 if (edev->config_space[1] & PCI_COMMAND_PARITY)
836 cmd |= PCI_COMMAND_PARITY;
838 cmd &= ~PCI_COMMAND_PARITY;
839 if (edev->config_space[1] & PCI_COMMAND_SERR)
840 cmd |= PCI_COMMAND_SERR;
842 cmd &= ~PCI_COMMAND_SERR;
843 eeh_ops->write_config(pdn, PCI_COMMAND, 4, cmd);
847 * eeh_restore_one_device_bars - Restore the Base Address Registers for one device
851 * Loads the PCI configuration space base address registers,
852 * the expansion ROM base address, the latency timer, and etc.
853 * from the saved values in the device node.
855 static void *eeh_restore_one_device_bars(struct eeh_dev *edev, void *flag)
857 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
859 /* Do special restore for bridges */
860 if (edev->mode & EEH_DEV_BRIDGE)
861 eeh_restore_bridge_bars(edev);
863 eeh_restore_device_bars(edev);
865 if (eeh_ops->restore_config && pdn)
866 eeh_ops->restore_config(pdn);
872 * eeh_pe_restore_bars - Restore the PCI config space info
875 * This routine performs a recursive walk to the children
876 * of this device as well.
878 void eeh_pe_restore_bars(struct eeh_pe *pe)
881 * We needn't take the EEH lock since eeh_pe_dev_traverse()
884 eeh_pe_dev_traverse(pe, eeh_restore_one_device_bars, NULL);
888 * eeh_pe_loc_get - Retrieve location code binding to the given PE
891 * Retrieve the location code of the given PE. If the primary PE bus
892 * is root bus, we will grab location code from PHB device tree node
893 * or root port. Otherwise, the upstream bridge's device tree node
894 * of the primary PE bus will be checked for the location code.
896 const char *eeh_pe_loc_get(struct eeh_pe *pe)
898 struct pci_bus *bus = eeh_pe_bus_get(pe);
899 struct device_node *dn;
900 const char *loc = NULL;
903 dn = pci_bus_to_OF_node(bus);
909 if (pci_is_root_bus(bus))
910 loc = of_get_property(dn, "ibm,io-base-loc-code", NULL);
912 loc = of_get_property(dn, "ibm,slot-location-code",
925 * eeh_pe_bus_get - Retrieve PCI bus according to the given PE
928 * Retrieve the PCI bus according to the given PE. Basically,
929 * there're 3 types of PEs: PHB/Bus/Device. For PHB PE, the
930 * primary PCI bus will be retrieved. The parent bus will be
931 * returned for BUS PE. However, we don't have associated PCI
934 struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe)
936 struct eeh_dev *edev;
937 struct pci_dev *pdev;
939 if (pe->type & EEH_PE_PHB)
942 /* The primary bus might be cached during probe time */
943 if (pe->state & EEH_PE_PRI_BUS)
946 /* Retrieve the parent PCI bus of first (top) PCI device */
947 edev = list_first_entry_or_null(&pe->edevs, struct eeh_dev, entry);
948 pdev = eeh_dev_to_pci_dev(edev);