1 #ifndef _ASM_POWERPC_PROCESSOR_H
2 #define _ASM_POWERPC_PROCESSOR_H
5 * Copyright (C) 2001 PPC 64 Team, IBM Corp
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
19 #define TS_FPROFFSET 0
20 #define TS_VSRLOWOFFSET 1
22 #define TS_FPROFFSET 1
23 #define TS_VSRLOWOFFSET 0
28 #define TS_FPROFFSET 0
32 /* Default SMT priority is set to 3. Use 11- 13bits to save priority. */
33 #define PPR_PRIORITY 3
35 #define DEFAULT_PPR (PPR_PRIORITY << 50)
37 #define DEFAULT_PPR ((u64)PPR_PRIORITY << 50)
38 #endif /* __ASSEMBLY__ */
39 #endif /* CONFIG_PPC64 */
42 #include <linux/types.h>
43 #include <linux/thread_info.h>
44 #include <asm/ptrace.h>
45 #include <asm/hw_breakpoint.h>
47 /* We do _not_ want to define new machine types at all, those must die
48 * in favor of using the device-tree
52 /* PREP sub-platform types. Unused */
53 #define _PREP_Motorola 0x01 /* motorola prep */
54 #define _PREP_Firm 0x02 /* firmworks prep */
55 #define _PREP_IBM 0x00 /* ibm prep */
56 #define _PREP_Bull 0x03 /* bull prep */
58 /* CHRP sub-platform types. These are arbitrary */
59 #define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */
60 #define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */
61 #define _CHRP_Pegasos 0x06 /* Genesi/bplan's Pegasos and Pegasos2 */
62 #define _CHRP_briq 0x07 /* TotalImpact's briQ */
64 #if defined(__KERNEL__) && defined(CONFIG_PPC32)
66 extern int _chrp_type;
68 #endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */
70 /* Macros for adjusting thread priority (hardware multi-threading) */
71 #define HMT_very_low() asm volatile("or 31,31,31 # very low priority")
72 #define HMT_low() asm volatile("or 1,1,1 # low priority")
73 #define HMT_medium_low() asm volatile("or 6,6,6 # medium low priority")
74 #define HMT_medium() asm volatile("or 2,2,2 # medium priority")
75 #define HMT_medium_high() asm volatile("or 5,5,5 # medium high priority")
76 #define HMT_high() asm volatile("or 3,3,3 # high priority")
81 #include <asm/task_size_64.h>
83 #include <asm/task_size_32.h>
87 void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp);
88 void release_thread(struct task_struct *);
94 #define TS_FPR(i) fp_state.fpr[i][TS_FPROFFSET]
95 #define TS_CKFPR(i) ckfp_state.fpr[i][TS_FPROFFSET]
97 /* FP and VSX 0-31 register set */
98 struct thread_fp_state {
99 u64 fpr[32][TS_FPRWIDTH] __attribute__((aligned(16)));
100 u64 fpscr; /* Floating point status */
103 /* Complete AltiVec register set including VSCR */
104 struct thread_vr_state {
105 vector128 vr[32] __attribute__((aligned(16)));
106 vector128 vscr __attribute__((aligned(16)));
110 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
112 * The following help to manage the use of Debug Control Registers
113 * om the BookE platforms.
121 * The stored value of the DBSR register will be the value at the
122 * last debug interrupt. This register can only be read from the
123 * user (will never be written to) and has value while helping to
124 * describe the reason for the last debug trap. Torez
128 * The following will contain addresses used by debug applications
129 * to help trace and trap on particular address locations.
130 * The bits in the Debug Control Registers above help define which
131 * of the following registers will contain valid data and/or addresses.
135 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
141 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
148 struct thread_struct {
149 unsigned long ksp; /* Kernel stack pointer */
152 unsigned long ksp_vsid;
154 struct pt_regs *regs; /* Pointer to saved register state */
155 mm_segment_t addr_limit; /* for get_fs() validation */
157 /* BookE base exception scratch space; align on cacheline */
158 unsigned long normsave[8] ____cacheline_aligned;
161 void *pgdir; /* root of page-table tree */
162 unsigned long ksp_limit; /* if ksp <= ksp_limit stack overflow */
163 #ifdef CONFIG_PPC_RTAS
164 unsigned long rtas_sp; /* stack pointer for when in RTAS */
167 #if defined(CONFIG_PPC_BOOK3S_32) && defined(CONFIG_PPC_KUAP)
168 unsigned long kuap; /* opened segments for user access */
170 /* Debug Registers */
171 struct debug_reg debug;
172 struct thread_fp_state fp_state;
173 struct thread_fp_state *fp_save_area;
174 int fpexc_mode; /* floating-point exception mode */
175 unsigned int align_ctl; /* alignment handling control */
176 #ifdef CONFIG_HAVE_HW_BREAKPOINT
177 struct perf_event *ptrace_bps[HBP_NUM];
179 * Helps identify source of single-step exception and subsequent
180 * hw-breakpoint enablement
182 struct perf_event *last_hit_ubp;
183 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
184 struct arch_hw_breakpoint hw_brk; /* info on the hardware breakpoint */
185 unsigned long trap_nr; /* last trap # on this thread */
186 u8 load_slb; /* Ages out SLB preload cache entries */
188 #ifdef CONFIG_ALTIVEC
190 struct thread_vr_state vr_state;
191 struct thread_vr_state *vr_save_area;
192 unsigned long vrsave;
193 int used_vr; /* set if process has used altivec */
194 #endif /* CONFIG_ALTIVEC */
197 int used_vsr; /* set if process has used VSX */
198 #endif /* CONFIG_VSX */
200 unsigned long evr[32]; /* upper 32-bits of SPE regs */
201 u64 acc; /* Accumulator */
202 unsigned long spefscr; /* SPE & eFP status */
203 unsigned long spefscr_last; /* SPEFSCR value on last prctl
204 call or trap return */
205 int used_spe; /* set if process has used spe */
206 #endif /* CONFIG_SPE */
207 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
209 u64 tm_tfhar; /* Transaction fail handler addr */
210 u64 tm_texasr; /* Transaction exception & summary */
211 u64 tm_tfiar; /* Transaction fail instr address reg */
212 struct pt_regs ckpt_regs; /* Checkpointed registers */
214 unsigned long tm_tar;
215 unsigned long tm_ppr;
216 unsigned long tm_dscr;
219 * Checkpointed FP and VSX 0-31 register set.
221 * When a transaction is active/signalled/scheduled etc., *regs is the
222 * most recent set of/speculated GPRs with ckpt_regs being the older
223 * checkpointed regs to which we roll back if transaction aborts.
225 * These are analogous to how ckpt_regs and pt_regs work
227 struct thread_fp_state ckfp_state; /* Checkpointed FP state */
228 struct thread_vr_state ckvr_state; /* Checkpointed VR state */
229 unsigned long ckvrsave; /* Checkpointed VRSAVE */
230 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
231 #ifdef CONFIG_PPC_MEM_KEYS
236 #ifdef CONFIG_KVM_BOOK3S_32_HANDLER
237 void* kvm_shadow_vcpu; /* KVM internal data */
238 #endif /* CONFIG_KVM_BOOK3S_32_HANDLER */
239 #if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
240 struct kvm_vcpu *kvm_vcpu;
246 * This member element dscr_inherit indicates that the process
247 * has explicitly attempted and changed the DSCR register value
248 * for itself. Hence kernel wont use the default CPU DSCR value
249 * contained in the PACA structure anymore during process context
250 * switch. Once this variable is set, this behaviour will also be
251 * inherited to all the children of this process from that point
257 #ifdef CONFIG_PPC_BOOK3S_64
269 unsigned int used_vas;
273 #define ARCH_MIN_TASKALIGN 16
275 #define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack)
276 #define INIT_SP_LIMIT ((unsigned long)&init_stack)
279 #define SPEFSCR_INIT \
280 .spefscr = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE, \
281 .spefscr_last = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE,
287 #define INIT_THREAD { \
289 .ksp_limit = INIT_SP_LIMIT, \
290 .addr_limit = KERNEL_DS, \
291 .pgdir = swapper_pg_dir, \
292 .fpexc_mode = MSR_FE0 | MSR_FE1, \
296 #define INIT_THREAD { \
298 .regs = (struct pt_regs *)INIT_SP - 1, /* XXX bogus, I think */ \
299 .addr_limit = KERNEL_DS, \
301 .fscr = FSCR_TAR | FSCR_EBB \
305 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.regs)
307 unsigned long get_wchan(struct task_struct *p);
309 #define KSTK_EIP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
310 #define KSTK_ESP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)
312 /* Get/set floating-point exception mode */
313 #define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
314 #define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))
316 extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr);
317 extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val);
319 #define GET_ENDIAN(tsk, adr) get_endian((tsk), (adr))
320 #define SET_ENDIAN(tsk, val) set_endian((tsk), (val))
322 extern int get_endian(struct task_struct *tsk, unsigned long adr);
323 extern int set_endian(struct task_struct *tsk, unsigned int val);
325 #define GET_UNALIGN_CTL(tsk, adr) get_unalign_ctl((tsk), (adr))
326 #define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val))
328 extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr);
329 extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);
331 extern void load_fp_state(struct thread_fp_state *fp);
332 extern void store_fp_state(struct thread_fp_state *fp);
333 extern void load_vr_state(struct thread_vr_state *vr);
334 extern void store_vr_state(struct thread_vr_state *vr);
336 static inline unsigned int __unpack_fe01(unsigned long msr_bits)
338 return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8);
341 static inline unsigned long __pack_fe01(unsigned int fpmode)
343 return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1);
347 #define cpu_relax() do { HMT_low(); HMT_medium(); barrier(); } while (0)
349 #define spin_begin() HMT_low()
351 #define spin_cpu_relax() barrier()
353 #define spin_cpu_yield() spin_cpu_relax()
355 #define spin_end() HMT_medium()
357 #define spin_until_cond(cond) \
359 if (unlikely(!(cond))) { \
369 #define cpu_relax() barrier()
372 /* Check that a certain kernel stack pointer is valid in task_struct p */
373 int validate_sp(unsigned long sp, struct task_struct *p,
374 unsigned long nbytes);
379 #define ARCH_HAS_PREFETCH
380 #define ARCH_HAS_PREFETCHW
381 #define ARCH_HAS_SPINLOCK_PREFETCH
383 static inline void prefetch(const void *x)
388 __asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
391 static inline void prefetchw(const void *x)
396 __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
399 #define spin_lock_prefetch(x) prefetchw(x)
401 #define HAVE_ARCH_PICK_MMAP_LAYOUT
404 static inline unsigned long get_clean_sp(unsigned long sp, int is_32)
407 return sp & 0x0ffffffffUL;
411 static inline unsigned long get_clean_sp(unsigned long sp, int is_32)
417 extern unsigned long cpuidle_disable;
418 enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};
420 extern int powersave_nap; /* set if nap mode can be used in idle loop */
421 extern unsigned long power7_idle_insn(unsigned long type); /* PNV_THREAD_NAP/etc*/
422 extern void power7_idle_type(unsigned long type);
423 extern unsigned long power9_idle_stop(unsigned long psscr_val);
424 extern unsigned long power9_offline_stop(unsigned long psscr_val);
425 extern void power9_idle_type(unsigned long stop_psscr_val,
426 unsigned long stop_psscr_mask);
428 extern void flush_instruction_cache(void);
429 extern void hard_reset_now(void);
430 extern void poweroff_now(void);
431 extern int fix_alignment(struct pt_regs *);
432 extern void cvt_fd(float *from, double *to);
433 extern void cvt_df(double *from, float *to);
434 extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
438 * We handle most unaligned accesses in hardware. On the other hand
439 * unaligned DMA can be very expensive on some ppc64 IO chips (it does
440 * powers of 2 writes until it reaches sufficient alignment).
442 * Based on this we disable the IP header alignment in network drivers.
444 #define NET_IP_ALIGN 0
447 #endif /* __KERNEL__ */
448 #endif /* __ASSEMBLY__ */
449 #endif /* _ASM_POWERPC_PROCESSOR_H */