1 #ifndef _ASM_POWERPC_PGTABLE_H
2 #define _ASM_POWERPC_PGTABLE_H
6 #include <linux/mmdebug.h>
7 #include <linux/mmzone.h>
8 #include <asm/processor.h> /* For TASK_SIZE */
14 #endif /* !__ASSEMBLY__ */
16 #if defined(CONFIG_PPC64)
17 # include <asm/pgtable-ppc64.h>
19 # include <asm/pgtable-ppc32.h>
23 * We save the slot number & secondary bit in the second half of the
24 * PTE page. We use the 8 bytes per each pte entry.
26 #define PTE_PAGE_HIDX_OFFSET (PTRS_PER_PTE * 8)
30 #include <asm/tlbflush.h>
32 /* Generic accessors to PTE bits */
33 static inline int pte_write(pte_t pte)
34 { return (pte_val(pte) & (_PAGE_RW | _PAGE_RO)) != _PAGE_RO; }
35 static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
36 static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
37 static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; }
38 static inline int pte_special(pte_t pte) { return pte_val(pte) & _PAGE_SPECIAL; }
39 static inline int pte_none(pte_t pte) { return (pte_val(pte) & ~_PTE_NONE_MASK) == 0; }
40 static inline pgprot_t pte_pgprot(pte_t pte) { return __pgprot(pte_val(pte) & PAGE_PROT_BITS); }
42 #ifdef CONFIG_NUMA_BALANCING
44 * These work without NUMA balancing but the kernel does not care. See the
45 * comment in include/asm-generic/pgtable.h . On powerpc, this will only
46 * work for user pages and always return true for kernel pages.
48 static inline int pte_protnone(pte_t pte)
50 return (pte_val(pte) &
51 (_PAGE_PRESENT | _PAGE_USER)) == _PAGE_PRESENT;
54 static inline int pmd_protnone(pmd_t pmd)
56 return pte_protnone(pmd_pte(pmd));
59 static inline int pte_present(pte_t pte)
61 return pte_val(pte) & _PAGE_NUMA_MASK;
64 #define pte_present_nonuma pte_present_nonuma
65 static inline int pte_present_nonuma(pte_t pte)
67 return pte_val(pte) & (_PAGE_PRESENT);
70 #define ptep_set_numa ptep_set_numa
71 static inline void ptep_set_numa(struct mm_struct *mm, unsigned long addr,
74 if ((pte_val(*ptep) & _PAGE_PRESENT) == 0)
77 pte_update(mm, addr, ptep, _PAGE_PRESENT, _PAGE_NUMA, 0);
81 #define pmdp_set_numa pmdp_set_numa
82 static inline void pmdp_set_numa(struct mm_struct *mm, unsigned long addr,
85 if ((pmd_val(*pmdp) & _PAGE_PRESENT) == 0)
88 pmd_hugepage_update(mm, addr, pmdp, _PAGE_PRESENT, _PAGE_NUMA);
93 * Generic NUMA pte helpers expect pteval_t and pmdval_t types to exist
94 * which was inherited from x86. For the purposes of powerpc pte_basic_t and
95 * pmd_t are equivalent
97 #define pteval_t pte_basic_t
98 #define pmdval_t pmd_t
99 static inline pteval_t ptenuma_flags(pte_t pte)
101 return pte_val(pte) & _PAGE_NUMA_MASK;
104 static inline pmdval_t pmdnuma_flags(pmd_t pmd)
106 return pmd_val(pmd) & _PAGE_NUMA_MASK;
111 static inline int pte_present(pte_t pte)
113 return pte_val(pte) & _PAGE_PRESENT;
115 #endif /* CONFIG_NUMA_BALANCING */
117 /* Conversion functions: convert a page and protection to a page entry,
118 * and a page entry and page directory to the page they refer to.
120 * Even if PTEs can be unsigned long long, a PFN is always an unsigned
123 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) {
124 return __pte(((pte_basic_t)(pfn) << PTE_RPN_SHIFT) |
125 pgprot_val(pgprot)); }
126 static inline unsigned long pte_pfn(pte_t pte) {
127 return pte_val(pte) >> PTE_RPN_SHIFT; }
129 /* Keep these as a macros to avoid include dependency mess */
130 #define pte_page(x) pfn_to_page(pte_pfn(x))
131 #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
133 /* Generic modifiers for PTE bits */
134 static inline pte_t pte_wrprotect(pte_t pte) {
135 pte_val(pte) &= ~(_PAGE_RW | _PAGE_HWWRITE);
136 pte_val(pte) |= _PAGE_RO; return pte; }
137 static inline pte_t pte_mkclean(pte_t pte) {
138 pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HWWRITE); return pte; }
139 static inline pte_t pte_mkold(pte_t pte) {
140 pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
141 static inline pte_t pte_mkwrite(pte_t pte) {
142 pte_val(pte) &= ~_PAGE_RO;
143 pte_val(pte) |= _PAGE_RW; return pte; }
144 static inline pte_t pte_mkdirty(pte_t pte) {
145 pte_val(pte) |= _PAGE_DIRTY; return pte; }
146 static inline pte_t pte_mkyoung(pte_t pte) {
147 pte_val(pte) |= _PAGE_ACCESSED; return pte; }
148 static inline pte_t pte_mkspecial(pte_t pte) {
149 pte_val(pte) |= _PAGE_SPECIAL; return pte; }
150 static inline pte_t pte_mkhuge(pte_t pte) {
152 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
154 pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot);
159 /* Insert a PTE, top-level function is out of line. It uses an inline
160 * low level function in the respective pgtable-* files
162 extern void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
165 /* This low level function performs the actual PTE insertion
166 * Setting the PTE depends on the MMU type and other factors. It's
167 * an horrible mess that I'm not going to try to clean up now but
168 * I'm keeping it in one place rather than spread around
170 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
171 pte_t *ptep, pte_t pte, int percpu)
173 #if defined(CONFIG_PPC_STD_MMU_32) && defined(CONFIG_SMP) && !defined(CONFIG_PTE_64BIT)
174 /* First case is 32-bit Hash MMU in SMP mode with 32-bit PTEs. We use the
175 * helper pte_update() which does an atomic update. We need to do that
176 * because a concurrent invalidation can clear _PAGE_HASHPTE. If it's a
177 * per-CPU PTE such as a kmap_atomic, we do a simple update preserving
178 * the hash bits instead (ie, same as the non-SMP case)
181 *ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE)
182 | (pte_val(pte) & ~_PAGE_HASHPTE));
184 pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte));
186 #elif defined(CONFIG_PPC32) && defined(CONFIG_PTE_64BIT)
187 /* Second case is 32-bit with 64-bit PTE. In this case, we
188 * can just store as long as we do the two halves in the right order
189 * with a barrier in between. This is possible because we take care,
190 * in the hash code, to pre-invalidate if the PTE was already hashed,
191 * which synchronizes us with any concurrent invalidation.
192 * In the percpu case, we also fallback to the simple update preserving
196 *ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE)
197 | (pte_val(pte) & ~_PAGE_HASHPTE));
200 #if _PAGE_HASHPTE != 0
201 if (pte_val(*ptep) & _PAGE_HASHPTE)
202 flush_hash_entry(mm, ptep, addr);
204 __asm__ __volatile__("\
208 : "=m" (*ptep), "=m" (*((unsigned char *)ptep+4))
209 : "r" (pte) : "memory");
211 #elif defined(CONFIG_PPC_STD_MMU_32)
212 /* Third case is 32-bit hash table in UP mode, we need to preserve
213 * the _PAGE_HASHPTE bit since we may not have invalidated the previous
214 * translation in the hash yet (done in a subsequent flush_tlb_xxx())
215 * and see we need to keep track that this PTE needs invalidating
217 *ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE)
218 | (pte_val(pte) & ~_PAGE_HASHPTE));
221 /* Anything else just stores the PTE normally. That covers all 64-bit
222 * cases, and 32-bit non-hash with 32-bit PTEs.
229 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
230 extern int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address,
231 pte_t *ptep, pte_t entry, int dirty);
234 * Macro to mark a page protection value as "uncacheable".
237 #define _PAGE_CACHE_CTL (_PAGE_COHERENT | _PAGE_GUARDED | _PAGE_NO_CACHE | \
240 #define pgprot_noncached(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
241 _PAGE_NO_CACHE | _PAGE_GUARDED))
243 #define pgprot_noncached_wc(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
246 #define pgprot_cached(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
249 #define pgprot_cached_wthru(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
250 _PAGE_COHERENT | _PAGE_WRITETHRU))
252 #define pgprot_cached_noncoherent(prot) \
253 (__pgprot(pgprot_val(prot) & ~_PAGE_CACHE_CTL))
255 #define pgprot_writecombine pgprot_noncached_wc
258 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
259 unsigned long size, pgprot_t vma_prot);
260 #define __HAVE_PHYS_MEM_ACCESS_PROT
263 * ZERO_PAGE is a global shared page that is always zero: used
264 * for zero-mapped memory areas etc..
266 extern unsigned long empty_zero_page[];
267 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
269 extern pgd_t swapper_pg_dir[];
271 void limit_zone_pfn(enum zone_type zone, unsigned long max_pfn);
272 int dma_pfn_limit_to_zone(u64 pfn_limit);
273 extern void paging_init(void);
276 * kern_addr_valid is intended to indicate whether an address is a valid
277 * kernel address. Most 32-bit archs define it as always true (like this)
278 * but most 64-bit archs actually perform a test. What should we do here?
280 #define kern_addr_valid(addr) (1)
282 #include <asm-generic/pgtable.h>
286 * This gets called at the end of handling a page fault, when
287 * the kernel has put a new PTE into the page table for the process.
288 * We use it to ensure coherency between the i-cache and d-cache
289 * for the page which has just been mapped in.
290 * On machines which use an MMU hash table, we use this to put a
291 * corresponding HPTE into the hash table ahead of time, instead of
292 * waiting for the inevitable extra hash-table miss exception.
294 extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *);
296 extern int gup_hugepte(pte_t *ptep, unsigned long sz, unsigned long addr,
297 unsigned long end, int write,
298 struct page **pages, int *nr);
299 #ifndef CONFIG_TRANSPARENT_HUGEPAGE
300 #define pmd_large(pmd) 0
301 #define has_transparent_hugepage() 0
303 pte_t *find_linux_pte_or_hugepte(pgd_t *pgdir, unsigned long ea,
306 static inline pte_t *lookup_linux_ptep(pgd_t *pgdir, unsigned long hva,
307 unsigned long *pte_sizep)
310 unsigned long ps = *pte_sizep;
313 ptep = find_linux_pte_or_hugepte(pgdir, hva, &shift);
317 *pte_sizep = 1ul << shift;
319 *pte_sizep = PAGE_SIZE;
326 #endif /* __ASSEMBLY__ */
328 #endif /* __KERNEL__ */
329 #endif /* _ASM_POWERPC_PGTABLE_H */