1 #ifndef _ASM_POWERPC_PCI_BRIDGE_H
2 #define _ASM_POWERPC_PCI_BRIDGE_H
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
10 #include <linux/pci.h>
11 #include <linux/list.h>
12 #include <linux/ioport.h>
13 #include <asm-generic/pci-bridge.h>
15 /* Return values for pci_controller_ops.probe_mode function */
16 #define PCI_PROBE_NONE -1 /* Don't look at this bus at all */
17 #define PCI_PROBE_NORMAL 0 /* Do normal PCI probing */
18 #define PCI_PROBE_DEVTREE 1 /* Instantiate from device tree */
23 * PCI controller operations
25 struct pci_controller_ops {
26 void (*dma_dev_setup)(struct pci_dev *dev);
27 void (*dma_bus_setup)(struct pci_bus *bus);
29 int (*probe_mode)(struct pci_bus *);
31 /* Called when pci_enable_device() is called. Returns true to
32 * allow assignment/enabling of the device. */
33 bool (*enable_device_hook)(struct pci_dev *);
35 /* Called during PCI resource reassignment */
36 resource_size_t (*window_alignment)(struct pci_bus *, unsigned long type);
40 * Structure of a PCI controller (host bridge)
42 struct pci_controller {
48 struct device_node *dn;
49 struct list_head list_node;
50 struct device *parent;
57 void __iomem *io_base_virt;
61 resource_size_t io_base_phys;
62 resource_size_t pci_io_size;
64 /* Some machines have a special region to forward the ISA
65 * "memory" cycles such as VGA memory regions. Left to 0
68 resource_size_t isa_mem_phys;
69 resource_size_t isa_mem_size;
71 struct pci_controller_ops controller_ops;
73 unsigned int __iomem *cfg_addr;
74 void __iomem *cfg_data;
77 * Used for variants of PCI indirect handling and possible quirks:
78 * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
79 * EXT_REG - provides access to PCI-e extended registers
80 * SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS
81 * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
82 * to determine which bus number to match on when generating type0
84 * NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
85 * hanging if we don't have link and try to do config cycles to
86 * anything but the PHB. Only allow talking to the PHB if this is
88 * BIG_ENDIAN - cfg_addr is a big endian register
89 * BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
90 * the PLB4. Effectively disable MRM commands by setting this.
91 * FSL_CFG_REG_LINK - Freescale controller version in which the PCIe
92 * link status is in a RC PCIe cfg register (vs being a SoC register)
94 #define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001
95 #define PPC_INDIRECT_TYPE_EXT_REG 0x00000002
96 #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004
97 #define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008
98 #define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010
99 #define PPC_INDIRECT_TYPE_BROKEN_MRM 0x00000020
100 #define PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK 0x00000040
102 /* Currently, we limit ourselves to 1 IO range and 3 mem
103 * ranges since the common pci_bus structure can't handle more
105 struct resource io_resource;
106 struct resource mem_resources[3];
107 resource_size_t mem_offset[3];
108 int global_number; /* PCI domain number */
110 resource_size_t dma_window_base_cur;
111 resource_size_t dma_window_size;
115 struct pci_dn *pci_data;
116 #endif /* CONFIG_PPC64 */
121 /* These are used for config access before all the PCI probing
123 extern int early_read_config_byte(struct pci_controller *hose, int bus,
124 int dev_fn, int where, u8 *val);
125 extern int early_read_config_word(struct pci_controller *hose, int bus,
126 int dev_fn, int where, u16 *val);
127 extern int early_read_config_dword(struct pci_controller *hose, int bus,
128 int dev_fn, int where, u32 *val);
129 extern int early_write_config_byte(struct pci_controller *hose, int bus,
130 int dev_fn, int where, u8 val);
131 extern int early_write_config_word(struct pci_controller *hose, int bus,
132 int dev_fn, int where, u16 val);
133 extern int early_write_config_dword(struct pci_controller *hose, int bus,
134 int dev_fn, int where, u32 val);
136 extern int early_find_capability(struct pci_controller *hose, int bus,
137 int dev_fn, int cap);
139 extern void setup_indirect_pci(struct pci_controller* hose,
140 resource_size_t cfg_addr,
141 resource_size_t cfg_data, u32 flags);
143 extern int indirect_read_config(struct pci_bus *bus, unsigned int devfn,
144 int offset, int len, u32 *val);
146 extern int __indirect_read_config(struct pci_controller *hose,
147 unsigned char bus_number, unsigned int devfn,
148 int offset, int len, u32 *val);
150 extern int indirect_write_config(struct pci_bus *bus, unsigned int devfn,
151 int offset, int len, u32 val);
153 static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
160 extern int pci_device_from_OF_node(struct device_node *node,
162 extern void pci_create_OF_bus_map(void);
164 static inline int isa_vaddr_is_ioport(void __iomem *address)
166 /* No specific ISA handling on ppc32 at this stage, it
167 * all goes through PCI
172 #else /* CONFIG_PPC64 */
175 * PCI stuff, for nodes representing PCI devices, pointed to
176 * by device_node->data.
183 int busno; /* pci bus number */
184 int devfn; /* pci device and function number */
185 int vendor_id; /* Vendor ID */
186 int device_id; /* Device ID */
187 int class_code; /* Device class code */
189 struct pci_dn *parent;
190 struct pci_controller *phb; /* for pci devices */
191 struct iommu_table *iommu_table; /* for phb's or bridges */
192 struct device_node *node; /* back-pointer to the device_node */
194 int pci_ext_config_space; /* for pci devices */
196 struct pci_dev *pcidev; /* back-pointer to the pci device */
198 struct eeh_dev *edev; /* eeh device */
200 #define IODA_INVALID_PE (-1)
201 #ifdef CONFIG_PPC_POWERNV
204 struct list_head child_list;
205 struct list_head list;
208 /* Get the pointer to a device_node's pci_dn */
209 #define PCI_DN(dn) ((struct pci_dn *) (dn)->data)
211 extern struct pci_dn *pci_get_pdn_by_devfn(struct pci_bus *bus,
213 extern struct pci_dn *pci_get_pdn(struct pci_dev *pdev);
214 extern void *update_dn_pci_info(struct device_node *dn, void *data);
216 static inline int pci_device_from_OF_node(struct device_node *np,
221 *bus = PCI_DN(np)->busno;
222 *devfn = PCI_DN(np)->devfn;
226 #if defined(CONFIG_EEH)
227 static inline struct eeh_dev *pdn_to_eeh_dev(struct pci_dn *pdn)
229 return pdn ? pdn->edev : NULL;
232 #define pdn_to_eeh_dev(x) (NULL)
235 /** Find the bus corresponding to the indicated device node */
236 extern struct pci_bus *pcibios_find_pci_bus(struct device_node *dn);
238 /** Remove all of the PCI devices under this bus */
239 extern void pcibios_remove_pci_devices(struct pci_bus *bus);
241 /** Discover new pci devices under this bus, and add them */
242 extern void pcibios_add_pci_devices(struct pci_bus *bus);
245 extern void isa_bridge_find_early(struct pci_controller *hose);
247 static inline int isa_vaddr_is_ioport(void __iomem *address)
249 /* Check if address hits the reserved legacy IO range */
250 unsigned long ea = (unsigned long)address;
251 return ea >= ISA_IO_BASE && ea < ISA_IO_END;
254 extern int pcibios_unmap_io_space(struct pci_bus *bus);
255 extern int pcibios_map_io_space(struct pci_bus *bus);
258 #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE))
260 #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1)
263 #endif /* CONFIG_PPC64 */
265 /* Get the PCI host controller for an OF device */
266 extern struct pci_controller *pci_find_hose_for_OF_device(
267 struct device_node* node);
269 /* Fill up host controller resources from the OF node */
270 extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
271 struct device_node *dev, int primary);
273 /* Allocate & free a PCI host bridge structure */
274 extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
275 extern void pcibios_free_controller(struct pci_controller *phb);
278 extern int pcibios_vaddr_is_ioport(void __iomem *address);
280 static inline int pcibios_vaddr_is_ioport(void __iomem *address)
284 #endif /* CONFIG_PCI */
287 * Shims to prefer pci_controller version over ppc_md where available.
289 static inline void pci_dma_dev_setup(struct pci_dev *dev)
291 struct pci_controller *phb = pci_bus_to_host(dev->bus);
293 if (phb->controller_ops.dma_dev_setup)
294 phb->controller_ops.dma_dev_setup(dev);
295 else if (ppc_md.pci_dma_dev_setup)
296 ppc_md.pci_dma_dev_setup(dev);
299 static inline void pci_dma_bus_setup(struct pci_bus *bus)
301 struct pci_controller *phb = pci_bus_to_host(bus);
303 if (phb->controller_ops.dma_bus_setup)
304 phb->controller_ops.dma_bus_setup(bus);
305 else if (ppc_md.pci_dma_bus_setup)
306 ppc_md.pci_dma_bus_setup(bus);
309 static inline int pci_probe_mode(struct pci_bus *bus)
311 struct pci_controller *phb = pci_bus_to_host(bus);
313 if (phb->controller_ops.probe_mode)
314 return phb->controller_ops.probe_mode(bus);
315 if (ppc_md.pci_probe_mode)
316 return ppc_md.pci_probe_mode(bus);
317 return PCI_PROBE_NORMAL;
320 static inline bool pcibios_enable_device_hook(struct pci_dev *dev)
322 struct pci_controller *phb = pci_bus_to_host(dev->bus);
324 if (phb->controller_ops.enable_device_hook)
325 return phb->controller_ops.enable_device_hook(dev);
326 if (ppc_md.pcibios_enable_device_hook)
327 return ppc_md.pcibios_enable_device_hook(dev);
331 static inline resource_size_t pci_window_alignment(struct pci_bus *bus,
334 struct pci_controller *phb = pci_bus_to_host(bus);
336 if (phb->controller_ops.window_alignment)
337 return phb->controller_ops.window_alignment(bus, type);
338 if (ppc_md.pcibios_window_alignment)
339 return ppc_md.pcibios_window_alignment(bus, type);
342 * PCI core will figure out the default
343 * alignment: 4KiB for I/O and 1MiB for
349 #endif /* __KERNEL__ */
350 #endif /* _ASM_POWERPC_PCI_BRIDGE_H */