2 * OPAL API definitions.
4 * Copyright 2011-2015 IBM Corp.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
15 /****** OPAL APIs ******/
18 #define OPAL_SUCCESS 0
19 #define OPAL_PARAMETER -1
21 #define OPAL_PARTIAL -3
22 #define OPAL_CONSTRAINED -4
23 #define OPAL_CLOSED -5
24 #define OPAL_HARDWARE -6
25 #define OPAL_UNSUPPORTED -7
26 #define OPAL_PERMISSION -8
27 #define OPAL_NO_MEM -9
28 #define OPAL_RESOURCE -10
29 #define OPAL_INTERNAL_ERROR -11
30 #define OPAL_BUSY_EVENT -12
31 #define OPAL_HARDWARE_FROZEN -13
32 #define OPAL_WRONG_STATE -14
33 #define OPAL_ASYNC_COMPLETION -15
34 #define OPAL_EMPTY -16
35 #define OPAL_I2C_TIMEOUT -17
36 #define OPAL_I2C_INVALID_CMD -18
37 #define OPAL_I2C_LBUS_PARITY -19
38 #define OPAL_I2C_BKEND_OVERRUN -20
39 #define OPAL_I2C_BKEND_ACCESS -21
40 #define OPAL_I2C_ARBT_LOST -22
41 #define OPAL_I2C_NACK_RCVD -23
42 #define OPAL_I2C_STOP_ERR -24
43 #define OPAL_XIVE_PROVISIONING -31
44 #define OPAL_XIVE_FREE_ACTIVE -32
45 #define OPAL_TIMEOUT -33
47 /* API Tokens (in r0) */
48 #define OPAL_INVALID_CALL -1
50 #define OPAL_CONSOLE_WRITE 1
51 #define OPAL_CONSOLE_READ 2
52 #define OPAL_RTC_READ 3
53 #define OPAL_RTC_WRITE 4
54 #define OPAL_CEC_POWER_DOWN 5
55 #define OPAL_CEC_REBOOT 6
56 #define OPAL_READ_NVRAM 7
57 #define OPAL_WRITE_NVRAM 8
58 #define OPAL_HANDLE_INTERRUPT 9
59 #define OPAL_POLL_EVENTS 10
60 #define OPAL_PCI_SET_HUB_TCE_MEMORY 11
61 #define OPAL_PCI_SET_PHB_TCE_MEMORY 12
62 #define OPAL_PCI_CONFIG_READ_BYTE 13
63 #define OPAL_PCI_CONFIG_READ_HALF_WORD 14
64 #define OPAL_PCI_CONFIG_READ_WORD 15
65 #define OPAL_PCI_CONFIG_WRITE_BYTE 16
66 #define OPAL_PCI_CONFIG_WRITE_HALF_WORD 17
67 #define OPAL_PCI_CONFIG_WRITE_WORD 18
68 #define OPAL_SET_XIVE 19
69 #define OPAL_GET_XIVE 20
70 #define OPAL_GET_COMPLETION_TOKEN_STATUS 21 /* obsolete */
71 #define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER 22
72 #define OPAL_PCI_EEH_FREEZE_STATUS 23
73 #define OPAL_PCI_SHPC 24
74 #define OPAL_CONSOLE_WRITE_BUFFER_SPACE 25
75 #define OPAL_PCI_EEH_FREEZE_CLEAR 26
76 #define OPAL_PCI_PHB_MMIO_ENABLE 27
77 #define OPAL_PCI_SET_PHB_MEM_WINDOW 28
78 #define OPAL_PCI_MAP_PE_MMIO_WINDOW 29
79 #define OPAL_PCI_SET_PHB_TABLE_MEMORY 30
80 #define OPAL_PCI_SET_PE 31
81 #define OPAL_PCI_SET_PELTV 32
82 #define OPAL_PCI_SET_MVE 33
83 #define OPAL_PCI_SET_MVE_ENABLE 34
84 #define OPAL_PCI_GET_XIVE_REISSUE 35
85 #define OPAL_PCI_SET_XIVE_REISSUE 36
86 #define OPAL_PCI_SET_XIVE_PE 37
87 #define OPAL_GET_XIVE_SOURCE 38
88 #define OPAL_GET_MSI_32 39
89 #define OPAL_GET_MSI_64 40
90 #define OPAL_START_CPU 41
91 #define OPAL_QUERY_CPU_STATUS 42
92 #define OPAL_WRITE_OPPANEL 43 /* unimplemented */
93 #define OPAL_PCI_MAP_PE_DMA_WINDOW 44
94 #define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL 45
95 #define OPAL_PCI_RESET 49
96 #define OPAL_PCI_GET_HUB_DIAG_DATA 50
97 #define OPAL_PCI_GET_PHB_DIAG_DATA 51
98 #define OPAL_PCI_FENCE_PHB 52
99 #define OPAL_PCI_REINIT 53
100 #define OPAL_PCI_MASK_PE_ERROR 54
101 #define OPAL_SET_SLOT_LED_STATUS 55
102 #define OPAL_GET_EPOW_STATUS 56
103 #define OPAL_SET_SYSTEM_ATTENTION_LED 57
104 #define OPAL_RESERVED1 58
105 #define OPAL_RESERVED2 59
106 #define OPAL_PCI_NEXT_ERROR 60
107 #define OPAL_PCI_EEH_FREEZE_STATUS2 61
108 #define OPAL_PCI_POLL 62
109 #define OPAL_PCI_MSI_EOI 63
110 #define OPAL_PCI_GET_PHB_DIAG_DATA2 64
111 #define OPAL_XSCOM_READ 65
112 #define OPAL_XSCOM_WRITE 66
113 #define OPAL_LPC_READ 67
114 #define OPAL_LPC_WRITE 68
115 #define OPAL_RETURN_CPU 69
116 #define OPAL_REINIT_CPUS 70
117 #define OPAL_ELOG_READ 71
118 #define OPAL_ELOG_WRITE 72
119 #define OPAL_ELOG_ACK 73
120 #define OPAL_ELOG_RESEND 74
121 #define OPAL_ELOG_SIZE 75
122 #define OPAL_FLASH_VALIDATE 76
123 #define OPAL_FLASH_MANAGE 77
124 #define OPAL_FLASH_UPDATE 78
125 #define OPAL_RESYNC_TIMEBASE 79
126 #define OPAL_CHECK_TOKEN 80
127 #define OPAL_DUMP_INIT 81
128 #define OPAL_DUMP_INFO 82
129 #define OPAL_DUMP_READ 83
130 #define OPAL_DUMP_ACK 84
131 #define OPAL_GET_MSG 85
132 #define OPAL_CHECK_ASYNC_COMPLETION 86
133 #define OPAL_SYNC_HOST_REBOOT 87
134 #define OPAL_SENSOR_READ 88
135 #define OPAL_GET_PARAM 89
136 #define OPAL_SET_PARAM 90
137 #define OPAL_DUMP_RESEND 91
138 #define OPAL_ELOG_SEND 92 /* Deprecated */
139 #define OPAL_PCI_SET_PHB_CAPI_MODE 93
140 #define OPAL_DUMP_INFO2 94
141 #define OPAL_WRITE_OPPANEL_ASYNC 95
142 #define OPAL_PCI_ERR_INJECT 96
143 #define OPAL_PCI_EEH_FREEZE_SET 97
144 #define OPAL_HANDLE_HMI 98
145 #define OPAL_CONFIG_CPU_IDLE_STATE 99
146 #define OPAL_SLW_SET_REG 100
147 #define OPAL_REGISTER_DUMP_REGION 101
148 #define OPAL_UNREGISTER_DUMP_REGION 102
149 #define OPAL_WRITE_TPO 103
150 #define OPAL_READ_TPO 104
151 #define OPAL_GET_DPO_STATUS 105
152 #define OPAL_OLD_I2C_REQUEST 106 /* Deprecated */
153 #define OPAL_IPMI_SEND 107
154 #define OPAL_IPMI_RECV 108
155 #define OPAL_I2C_REQUEST 109
156 #define OPAL_FLASH_READ 110
157 #define OPAL_FLASH_WRITE 111
158 #define OPAL_FLASH_ERASE 112
159 #define OPAL_PRD_MSG 113
160 #define OPAL_LEDS_GET_INDICATOR 114
161 #define OPAL_LEDS_SET_INDICATOR 115
162 #define OPAL_CEC_REBOOT2 116
163 #define OPAL_CONSOLE_FLUSH 117
164 #define OPAL_GET_DEVICE_TREE 118
165 #define OPAL_PCI_GET_PRESENCE_STATE 119
166 #define OPAL_PCI_GET_POWER_STATE 120
167 #define OPAL_PCI_SET_POWER_STATE 121
168 #define OPAL_INT_GET_XIRR 122
169 #define OPAL_INT_SET_CPPR 123
170 #define OPAL_INT_EOI 124
171 #define OPAL_INT_SET_MFRR 125
172 #define OPAL_PCI_TCE_KILL 126
173 #define OPAL_NMMU_SET_PTCR 127
174 #define OPAL_XIVE_RESET 128
175 #define OPAL_XIVE_GET_IRQ_INFO 129
176 #define OPAL_XIVE_GET_IRQ_CONFIG 130
177 #define OPAL_XIVE_SET_IRQ_CONFIG 131
178 #define OPAL_XIVE_GET_QUEUE_INFO 132
179 #define OPAL_XIVE_SET_QUEUE_INFO 133
180 #define OPAL_XIVE_DONATE_PAGE 134
181 #define OPAL_XIVE_ALLOCATE_VP_BLOCK 135
182 #define OPAL_XIVE_FREE_VP_BLOCK 136
183 #define OPAL_XIVE_GET_VP_INFO 137
184 #define OPAL_XIVE_SET_VP_INFO 138
185 #define OPAL_XIVE_ALLOCATE_IRQ 139
186 #define OPAL_XIVE_FREE_IRQ 140
187 #define OPAL_XIVE_SYNC 141
188 #define OPAL_XIVE_DUMP 142
189 #define OPAL_XIVE_RESERVED3 143
190 #define OPAL_XIVE_RESERVED4 144
191 #define OPAL_NPU_INIT_CONTEXT 146
192 #define OPAL_NPU_DESTROY_CONTEXT 147
193 #define OPAL_NPU_MAP_LPAR 148
194 #define OPAL_IMC_COUNTERS_INIT 149
195 #define OPAL_IMC_COUNTERS_START 150
196 #define OPAL_IMC_COUNTERS_STOP 151
197 #define OPAL_GET_POWERCAP 152
198 #define OPAL_SET_POWERCAP 153
199 #define OPAL_GET_POWER_SHIFT_RATIO 154
200 #define OPAL_SET_POWER_SHIFT_RATIO 155
201 #define OPAL_SENSOR_GROUP_CLEAR 156
202 #define OPAL_PCI_SET_P2P 157
203 #define OPAL_LAST 157
205 /* Device tree flags */
208 * Flags set in power-mgmt nodes in device tree describing
209 * idle states that are supported in the platform.
212 #define OPAL_PM_TIMEBASE_STOP 0x00000002
213 #define OPAL_PM_LOSE_HYP_CONTEXT 0x00002000
214 #define OPAL_PM_LOSE_FULL_CONTEXT 0x00004000
215 #define OPAL_PM_NAP_ENABLED 0x00010000
216 #define OPAL_PM_SLEEP_ENABLED 0x00020000
217 #define OPAL_PM_WINKLE_ENABLED 0x00040000
218 #define OPAL_PM_SLEEP_ENABLED_ER1 0x00080000 /* with workaround */
219 #define OPAL_PM_STOP_INST_FAST 0x00100000
220 #define OPAL_PM_STOP_INST_DEEP 0x00200000
223 * OPAL_CONFIG_CPU_IDLE_STATE parameters
225 #define OPAL_CONFIG_IDLE_FASTSLEEP 1
226 #define OPAL_CONFIG_IDLE_UNDO 0
227 #define OPAL_CONFIG_IDLE_APPLY 1
232 enum OpalFreezeState {
233 OPAL_EEH_STOPPED_NOT_FROZEN = 0,
234 OPAL_EEH_STOPPED_MMIO_FREEZE = 1,
235 OPAL_EEH_STOPPED_DMA_FREEZE = 2,
236 OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3,
237 OPAL_EEH_STOPPED_RESET = 4,
238 OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,
239 OPAL_EEH_STOPPED_PERM_UNAVAIL = 6
242 enum OpalEehFreezeActionToken {
243 OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
244 OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
245 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3,
247 OPAL_EEH_ACTION_SET_FREEZE_MMIO = 1,
248 OPAL_EEH_ACTION_SET_FREEZE_DMA = 2,
249 OPAL_EEH_ACTION_SET_FREEZE_ALL = 3
252 enum OpalPciStatusToken {
253 OPAL_EEH_NO_ERROR = 0,
254 OPAL_EEH_IOC_ERROR = 1,
255 OPAL_EEH_PHB_ERROR = 2,
256 OPAL_EEH_PE_ERROR = 3,
257 OPAL_EEH_PE_MMIO_ERROR = 4,
258 OPAL_EEH_PE_DMA_ERROR = 5
261 enum OpalPciErrorSeverity {
262 OPAL_EEH_SEV_NO_ERROR = 0,
263 OPAL_EEH_SEV_IOC_DEAD = 1,
264 OPAL_EEH_SEV_PHB_DEAD = 2,
265 OPAL_EEH_SEV_PHB_FENCED = 3,
266 OPAL_EEH_SEV_PE_ER = 4,
270 enum OpalErrinjectType {
271 OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR = 0,
272 OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64 = 1,
275 enum OpalErrinjectFunc {
276 /* IOA bus specific errors */
277 OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR = 0,
278 OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_DATA = 1,
279 OPAL_ERR_INJECT_FUNC_IOA_LD_IO_ADDR = 2,
280 OPAL_ERR_INJECT_FUNC_IOA_LD_IO_DATA = 3,
281 OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_ADDR = 4,
282 OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_DATA = 5,
283 OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_ADDR = 6,
284 OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_DATA = 7,
285 OPAL_ERR_INJECT_FUNC_IOA_ST_IO_ADDR = 8,
286 OPAL_ERR_INJECT_FUNC_IOA_ST_IO_DATA = 9,
287 OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_ADDR = 10,
288 OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_DATA = 11,
289 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_ADDR = 12,
290 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_DATA = 13,
291 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_MASTER = 14,
292 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_TARGET = 15,
293 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_ADDR = 16,
294 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_DATA = 17,
295 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_MASTER = 18,
296 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET = 19,
299 enum OpalMmioWindowType {
300 OPAL_M32_WINDOW_TYPE = 1,
301 OPAL_M64_WINDOW_TYPE = 2,
302 OPAL_IO_WINDOW_TYPE = 3
305 enum OpalExceptionHandler {
306 OPAL_MACHINE_CHECK_HANDLER = 1,
307 OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,
308 OPAL_SOFTPATCH_HANDLER = 3
311 enum OpalPendingState {
312 OPAL_EVENT_OPAL_INTERNAL = 0x1,
313 OPAL_EVENT_NVRAM = 0x2,
314 OPAL_EVENT_RTC = 0x4,
315 OPAL_EVENT_CONSOLE_OUTPUT = 0x8,
316 OPAL_EVENT_CONSOLE_INPUT = 0x10,
317 OPAL_EVENT_ERROR_LOG_AVAIL = 0x20,
318 OPAL_EVENT_ERROR_LOG = 0x40,
319 OPAL_EVENT_EPOW = 0x80,
320 OPAL_EVENT_LED_STATUS = 0x100,
321 OPAL_EVENT_PCI_ERROR = 0x200,
322 OPAL_EVENT_DUMP_AVAIL = 0x400,
323 OPAL_EVENT_MSG_PENDING = 0x800,
326 enum OpalThreadStatus {
327 OPAL_THREAD_INACTIVE = 0x0,
328 OPAL_THREAD_STARTED = 0x1,
329 OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */
332 enum OpalPciBusCompare {
333 OpalPciBusAny = 0, /* Any bus number match */
334 OpalPciBus3Bits = 2, /* Match top 3 bits of bus number */
335 OpalPciBus4Bits = 3, /* Match top 4 bits of bus number */
336 OpalPciBus5Bits = 4, /* Match top 5 bits of bus number */
337 OpalPciBus6Bits = 5, /* Match top 6 bits of bus number */
338 OpalPciBus7Bits = 6, /* Match top 7 bits of bus number */
339 OpalPciBusAll = 7, /* Match bus number exactly */
342 enum OpalDeviceCompare {
343 OPAL_IGNORE_RID_DEVICE_NUMBER = 0,
344 OPAL_COMPARE_RID_DEVICE_NUMBER = 1
347 enum OpalFuncCompare {
348 OPAL_IGNORE_RID_FUNCTION_NUMBER = 0,
349 OPAL_COMPARE_RID_FUNCTION_NUMBER = 1
357 enum OpalPeltvAction {
358 OPAL_REMOVE_PE_FROM_DOMAIN = 0,
359 OPAL_ADD_PE_TO_DOMAIN = 1
362 enum OpalMveEnableAction {
363 OPAL_DISABLE_MVE = 0,
368 OPAL_DISABLE_M64 = 0,
369 OPAL_ENABLE_M64_SPLIT = 1,
370 OPAL_ENABLE_M64_NON_SPLIT = 2
373 enum OpalPciResetScope {
374 OPAL_RESET_PHB_COMPLETE = 1,
375 OPAL_RESET_PCI_LINK = 2,
376 OPAL_RESET_PHB_ERROR = 3,
377 OPAL_RESET_PCI_HOT = 4,
378 OPAL_RESET_PCI_FUNDAMENTAL = 5,
379 OPAL_RESET_PCI_IODA_TABLE = 6
382 enum OpalPciReinitScope {
384 * Note: we chose values that do not overlap
385 * OpalPciResetScope as OPAL v2 used the same
388 OPAL_REINIT_PCI_DEV = 1000
391 enum OpalPciResetState {
392 OPAL_DEASSERT_RESET = 0,
393 OPAL_ASSERT_RESET = 1
396 enum OpalPciSlotPresence {
397 OPAL_PCI_SLOT_EMPTY = 0,
398 OPAL_PCI_SLOT_PRESENT = 1
401 enum OpalPciSlotPower {
402 OPAL_PCI_SLOT_POWER_OFF = 0,
403 OPAL_PCI_SLOT_POWER_ON = 1,
404 OPAL_PCI_SLOT_OFFLINE = 2,
405 OPAL_PCI_SLOT_ONLINE = 3
408 enum OpalSlotLedType {
409 OPAL_SLOT_LED_TYPE_ID = 0, /* IDENTIFY LED */
410 OPAL_SLOT_LED_TYPE_FAULT = 1, /* FAULT LED */
411 OPAL_SLOT_LED_TYPE_ATTN = 2, /* System Attention LED */
412 OPAL_SLOT_LED_TYPE_MAX = 3
415 enum OpalSlotLedState {
416 OPAL_SLOT_LED_STATE_OFF = 0, /* LED is OFF */
417 OPAL_SLOT_LED_STATE_ON = 1 /* LED is ON */
421 * Address cycle types for LPC accesses. These also correspond
422 * to the content of the first cell of the "reg" property for
423 * device nodes on the LPC bus
425 enum OpalLPCAddressType {
432 OPAL_MSG_ASYNC_COMP = 0, /* params[0] = token, params[1] = rc,
433 * additional params function-specific
435 OPAL_MSG_MEM_ERR = 1,
437 OPAL_MSG_SHUTDOWN = 3, /* params[0] = 1 reboot, 0 shutdown */
438 OPAL_MSG_HMI_EVT = 4,
451 /* System parameter permission */
452 enum OpalSysparamPerm {
453 OPAL_SYSPARAM_READ = 0x1,
454 OPAL_SYSPARAM_WRITE = 0x2,
455 OPAL_SYSPARAM_RW = (OPAL_SYSPARAM_READ | OPAL_SYSPARAM_WRITE),
459 OPAL_IPMI_MSG_FORMAT_VERSION_1 = 1,
462 struct opal_ipmi_msg {
469 /* FSP memory errors handling */
470 enum OpalMemErr_Version {
474 enum OpalMemErrType {
475 OPAL_MEM_ERR_TYPE_RESILIENCE = 0,
476 OPAL_MEM_ERR_TYPE_DYN_DALLOC,
479 /* Memory Reilience error type */
480 enum OpalMemErr_ResilErrType {
481 OPAL_MEM_RESILIENCE_CE = 0,
482 OPAL_MEM_RESILIENCE_UE,
483 OPAL_MEM_RESILIENCE_UE_SCRUB,
486 /* Dynamic Memory Deallocation type */
487 enum OpalMemErr_DynErrType {
488 OPAL_MEM_DYNAMIC_DEALLOC = 0,
491 struct OpalMemoryErrorData {
492 enum OpalMemErr_Version version:8; /* 0x00 */
493 enum OpalMemErrType type:8; /* 0x01 */
494 __be16 flags; /* 0x02 */
495 uint8_t reserved_1[4]; /* 0x04 */
498 /* Memory Resilience corrected/uncorrected error info */
500 enum OpalMemErr_ResilErrType resil_err_type:8;
501 uint8_t reserved_1[7];
502 __be64 physical_address_start;
503 __be64 physical_address_end;
505 /* Dynamic memory deallocation error info */
507 enum OpalMemErr_DynErrType dyn_err_type:8;
508 uint8_t reserved_1[7];
509 __be64 physical_address_start;
510 __be64 physical_address_end;
515 /* HMI interrupt event */
516 enum OpalHMI_Version {
521 enum OpalHMI_Severity {
522 OpalHMI_SEV_NO_ERROR = 0,
523 OpalHMI_SEV_WARNING = 1,
524 OpalHMI_SEV_ERROR_SYNC = 2,
525 OpalHMI_SEV_FATAL = 3,
528 enum OpalHMI_Disposition {
529 OpalHMI_DISPOSITION_RECOVERED = 0,
530 OpalHMI_DISPOSITION_NOT_RECOVERED = 1,
533 enum OpalHMI_ErrType {
534 OpalHMI_ERROR_MALFUNC_ALERT = 0,
535 OpalHMI_ERROR_PROC_RECOV_DONE,
536 OpalHMI_ERROR_PROC_RECOV_DONE_AGAIN,
537 OpalHMI_ERROR_PROC_RECOV_MASKED,
539 OpalHMI_ERROR_TFMR_PARITY,
540 OpalHMI_ERROR_HA_OVERFLOW_WARN,
541 OpalHMI_ERROR_XSCOM_FAIL,
542 OpalHMI_ERROR_XSCOM_DONE,
543 OpalHMI_ERROR_SCOM_FIR,
544 OpalHMI_ERROR_DEBUG_TRIG_FIR,
545 OpalHMI_ERROR_HYP_RESOURCE,
546 OpalHMI_ERROR_CAPP_RECOVERY,
549 enum OpalHMI_XstopType {
550 CHECKSTOP_TYPE_UNKNOWN = 0,
551 CHECKSTOP_TYPE_CORE = 1,
552 CHECKSTOP_TYPE_NX = 2,
555 enum OpalHMI_CoreXstopReason {
556 CORE_CHECKSTOP_IFU_REGFILE = 0x00000001,
557 CORE_CHECKSTOP_IFU_LOGIC = 0x00000002,
558 CORE_CHECKSTOP_PC_DURING_RECOV = 0x00000004,
559 CORE_CHECKSTOP_ISU_REGFILE = 0x00000008,
560 CORE_CHECKSTOP_ISU_LOGIC = 0x00000010,
561 CORE_CHECKSTOP_FXU_LOGIC = 0x00000020,
562 CORE_CHECKSTOP_VSU_LOGIC = 0x00000040,
563 CORE_CHECKSTOP_PC_RECOV_IN_MAINT_MODE = 0x00000080,
564 CORE_CHECKSTOP_LSU_REGFILE = 0x00000100,
565 CORE_CHECKSTOP_PC_FWD_PROGRESS = 0x00000200,
566 CORE_CHECKSTOP_LSU_LOGIC = 0x00000400,
567 CORE_CHECKSTOP_PC_LOGIC = 0x00000800,
568 CORE_CHECKSTOP_PC_HYP_RESOURCE = 0x00001000,
569 CORE_CHECKSTOP_PC_HANG_RECOV_FAILED = 0x00002000,
570 CORE_CHECKSTOP_PC_AMBI_HANG_DETECTED = 0x00004000,
571 CORE_CHECKSTOP_PC_DEBUG_TRIG_ERR_INJ = 0x00008000,
572 CORE_CHECKSTOP_PC_SPRD_HYP_ERR_INJ = 0x00010000,
575 enum OpalHMI_NestAccelXstopReason {
576 NX_CHECKSTOP_SHM_INVAL_STATE_ERR = 0x00000001,
577 NX_CHECKSTOP_DMA_INVAL_STATE_ERR_1 = 0x00000002,
578 NX_CHECKSTOP_DMA_INVAL_STATE_ERR_2 = 0x00000004,
579 NX_CHECKSTOP_DMA_CH0_INVAL_STATE_ERR = 0x00000008,
580 NX_CHECKSTOP_DMA_CH1_INVAL_STATE_ERR = 0x00000010,
581 NX_CHECKSTOP_DMA_CH2_INVAL_STATE_ERR = 0x00000020,
582 NX_CHECKSTOP_DMA_CH3_INVAL_STATE_ERR = 0x00000040,
583 NX_CHECKSTOP_DMA_CH4_INVAL_STATE_ERR = 0x00000080,
584 NX_CHECKSTOP_DMA_CH5_INVAL_STATE_ERR = 0x00000100,
585 NX_CHECKSTOP_DMA_CH6_INVAL_STATE_ERR = 0x00000200,
586 NX_CHECKSTOP_DMA_CH7_INVAL_STATE_ERR = 0x00000400,
587 NX_CHECKSTOP_DMA_CRB_UE = 0x00000800,
588 NX_CHECKSTOP_DMA_CRB_SUE = 0x00001000,
589 NX_CHECKSTOP_PBI_ISN_UE = 0x00002000,
592 struct OpalHMIEvent {
593 uint8_t version; /* 0x00 */
594 uint8_t severity; /* 0x01 */
595 uint8_t type; /* 0x02 */
596 uint8_t disposition; /* 0x03 */
597 uint8_t reserved_1[4]; /* 0x04 */
600 /* TFMR register. Valid only for TFAC and TFMR_PARITY error type. */
603 /* version 2 and later */
606 * checkstop info (Core/NX).
607 * Valid for OpalHMI_ERROR_MALFUNC_ALERT.
610 uint8_t xstop_type; /* enum OpalHMI_XstopType */
611 uint8_t reserved_1[3];
614 __be32 pir; /* for CHECKSTOP_TYPE_CORE */
615 __be32 chip_id; /* for CHECKSTOP_TYPE_NX */
622 OPAL_P7IOC_DIAG_TYPE_NONE = 0,
623 OPAL_P7IOC_DIAG_TYPE_RGC = 1,
624 OPAL_P7IOC_DIAG_TYPE_BI = 2,
625 OPAL_P7IOC_DIAG_TYPE_CI = 3,
626 OPAL_P7IOC_DIAG_TYPE_MISC = 4,
627 OPAL_P7IOC_DIAG_TYPE_I2C = 5,
628 OPAL_P7IOC_DIAG_TYPE_LAST = 6
631 struct OpalIoP7IOCErrorData {
649 struct OpalIoP7IOCRgcErrorData {
650 __be64 rgcStatus; /* 3E1C10 */
651 __be64 rgcLdcp; /* 3E1C18 */
653 struct OpalIoP7IOCBiErrorData {
654 __be64 biLdcp0; /* 3C0100, 3C0118 */
655 __be64 biLdcp1; /* 3C0108, 3C0120 */
656 __be64 biLdcp2; /* 3C0110, 3C0128 */
657 __be64 biFenceStatus; /* 3C0130, 3C0130 */
659 uint8_t biDownbound; /* BI Downbound or Upbound */
661 struct OpalIoP7IOCCiErrorData {
662 __be64 ciPortStatus; /* 3Dn008 */
663 __be64 ciPortLdcp; /* 3Dn010 */
665 uint8_t ciPort; /* Index of CI port: 0/1 */
671 * This structure defines the overlay which will be used to store PHB error
675 OPAL_PHB_ERROR_DATA_VERSION_1 = 1,
679 OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1,
680 OPAL_PHB_ERROR_DATA_TYPE_PHB3 = 2,
681 OPAL_PHB_ERROR_DATA_TYPE_PHB4 = 3
685 OPAL_P7IOC_NUM_PEST_REGS = 128,
686 OPAL_PHB3_NUM_PEST_REGS = 256,
687 OPAL_PHB4_NUM_PEST_REGS = 512
690 struct OpalIoPhbErrorCommon {
696 struct OpalIoP7IOCPhbErrorData {
697 struct OpalIoPhbErrorCommon common;
702 __be32 portStatusReg;
703 __be32 rootCmplxStatus;
704 __be32 busAgentStatus;
714 __be32 rootErrorStatus;
715 __be32 uncorrErrorStatus;
716 __be32 corrErrorStatus;
725 // Record data about the call to allocate a buffer.
729 //P7IOC MMIO Error Regs
730 __be64 p7iocPlssr; // n120
731 __be64 p7iocCsr; // n110
732 __be64 lemFir; // nC00
733 __be64 lemErrorMask; // nC18
734 __be64 lemWOF; // nC40
735 __be64 phbErrorStatus; // nC80
736 __be64 phbFirstErrorStatus; // nC88
737 __be64 phbErrorLog0; // nCC0
738 __be64 phbErrorLog1; // nCC8
739 __be64 mmioErrorStatus; // nD00
740 __be64 mmioFirstErrorStatus; // nD08
741 __be64 mmioErrorLog0; // nD40
742 __be64 mmioErrorLog1; // nD48
743 __be64 dma0ErrorStatus; // nD80
744 __be64 dma0FirstErrorStatus; // nD88
745 __be64 dma0ErrorLog0; // nDC0
746 __be64 dma0ErrorLog1; // nDC8
747 __be64 dma1ErrorStatus; // nE00
748 __be64 dma1FirstErrorStatus; // nE08
749 __be64 dma1ErrorLog0; // nE40
750 __be64 dma1ErrorLog1; // nE48
751 __be64 pestA[OPAL_P7IOC_NUM_PEST_REGS];
752 __be64 pestB[OPAL_P7IOC_NUM_PEST_REGS];
755 struct OpalIoPhb3ErrorData {
756 struct OpalIoPhbErrorCommon common;
761 __be32 portStatusReg;
762 __be32 rootCmplxStatus;
763 __be32 busAgentStatus;
773 __be32 rootErrorStatus;
774 __be32 uncorrErrorStatus;
775 __be32 corrErrorStatus;
784 /* Record data about the call to allocate a buffer */
788 /* PHB3 MMIO Error Regs */
789 __be64 nFir; /* 000 */
790 __be64 nFirMask; /* 003 */
791 __be64 nFirWOF; /* 008 */
792 __be64 phbPlssr; /* 120 */
793 __be64 phbCsr; /* 110 */
794 __be64 lemFir; /* C00 */
795 __be64 lemErrorMask; /* C18 */
796 __be64 lemWOF; /* C40 */
797 __be64 phbErrorStatus; /* C80 */
798 __be64 phbFirstErrorStatus; /* C88 */
799 __be64 phbErrorLog0; /* CC0 */
800 __be64 phbErrorLog1; /* CC8 */
801 __be64 mmioErrorStatus; /* D00 */
802 __be64 mmioFirstErrorStatus; /* D08 */
803 __be64 mmioErrorLog0; /* D40 */
804 __be64 mmioErrorLog1; /* D48 */
805 __be64 dma0ErrorStatus; /* D80 */
806 __be64 dma0FirstErrorStatus; /* D88 */
807 __be64 dma0ErrorLog0; /* DC0 */
808 __be64 dma0ErrorLog1; /* DC8 */
809 __be64 dma1ErrorStatus; /* E00 */
810 __be64 dma1FirstErrorStatus; /* E08 */
811 __be64 dma1ErrorLog0; /* E40 */
812 __be64 dma1ErrorLog1; /* E48 */
813 __be64 pestA[OPAL_PHB3_NUM_PEST_REGS];
814 __be64 pestB[OPAL_PHB3_NUM_PEST_REGS];
817 struct OpalIoPhb4ErrorData {
818 struct OpalIoPhbErrorCommon common;
830 __be32 rootErrorStatus;
831 __be32 uncorrErrorStatus;
832 __be32 corrErrorStatus;
839 /* PHB4 ETU Error Regs */
840 __be64 nFir; /* 000 */
841 __be64 nFirMask; /* 003 */
842 __be64 nFirWOF; /* 008 */
843 __be64 phbPlssr; /* 120 */
844 __be64 phbCsr; /* 110 */
845 __be64 lemFir; /* C00 */
846 __be64 lemErrorMask; /* C18 */
847 __be64 lemWOF; /* C40 */
848 __be64 phbErrorStatus; /* C80 */
849 __be64 phbFirstErrorStatus; /* C88 */
850 __be64 phbErrorLog0; /* CC0 */
851 __be64 phbErrorLog1; /* CC8 */
852 __be64 phbTxeErrorStatus; /* D00 */
853 __be64 phbTxeFirstErrorStatus; /* D08 */
854 __be64 phbTxeErrorLog0; /* D40 */
855 __be64 phbTxeErrorLog1; /* D48 */
856 __be64 phbRxeArbErrorStatus; /* D80 */
857 __be64 phbRxeArbFirstErrorStatus; /* D88 */
858 __be64 phbRxeArbErrorLog0; /* DC0 */
859 __be64 phbRxeArbErrorLog1; /* DC8 */
860 __be64 phbRxeMrgErrorStatus; /* E00 */
861 __be64 phbRxeMrgFirstErrorStatus; /* E08 */
862 __be64 phbRxeMrgErrorLog0; /* E40 */
863 __be64 phbRxeMrgErrorLog1; /* E48 */
864 __be64 phbRxeTceErrorStatus; /* E80 */
865 __be64 phbRxeTceFirstErrorStatus; /* E88 */
866 __be64 phbRxeTceErrorLog0; /* EC0 */
867 __be64 phbRxeTceErrorLog1; /* EC8 */
869 /* PHB4 REGB Error Regs */
870 __be64 phbPblErrorStatus; /* 1900 */
871 __be64 phbPblFirstErrorStatus; /* 1908 */
872 __be64 phbPblErrorLog0; /* 1940 */
873 __be64 phbPblErrorLog1; /* 1948 */
874 __be64 phbPcieDlpErrorLog1; /* 1AA0 */
875 __be64 phbPcieDlpErrorLog2; /* 1AA8 */
876 __be64 phbPcieDlpErrorStatus; /* 1AB0 */
877 __be64 phbRegbErrorStatus; /* 1C00 */
878 __be64 phbRegbFirstErrorStatus; /* 1C08 */
879 __be64 phbRegbErrorLog0; /* 1C40 */
880 __be64 phbRegbErrorLog1; /* 1C48 */
882 __be64 pestA[OPAL_PHB4_NUM_PEST_REGS];
883 __be64 pestB[OPAL_PHB4_NUM_PEST_REGS];
887 OPAL_REINIT_CPUS_HILE_BE = (1 << 0),
888 OPAL_REINIT_CPUS_HILE_LE = (1 << 1),
890 /* These two define the base MMU mode of the host on P9
892 * On P9 Nimbus DD2.0 and Cumlus (and later), KVM can still
893 * create hash guests in "radix" mode with care (full core
896 OPAL_REINIT_CPUS_MMU_HASH = (1 << 2),
897 OPAL_REINIT_CPUS_MMU_RADIX = (1 << 3),
900 typedef struct oppanel_line {
905 enum opal_prd_msg_type {
906 OPAL_PRD_MSG_TYPE_INIT = 0, /* HBRT --> OPAL */
907 OPAL_PRD_MSG_TYPE_FINI, /* HBRT/kernel --> OPAL */
908 OPAL_PRD_MSG_TYPE_ATTN, /* HBRT <-- OPAL */
909 OPAL_PRD_MSG_TYPE_ATTN_ACK, /* HBRT --> OPAL */
910 OPAL_PRD_MSG_TYPE_OCC_ERROR, /* HBRT <-- OPAL */
911 OPAL_PRD_MSG_TYPE_OCC_RESET, /* HBRT <-- OPAL */
914 struct opal_prd_msg_header {
924 #define OCC_THROTTLE 2
925 #define OCC_MAX_THROTTLE_STATUS 5
927 struct opal_occ_msg {
930 __be64 throttle_status;
936 * WARNING: The current implementation requires each entry
937 * to represent a block that is 4k aligned *and* each block
938 * size except the last one in the list to be as well.
940 struct opal_sg_entry {
946 * Candidate image SG list.
948 * length = VER | length
950 struct opal_sg_list {
953 struct opal_sg_entry entry[];
957 * Dump region ID range usable by the OS
959 #define OPAL_DUMP_REGION_HOST_START 0x80
960 #define OPAL_DUMP_REGION_LOG_BUF 0x80
961 #define OPAL_DUMP_REGION_HOST_END 0xFF
963 /* CAPI modes for PHB */
965 OPAL_PHB_CAPI_MODE_PCIE = 0,
966 OPAL_PHB_CAPI_MODE_CAPI = 1,
967 OPAL_PHB_CAPI_MODE_SNOOP_OFF = 2,
968 OPAL_PHB_CAPI_MODE_SNOOP_ON = 3,
969 OPAL_PHB_CAPI_MODE_DMA = 4,
970 OPAL_PHB_CAPI_MODE_DMA_TVT1 = 5,
973 /* OPAL I2C request */
974 struct opal_i2c_request {
976 #define OPAL_I2C_RAW_READ 0
977 #define OPAL_I2C_RAW_WRITE 1
978 #define OPAL_I2C_SM_READ 2
979 #define OPAL_I2C_SM_WRITE 3
981 #define OPAL_I2C_ADDR_10 0x01 /* Not supported yet */
982 uint8_t subaddr_sz; /* Max 4 */
984 __be16 addr; /* 7 or 10 bit address */
986 __be32 subaddr; /* Sub-address if any */
987 __be32 size; /* Data size */
988 __be64 buffer_ra; /* Buffer real address */
992 * EPOW status sharing (OPAL and the host)
994 * The host will pass on OPAL, a buffer of length OPAL_SYSEPOW_MAX
995 * with individual elements being 16 bits wide to fetch the system
996 * wide EPOW status. Each element in the buffer will contain the
997 * EPOW status in it's bit representation for a particular EPOW sub
998 * class as defined here. So multiple detailed EPOW status bits
999 * specific for any sub class can be represented in a single buffer
1000 * element as it's bit representation.
1003 /* System EPOW type */
1005 OPAL_SYSEPOW_POWER = 0, /* Power EPOW */
1006 OPAL_SYSEPOW_TEMP = 1, /* Temperature EPOW */
1007 OPAL_SYSEPOW_COOLING = 2, /* Cooling EPOW */
1008 OPAL_SYSEPOW_MAX = 3, /* Max EPOW categories */
1013 OPAL_SYSPOWER_UPS = 0x0001, /* System on UPS power */
1014 OPAL_SYSPOWER_CHNG = 0x0002, /* System power config change */
1015 OPAL_SYSPOWER_FAIL = 0x0004, /* System impending power failure */
1016 OPAL_SYSPOWER_INCL = 0x0008, /* System incomplete power */
1019 /* Temperature EPOW */
1021 OPAL_SYSTEMP_AMB = 0x0001, /* System over ambient temperature */
1022 OPAL_SYSTEMP_INT = 0x0002, /* System over internal temperature */
1023 OPAL_SYSTEMP_HMD = 0x0004, /* System over ambient humidity */
1027 enum OpalSysCooling {
1028 OPAL_SYSCOOL_INSF = 0x0001, /* System insufficient cooling */
1031 /* Argument to OPAL_CEC_REBOOT2() */
1033 OPAL_REBOOT_NORMAL = 0,
1034 OPAL_REBOOT_PLATFORM_ERROR = 1,
1037 /* Argument to OPAL_PCI_TCE_KILL */
1039 OPAL_PCI_TCE_KILL_PAGES,
1040 OPAL_PCI_TCE_KILL_PE,
1041 OPAL_PCI_TCE_KILL_ALL,
1044 /* The xive operation mode indicates the active "API" and
1045 * corresponds to the "mode" parameter of the opal_xive_reset()
1049 OPAL_XIVE_MODE_EMU = 0,
1050 OPAL_XIVE_MODE_EXPL = 1,
1053 /* Flags for OPAL_XIVE_GET_IRQ_INFO */
1055 OPAL_XIVE_IRQ_TRIGGER_PAGE = 0x00000001,
1056 OPAL_XIVE_IRQ_STORE_EOI = 0x00000002,
1057 OPAL_XIVE_IRQ_LSI = 0x00000004,
1058 OPAL_XIVE_IRQ_SHIFT_BUG = 0x00000008,
1059 OPAL_XIVE_IRQ_MASK_VIA_FW = 0x00000010,
1060 OPAL_XIVE_IRQ_EOI_VIA_FW = 0x00000020,
1063 /* Flags for OPAL_XIVE_GET/SET_QUEUE_INFO */
1065 OPAL_XIVE_EQ_ENABLED = 0x00000001,
1066 OPAL_XIVE_EQ_ALWAYS_NOTIFY = 0x00000002,
1067 OPAL_XIVE_EQ_ESCALATE = 0x00000004,
1070 /* Flags for OPAL_XIVE_GET/SET_VP_INFO */
1072 OPAL_XIVE_VP_ENABLED = 0x00000001,
1075 /* "Any chip" replacement for chip ID for allocation functions */
1077 OPAL_XIVE_ANY_CHIP = 0xffffffff,
1080 /* Xive sync options */
1082 /* This bits are cumulative, arg is a girq */
1083 XIVE_SYNC_EAS = 0x00000001, /* Sync irq source */
1084 XIVE_SYNC_QUEUE = 0x00000002, /* Sync irq target */
1089 XIVE_DUMP_TM_HYP = 0,
1090 XIVE_DUMP_TM_POOL = 1,
1091 XIVE_DUMP_TM_OS = 2,
1092 XIVE_DUMP_TM_USER = 3,
1094 XIVE_DUMP_EMU_STATE = 5,
1097 /* "type" argument options for OPAL_IMC_COUNTERS_* calls */
1099 OPAL_IMC_COUNTERS_NEST = 1,
1100 OPAL_IMC_COUNTERS_CORE = 2,
1104 /* PCI p2p descriptor */
1105 #define OPAL_PCI_P2P_ENABLE 0x1
1106 #define OPAL_PCI_P2P_LOAD 0x2
1107 #define OPAL_PCI_P2P_STORE 0x4
1109 #endif /* __ASSEMBLY__ */
1111 #endif /* __OPAL_API_H */