1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_POWERPC_NOHASH_64_PGTABLE_64K_H
3 #define _ASM_POWERPC_NOHASH_64_PGTABLE_64K_H
5 #define __ARCH_USE_5LEVEL_HACK
6 #include <asm-generic/pgtable-nopud.h>
9 #define PTE_INDEX_SIZE 8
10 #define PMD_INDEX_SIZE 10
11 #define PUD_INDEX_SIZE 0
12 #define PGD_INDEX_SIZE 12
15 * we support 32 fragments per PTE page of 64K size
17 #define PTE_FRAG_NR 32
19 * We use a 2K PTE page fragment and another 2K for storing
20 * real_pte_t hash index
22 #define PTE_FRAG_SIZE_SHIFT 11
23 #define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT)
26 #define PTE_TABLE_SIZE PTE_FRAG_SIZE
27 #define PMD_TABLE_SIZE (sizeof(pmd_t) << PMD_INDEX_SIZE)
28 #define PUD_TABLE_SIZE (0)
29 #define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE)
30 #endif /* __ASSEMBLY__ */
32 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
33 #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE)
34 #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
36 /* PMD_SHIFT determines what a second-level page table entry can map */
37 #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
38 #define PMD_SIZE (1UL << PMD_SHIFT)
39 #define PMD_MASK (~(PMD_SIZE-1))
41 /* PGDIR_SHIFT determines what a third-level page table entry can map */
42 #define PGDIR_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE)
43 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
44 #define PGDIR_MASK (~(PGDIR_SIZE-1))
47 * Bits to mask out from a PMD to get to the PTE page
48 * PMDs point to PTE table fragments which are PTE_FRAG_SIZE aligned.
50 #define PMD_MASKED_BITS (PTE_FRAG_SIZE - 1)
51 /* Bits to mask out from a PGD/PUD to get to the PMD page */
52 #define PUD_MASKED_BITS 0x1ff
54 #define pgd_pte(pgd) (pud_pte(((pud_t){ pgd })))
55 #define pte_pgd(pte) ((pgd_t)pte_pud(pte))
57 #endif /* _ASM_POWERPC_NOHASH_64_PGTABLE_64K_H */