1 #ifndef _ASM_POWERPC_IO_H
2 #define _ASM_POWERPC_IO_H
5 #define ARCH_HAS_IOREMAP_WC
7 #define ARCH_HAS_IOREMAP_WT
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
17 /* Check of existence of legacy devices */
18 extern int check_legacy_ioport(unsigned long base_port);
19 #define I8042_DATA_REG 0x60
20 #define FDC_BASE 0x3f0
22 #if defined(CONFIG_PPC64) && defined(CONFIG_PCI)
23 extern struct pci_dev *isa_bridge_pcidev;
25 * has legacy ISA devices ?
27 #define arch_has_dev_port() (isa_bridge_pcidev != NULL || isa_io_special)
30 #include <linux/device.h>
31 #include <linux/compiler.h>
34 #include <asm/byteorder.h>
35 #include <asm/synch.h>
36 #include <asm/delay.h>
37 #include <asm/mmiowb.h>
39 #include <asm/ppc_asm.h>
40 #include <asm/pgtable.h>
42 #define SIO_CONFIG_RA 0x398
43 #define SIO_CONFIG_RD 0x399
47 /* 32 bits uses slightly different variables for the various IO
48 * bases. Most of this file only uses _IO_BASE though which we
49 * define properly based on the platform
53 #define _ISA_MEM_BASE 0
54 #define PCI_DRAM_OFFSET 0
55 #elif defined(CONFIG_PPC32)
56 #define _IO_BASE isa_io_base
57 #define _ISA_MEM_BASE isa_mem_base
58 #define PCI_DRAM_OFFSET pci_dram_offset
60 #define _IO_BASE pci_io_base
61 #define _ISA_MEM_BASE isa_mem_base
62 #define PCI_DRAM_OFFSET 0
65 extern unsigned long isa_io_base;
66 extern unsigned long pci_io_base;
67 extern unsigned long pci_dram_offset;
69 extern resource_size_t isa_mem_base;
71 /* Boolean set by platform if PIO accesses are suppored while _IO_BASE
72 * is not set or addresses cannot be translated to MMIO. This is typically
73 * set when the platform supports "special" PIO accesses via a non memory
74 * mapped mechanism, and allows things like the early udbg UART code to
77 extern bool isa_io_special;
80 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
81 #error CONFIG_PPC_INDIRECT_{PIO,MMIO} are not yet supported on 32 bits
87 * Low level MMIO accessors
89 * This provides the non-bus specific accessors to MMIO. Those are PowerPC
90 * specific and thus shouldn't be used in generic code. The accessors
93 * in_8, in_le16, in_be16, in_le32, in_be32, in_le64, in_be64
94 * out_8, out_le16, out_be16, out_le32, out_be32, out_le64, out_be64
95 * _insb, _insw_ns, _insl_ns, _outsb, _outsw_ns, _outsl_ns
97 * Those operate directly on a kernel virtual address. Note that the prototype
98 * for the out_* accessors has the arguments in opposite order from the usual
99 * linux PCI accessors. Unlike those, they take the address first and the value
102 * Note: I might drop the _ns suffix on the stream operations soon as it is
103 * simply normal for stream operations to not swap in the first place.
107 #define DEF_MMIO_IN_X(name, size, insn) \
108 static inline u##size name(const volatile u##size __iomem *addr) \
111 __asm__ __volatile__("sync;"#insn" %0,%y1;twi 0,%0,0;isync" \
112 : "=r" (ret) : "Z" (*addr) : "memory"); \
116 #define DEF_MMIO_OUT_X(name, size, insn) \
117 static inline void name(volatile u##size __iomem *addr, u##size val) \
119 __asm__ __volatile__("sync;"#insn" %1,%y0" \
120 : "=Z" (*addr) : "r" (val) : "memory"); \
121 mmiowb_set_pending(); \
124 #define DEF_MMIO_IN_D(name, size, insn) \
125 static inline u##size name(const volatile u##size __iomem *addr) \
128 __asm__ __volatile__("sync;"#insn"%U1%X1 %0,%1;twi 0,%0,0;isync"\
129 : "=r" (ret) : "m" (*addr) : "memory"); \
133 #define DEF_MMIO_OUT_D(name, size, insn) \
134 static inline void name(volatile u##size __iomem *addr, u##size val) \
136 __asm__ __volatile__("sync;"#insn"%U0%X0 %1,%0" \
137 : "=m" (*addr) : "r" (val) : "memory"); \
138 mmiowb_set_pending(); \
141 DEF_MMIO_IN_D(in_8, 8, lbz);
142 DEF_MMIO_OUT_D(out_8, 8, stb);
144 #ifdef __BIG_ENDIAN__
145 DEF_MMIO_IN_D(in_be16, 16, lhz);
146 DEF_MMIO_IN_D(in_be32, 32, lwz);
147 DEF_MMIO_IN_X(in_le16, 16, lhbrx);
148 DEF_MMIO_IN_X(in_le32, 32, lwbrx);
150 DEF_MMIO_OUT_D(out_be16, 16, sth);
151 DEF_MMIO_OUT_D(out_be32, 32, stw);
152 DEF_MMIO_OUT_X(out_le16, 16, sthbrx);
153 DEF_MMIO_OUT_X(out_le32, 32, stwbrx);
155 DEF_MMIO_IN_X(in_be16, 16, lhbrx);
156 DEF_MMIO_IN_X(in_be32, 32, lwbrx);
157 DEF_MMIO_IN_D(in_le16, 16, lhz);
158 DEF_MMIO_IN_D(in_le32, 32, lwz);
160 DEF_MMIO_OUT_X(out_be16, 16, sthbrx);
161 DEF_MMIO_OUT_X(out_be32, 32, stwbrx);
162 DEF_MMIO_OUT_D(out_le16, 16, sth);
163 DEF_MMIO_OUT_D(out_le32, 32, stw);
165 #endif /* __BIG_ENDIAN */
169 #ifdef __BIG_ENDIAN__
170 DEF_MMIO_OUT_D(out_be64, 64, std);
171 DEF_MMIO_IN_D(in_be64, 64, ld);
173 /* There is no asm instructions for 64 bits reverse loads and stores */
174 static inline u64 in_le64(const volatile u64 __iomem *addr)
176 return swab64(in_be64(addr));
179 static inline void out_le64(volatile u64 __iomem *addr, u64 val)
181 out_be64(addr, swab64(val));
184 DEF_MMIO_OUT_D(out_le64, 64, std);
185 DEF_MMIO_IN_D(in_le64, 64, ld);
187 /* There is no asm instructions for 64 bits reverse loads and stores */
188 static inline u64 in_be64(const volatile u64 __iomem *addr)
190 return swab64(in_le64(addr));
193 static inline void out_be64(volatile u64 __iomem *addr, u64 val)
195 out_le64(addr, swab64(val));
199 #endif /* __powerpc64__ */
202 * Low level IO stream instructions are defined out of line for now
204 extern void _insb(const volatile u8 __iomem *addr, void *buf, long count);
205 extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count);
206 extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count);
207 extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count);
208 extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count);
209 extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count);
211 /* The _ns naming is historical and will be removed. For now, just #define
212 * the non _ns equivalent names
214 #define _insw _insw_ns
215 #define _insl _insl_ns
216 #define _outsw _outsw_ns
217 #define _outsl _outsl_ns
221 * memset_io, memcpy_toio, memcpy_fromio base implementations are out of line
224 extern void _memset_io(volatile void __iomem *addr, int c, unsigned long n);
225 extern void _memcpy_fromio(void *dest, const volatile void __iomem *src,
227 extern void _memcpy_toio(volatile void __iomem *dest, const void *src,
232 * PCI and standard ISA accessors
234 * Those are globally defined linux accessors for devices on PCI or ISA
235 * busses. They follow the Linux defined semantics. The current implementation
236 * for PowerPC is as close as possible to the x86 version of these, and thus
237 * provides fairly heavy weight barriers for the non-raw versions
239 * In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_MMIO
240 * or CONFIG_PPC_INDIRECT_PIO are set allowing the platform to provide its
241 * own implementation of some or all of the accessors.
245 * Include the EEH definitions when EEH is enabled only so they don't get
246 * in the way when building for 32 bits
252 /* Shortcut to the MMIO argument pointer */
253 #define PCI_IO_ADDR volatile void __iomem *
255 /* Indirect IO address tokens:
257 * When CONFIG_PPC_INDIRECT_MMIO is set, the platform can provide hooks
258 * on all MMIOs. (Note that this is all 64 bits only for now)
260 * To help platforms who may need to differentiate MMIO addresses in
261 * their hooks, a bitfield is reserved for use by the platform near the
262 * top of MMIO addresses (not PIO, those have to cope the hard way).
264 * The highest address in the kernel virtual space are:
266 * d0003fffffffffff # with Hash MMU
267 * c00fffffffffffff # with Radix MMU
269 * The top 4 bits are reserved as the region ID on hash, leaving us 8 bits
270 * that can be used for the field.
272 * The direct IO mapping operations will then mask off those bits
273 * before doing the actual access, though that only happen when
274 * CONFIG_PPC_INDIRECT_MMIO is set, thus be careful when you use that
277 * For PIO, there is a separate CONFIG_PPC_INDIRECT_PIO which makes
278 * all PIO functions call through a hook.
281 #ifdef CONFIG_PPC_INDIRECT_MMIO
282 #define PCI_IO_IND_TOKEN_SHIFT 52
283 #define PCI_IO_IND_TOKEN_MASK (0xfful << PCI_IO_IND_TOKEN_SHIFT)
284 #define PCI_FIX_ADDR(addr) \
285 ((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK))
286 #define PCI_GET_ADDR_TOKEN(addr) \
287 (((unsigned long)(addr) & PCI_IO_IND_TOKEN_MASK) >> \
288 PCI_IO_IND_TOKEN_SHIFT)
289 #define PCI_SET_ADDR_TOKEN(addr, token) \
291 unsigned long __a = (unsigned long)(addr); \
292 __a &= ~PCI_IO_IND_TOKEN_MASK; \
293 __a |= ((unsigned long)(token)) << PCI_IO_IND_TOKEN_SHIFT; \
294 (addr) = (void __iomem *)__a; \
297 #define PCI_FIX_ADDR(addr) (addr)
302 * Non ordered and non-swapping "raw" accessors
305 static inline unsigned char __raw_readb(const volatile void __iomem *addr)
307 return *(volatile unsigned char __force *)PCI_FIX_ADDR(addr);
309 static inline unsigned short __raw_readw(const volatile void __iomem *addr)
311 return *(volatile unsigned short __force *)PCI_FIX_ADDR(addr);
313 static inline unsigned int __raw_readl(const volatile void __iomem *addr)
315 return *(volatile unsigned int __force *)PCI_FIX_ADDR(addr);
317 static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
319 *(volatile unsigned char __force *)PCI_FIX_ADDR(addr) = v;
321 static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
323 *(volatile unsigned short __force *)PCI_FIX_ADDR(addr) = v;
325 static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
327 *(volatile unsigned int __force *)PCI_FIX_ADDR(addr) = v;
331 static inline unsigned long __raw_readq(const volatile void __iomem *addr)
333 return *(volatile unsigned long __force *)PCI_FIX_ADDR(addr);
335 static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr)
337 *(volatile unsigned long __force *)PCI_FIX_ADDR(addr) = v;
340 static inline void __raw_writeq_be(unsigned long v, volatile void __iomem *addr)
342 __raw_writeq((__force unsigned long)cpu_to_be64(v), addr);
346 * Real mode versions of the above. Those instructions are only supposed
347 * to be used in hypervisor real mode as per the architecture spec.
349 static inline void __raw_rm_writeb(u8 val, volatile void __iomem *paddr)
351 __asm__ __volatile__("stbcix %0,0,%1"
352 : : "r" (val), "r" (paddr) : "memory");
355 static inline void __raw_rm_writew(u16 val, volatile void __iomem *paddr)
357 __asm__ __volatile__("sthcix %0,0,%1"
358 : : "r" (val), "r" (paddr) : "memory");
361 static inline void __raw_rm_writel(u32 val, volatile void __iomem *paddr)
363 __asm__ __volatile__("stwcix %0,0,%1"
364 : : "r" (val), "r" (paddr) : "memory");
367 static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr)
369 __asm__ __volatile__("stdcix %0,0,%1"
370 : : "r" (val), "r" (paddr) : "memory");
373 static inline void __raw_rm_writeq_be(u64 val, volatile void __iomem *paddr)
375 __raw_rm_writeq((__force u64)cpu_to_be64(val), paddr);
378 static inline u8 __raw_rm_readb(volatile void __iomem *paddr)
381 __asm__ __volatile__("lbzcix %0,0, %1"
382 : "=r" (ret) : "r" (paddr) : "memory");
386 static inline u16 __raw_rm_readw(volatile void __iomem *paddr)
389 __asm__ __volatile__("lhzcix %0,0, %1"
390 : "=r" (ret) : "r" (paddr) : "memory");
394 static inline u32 __raw_rm_readl(volatile void __iomem *paddr)
397 __asm__ __volatile__("lwzcix %0,0, %1"
398 : "=r" (ret) : "r" (paddr) : "memory");
402 static inline u64 __raw_rm_readq(volatile void __iomem *paddr)
405 __asm__ __volatile__("ldcix %0,0, %1"
406 : "=r" (ret) : "r" (paddr) : "memory");
409 #endif /* __powerpc64__ */
413 * PCI PIO and MMIO accessors.
416 * On 32 bits, PIO operations have a recovery mechanism in case they trigger
417 * machine checks (which they occasionally do when probing non existing
418 * IO ports on some platforms, like PowerMac and 8xx).
419 * I always found it to be of dubious reliability and I am tempted to get
420 * rid of it one of these days. So if you think it's important to keep it,
421 * please voice up asap. We never had it for 64 bits and I do not intend
427 #define __do_in_asm(name, op) \
428 static inline unsigned int name(unsigned int port) \
431 __asm__ __volatile__( \
433 "0:" op " %0,0,%1\n" \
438 ".section .fixup,\"ax\"\n" \
447 : "r" (port + _IO_BASE) \
452 #define __do_out_asm(name, op) \
453 static inline void name(unsigned int val, unsigned int port) \
455 __asm__ __volatile__( \
457 "0:" op " %0,0,%1\n" \
462 : : "r" (val), "r" (port + _IO_BASE) \
466 __do_in_asm(_rec_inb, "lbzx")
467 __do_in_asm(_rec_inw, "lhbrx")
468 __do_in_asm(_rec_inl, "lwbrx")
469 __do_out_asm(_rec_outb, "stbx")
470 __do_out_asm(_rec_outw, "sthbrx")
471 __do_out_asm(_rec_outl, "stwbrx")
473 #endif /* CONFIG_PPC32 */
475 /* The "__do_*" operations below provide the actual "base" implementation
476 * for each of the defined accessors. Some of them use the out_* functions
477 * directly, some of them still use EEH, though we might change that in the
478 * future. Those macros below provide the necessary argument swapping and
479 * handling of the IO base for PIO.
481 * They are themselves used by the macros that define the actual accessors
482 * and can be used by the hooks if any.
484 * Note that PIO operations are always defined in terms of their corresonding
485 * MMIO operations. That allows platforms like iSeries who want to modify the
486 * behaviour of both to only hook on the MMIO version and get both. It's also
487 * possible to hook directly at the toplevel PIO operation if they have to
488 * be handled differently
490 #define __do_writeb(val, addr) out_8(PCI_FIX_ADDR(addr), val)
491 #define __do_writew(val, addr) out_le16(PCI_FIX_ADDR(addr), val)
492 #define __do_writel(val, addr) out_le32(PCI_FIX_ADDR(addr), val)
493 #define __do_writeq(val, addr) out_le64(PCI_FIX_ADDR(addr), val)
494 #define __do_writew_be(val, addr) out_be16(PCI_FIX_ADDR(addr), val)
495 #define __do_writel_be(val, addr) out_be32(PCI_FIX_ADDR(addr), val)
496 #define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val)
499 #define __do_readb(addr) eeh_readb(PCI_FIX_ADDR(addr))
500 #define __do_readw(addr) eeh_readw(PCI_FIX_ADDR(addr))
501 #define __do_readl(addr) eeh_readl(PCI_FIX_ADDR(addr))
502 #define __do_readq(addr) eeh_readq(PCI_FIX_ADDR(addr))
503 #define __do_readw_be(addr) eeh_readw_be(PCI_FIX_ADDR(addr))
504 #define __do_readl_be(addr) eeh_readl_be(PCI_FIX_ADDR(addr))
505 #define __do_readq_be(addr) eeh_readq_be(PCI_FIX_ADDR(addr))
506 #else /* CONFIG_EEH */
507 #define __do_readb(addr) in_8(PCI_FIX_ADDR(addr))
508 #define __do_readw(addr) in_le16(PCI_FIX_ADDR(addr))
509 #define __do_readl(addr) in_le32(PCI_FIX_ADDR(addr))
510 #define __do_readq(addr) in_le64(PCI_FIX_ADDR(addr))
511 #define __do_readw_be(addr) in_be16(PCI_FIX_ADDR(addr))
512 #define __do_readl_be(addr) in_be32(PCI_FIX_ADDR(addr))
513 #define __do_readq_be(addr) in_be64(PCI_FIX_ADDR(addr))
514 #endif /* !defined(CONFIG_EEH) */
517 #define __do_outb(val, port) _rec_outb(val, port)
518 #define __do_outw(val, port) _rec_outw(val, port)
519 #define __do_outl(val, port) _rec_outl(val, port)
520 #define __do_inb(port) _rec_inb(port)
521 #define __do_inw(port) _rec_inw(port)
522 #define __do_inl(port) _rec_inl(port)
523 #else /* CONFIG_PPC32 */
524 #define __do_outb(val, port) writeb(val,(PCI_IO_ADDR)_IO_BASE+port);
525 #define __do_outw(val, port) writew(val,(PCI_IO_ADDR)_IO_BASE+port);
526 #define __do_outl(val, port) writel(val,(PCI_IO_ADDR)_IO_BASE+port);
527 #define __do_inb(port) readb((PCI_IO_ADDR)_IO_BASE + port);
528 #define __do_inw(port) readw((PCI_IO_ADDR)_IO_BASE + port);
529 #define __do_inl(port) readl((PCI_IO_ADDR)_IO_BASE + port);
530 #endif /* !CONFIG_PPC32 */
533 #define __do_readsb(a, b, n) eeh_readsb(PCI_FIX_ADDR(a), (b), (n))
534 #define __do_readsw(a, b, n) eeh_readsw(PCI_FIX_ADDR(a), (b), (n))
535 #define __do_readsl(a, b, n) eeh_readsl(PCI_FIX_ADDR(a), (b), (n))
536 #else /* CONFIG_EEH */
537 #define __do_readsb(a, b, n) _insb(PCI_FIX_ADDR(a), (b), (n))
538 #define __do_readsw(a, b, n) _insw(PCI_FIX_ADDR(a), (b), (n))
539 #define __do_readsl(a, b, n) _insl(PCI_FIX_ADDR(a), (b), (n))
540 #endif /* !CONFIG_EEH */
541 #define __do_writesb(a, b, n) _outsb(PCI_FIX_ADDR(a),(b),(n))
542 #define __do_writesw(a, b, n) _outsw(PCI_FIX_ADDR(a),(b),(n))
543 #define __do_writesl(a, b, n) _outsl(PCI_FIX_ADDR(a),(b),(n))
545 #define __do_insb(p, b, n) readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
546 #define __do_insw(p, b, n) readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
547 #define __do_insl(p, b, n) readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
548 #define __do_outsb(p, b, n) writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
549 #define __do_outsw(p, b, n) writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
550 #define __do_outsl(p, b, n) writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
552 #define __do_memset_io(addr, c, n) \
553 _memset_io(PCI_FIX_ADDR(addr), c, n)
554 #define __do_memcpy_toio(dst, src, n) \
555 _memcpy_toio(PCI_FIX_ADDR(dst), src, n)
558 #define __do_memcpy_fromio(dst, src, n) \
559 eeh_memcpy_fromio(dst, PCI_FIX_ADDR(src), n)
560 #else /* CONFIG_EEH */
561 #define __do_memcpy_fromio(dst, src, n) \
562 _memcpy_fromio(dst,PCI_FIX_ADDR(src),n)
563 #endif /* !CONFIG_EEH */
565 #ifdef CONFIG_PPC_INDIRECT_PIO
566 #define DEF_PCI_HOOK_pio(x) x
568 #define DEF_PCI_HOOK_pio(x) NULL
571 #ifdef CONFIG_PPC_INDIRECT_MMIO
572 #define DEF_PCI_HOOK_mem(x) x
574 #define DEF_PCI_HOOK_mem(x) NULL
577 /* Structure containing all the hooks */
578 extern struct ppc_pci_io {
580 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) ret (*name) at;
581 #define DEF_PCI_AC_NORET(name, at, al, space, aa) void (*name) at;
583 #include <asm/io-defs.h>
585 #undef DEF_PCI_AC_RET
586 #undef DEF_PCI_AC_NORET
590 /* The inline wrappers */
591 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) \
592 static inline ret name at \
594 if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \
595 return ppc_pci_io.name al; \
596 return __do_##name al; \
599 #define DEF_PCI_AC_NORET(name, at, al, space, aa) \
600 static inline void name at \
602 if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \
603 ppc_pci_io.name al; \
608 #include <asm/io-defs.h>
610 #undef DEF_PCI_AC_RET
611 #undef DEF_PCI_AC_NORET
613 /* Some drivers check for the presence of readq & writeq with
614 * a #ifdef, so we make them happy here.
618 #define writeq writeq
622 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
625 #define xlate_dev_mem_ptr(p) __va(p)
628 * Convert a virtual cached pointer to an uncached pointer
630 #define xlate_dev_kmem_ptr(p) p
633 * We don't do relaxed operations yet, at least not with this semantic
635 #define readb_relaxed(addr) readb(addr)
636 #define readw_relaxed(addr) readw(addr)
637 #define readl_relaxed(addr) readl(addr)
638 #define readq_relaxed(addr) readq(addr)
639 #define writeb_relaxed(v, addr) writeb(v, addr)
640 #define writew_relaxed(v, addr) writew(v, addr)
641 #define writel_relaxed(v, addr) writel(v, addr)
642 #define writeq_relaxed(v, addr) writeq(v, addr)
644 #include <asm-generic/iomap.h>
646 static inline void iosync(void)
648 __asm__ __volatile__ ("sync" : : : "memory");
651 /* Enforce in-order execution of data I/O.
652 * No distinction between read/write on PPC; use eieio for all three.
653 * Those are fairly week though. They don't provide a barrier between
654 * MMIO and cacheable storage nor do they provide a barrier vs. locks,
655 * they only provide barriers between 2 __raw MMIO operations and
656 * possibly break write combining.
658 #define iobarrier_rw() eieio()
659 #define iobarrier_r() eieio()
660 #define iobarrier_w() eieio()
664 * output pause versions need a delay at least for the
665 * w83c105 ide controller in a p610.
667 #define inb_p(port) inb(port)
668 #define outb_p(val, port) (udelay(1), outb((val), (port)))
669 #define inw_p(port) inw(port)
670 #define outw_p(val, port) (udelay(1), outw((val), (port)))
671 #define inl_p(port) inl(port)
672 #define outl_p(val, port) (udelay(1), outl((val), (port)))
675 #define IO_SPACE_LIMIT ~(0UL)
679 * ioremap - map bus memory into CPU space
680 * @address: bus address of the memory
681 * @size: size of the resource to map
683 * ioremap performs a platform specific sequence of operations to
684 * make bus memory CPU accessible via the readb/readw/readl/writeb/
685 * writew/writel functions and the other mmio helpers. The returned
686 * address is not guaranteed to be usable directly as a virtual
689 * We provide a few variations of it:
691 * * ioremap is the standard one and provides non-cacheable guarded mappings
692 * and can be hooked by the platform via ppc_md
694 * * ioremap_prot allows to specify the page flags as an argument and can
695 * also be hooked by the platform via ppc_md.
697 * * ioremap_nocache is identical to ioremap
699 * * ioremap_wc enables write combining
701 * * ioremap_wt enables write through
703 * * ioremap_coherent maps coherent cached memory
705 * * iounmap undoes such a mapping and can be hooked
707 * * __ioremap_at (and the pending __iounmap_at) are low level functions to
708 * create hand-made mappings for use only by the PCI code and cannot
709 * currently be hooked. Must be page aligned.
711 * * __ioremap is the low level implementation used by ioremap and
712 * ioremap_prot and cannot be hooked (but can be used by a hook on one
713 * of the previous ones)
715 * * __ioremap_caller is the same as above but takes an explicit caller
716 * reference rather than using __builtin_return_address(0)
718 * * __iounmap, is the low level implementation used by iounmap and cannot
719 * be hooked (but can be used by a hook on iounmap)
722 extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
723 extern void __iomem *ioremap_prot(phys_addr_t address, unsigned long size,
724 unsigned long flags);
725 extern void __iomem *ioremap_wc(phys_addr_t address, unsigned long size);
726 void __iomem *ioremap_wt(phys_addr_t address, unsigned long size);
727 void __iomem *ioremap_coherent(phys_addr_t address, unsigned long size);
728 #define ioremap_nocache(addr, size) ioremap((addr), (size))
729 #define ioremap_uc(addr, size) ioremap((addr), (size))
730 #define ioremap_cache(addr, size) \
731 ioremap_prot((addr), (size), pgprot_val(PAGE_KERNEL))
733 extern void iounmap(volatile void __iomem *addr);
735 extern void __iomem *__ioremap(phys_addr_t, unsigned long size,
736 unsigned long flags);
737 extern void __iomem *__ioremap_caller(phys_addr_t, unsigned long size,
738 pgprot_t prot, void *caller);
740 extern void __iounmap(volatile void __iomem *addr);
742 extern void __iomem * __ioremap_at(phys_addr_t pa, void *ea,
743 unsigned long size, pgprot_t prot);
744 extern void __iounmap_at(void *ea, unsigned long size);
747 * When CONFIG_PPC_INDIRECT_PIO is set, we use the generic iomap implementation
748 * which needs some additional definitions here. They basically allow PIO
749 * space overall to be 1GB. This will work as long as we never try to use
750 * iomap to map MMIO below 1GB which should be fine on ppc64
752 #define HAVE_ARCH_PIO_SIZE 1
753 #define PIO_OFFSET 0x00000000UL
754 #define PIO_MASK (FULL_IO_SIZE - 1)
755 #define PIO_RESERVED (FULL_IO_SIZE)
757 #define mmio_read16be(addr) readw_be(addr)
758 #define mmio_read32be(addr) readl_be(addr)
759 #define mmio_read64be(addr) readq_be(addr)
760 #define mmio_write16be(val, addr) writew_be(val, addr)
761 #define mmio_write32be(val, addr) writel_be(val, addr)
762 #define mmio_write64be(val, addr) writeq_be(val, addr)
763 #define mmio_insb(addr, dst, count) readsb(addr, dst, count)
764 #define mmio_insw(addr, dst, count) readsw(addr, dst, count)
765 #define mmio_insl(addr, dst, count) readsl(addr, dst, count)
766 #define mmio_outsb(addr, src, count) writesb(addr, src, count)
767 #define mmio_outsw(addr, src, count) writesw(addr, src, count)
768 #define mmio_outsl(addr, src, count) writesl(addr, src, count)
771 * virt_to_phys - map virtual addresses to physical
772 * @address: address to remap
774 * The returned physical address is the physical (CPU) mapping for
775 * the memory address given. It is only valid to use this function on
776 * addresses directly mapped or allocated via kmalloc.
778 * This function does not give bus mappings for DMA transfers. In
779 * almost all conceivable cases a device driver should not be using
782 static inline unsigned long virt_to_phys(volatile void * address)
784 WARN_ON(IS_ENABLED(CONFIG_DEBUG_VIRTUAL) && !virt_addr_valid(address));
786 return __pa((unsigned long)address);
790 * phys_to_virt - map physical address to virtual
791 * @address: address to remap
793 * The returned virtual address is a current CPU mapping for
794 * the memory address given. It is only valid to use this function on
795 * addresses that have a kernel mapping
797 * This function does not handle bus mappings for DMA transfers. In
798 * almost all conceivable cases a device driver should not be using
801 static inline void * phys_to_virt(unsigned long address)
803 return (void *)__va(address);
807 * Change "struct page" to physical address.
809 static inline phys_addr_t page_to_phys(struct page *page)
811 unsigned long pfn = page_to_pfn(page);
813 WARN_ON(IS_ENABLED(CONFIG_DEBUG_VIRTUAL) && !pfn_valid(pfn));
815 return PFN_PHYS(pfn);
819 * 32 bits still uses virt_to_bus() for it's implementation of DMA
820 * mappings se we have to keep it defined here. We also have some old
821 * drivers (shame shame shame) that use bus_to_virt() and haven't been
822 * fixed yet so I need to define it here.
826 static inline unsigned long virt_to_bus(volatile void * address)
830 return __pa(address) + PCI_DRAM_OFFSET;
833 static inline void * bus_to_virt(unsigned long address)
837 return __va(address - PCI_DRAM_OFFSET);
840 #define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET)
842 #endif /* CONFIG_PPC32 */
845 #define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v))
846 #define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
848 #define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v))
849 #define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v))
851 #define setbits8(_addr, _v) out_8((_addr), in_8(_addr) | (_v))
852 #define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v))
854 /* Clear and set bits in one shot. These macros can be used to clear and
855 * set multiple bits in a register using a single read-modify-write. These
856 * macros can also be used to set a multiple-bit bit pattern using a mask,
857 * by specifying the mask in the 'clear' parameter and the new bit pattern
858 * in the 'set' parameter.
861 #define clrsetbits(type, addr, clear, set) \
862 out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
865 #define clrsetbits_be64(addr, clear, set) clrsetbits(be64, addr, clear, set)
866 #define clrsetbits_le64(addr, clear, set) clrsetbits(le64, addr, clear, set)
869 #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
870 #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
872 #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
873 #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
875 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
877 #endif /* __KERNEL__ */
879 #endif /* _ASM_POWERPC_IO_H */