1 #ifndef __ASM_POWERPC_IMC_PMU_H
2 #define __ASM_POWERPC_IMC_PMU_H
5 * IMC Nest Performance Monitor counter support.
7 * Copyright (C) 2017 Madhavan Srinivasan, IBM Corporation.
8 * (C) 2017 Anju T Sudhakar, IBM Corporation.
9 * (C) 2017 Hemant K Shaw, IBM Corporation.
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or later version.
17 #include <linux/perf_event.h>
18 #include <linux/slab.h>
24 * Compatibility macros for IMC devices
26 #define IMC_DTB_COMPAT "ibm,opal-in-memory-counters"
27 #define IMC_DTB_UNIT_COMPAT "ibm,imc-counters"
31 * LDBAR: Counter address and Enable/Disable macro.
32 * perf/imc-pmu.c has the LDBAR layout information.
34 #define THREAD_IMC_LDBAR_MASK 0x0003ffffffffe000ULL
35 #define THREAD_IMC_ENABLE 0x8000000000000000ULL
38 * Structure to hold memory address information for imc units.
46 * Place holder for nest pmu events and values.
55 /* Event attribute array index */
56 #define IMC_FORMAT_ATTR 0
57 #define IMC_EVENT_ATTR 1
58 #define IMC_CPUMASK_ATTR 2
59 #define IMC_NULL_ATTR 3
61 /* PMU Format attribute macros */
62 #define IMC_EVENT_OFFSET_MASK 0xffffffffULL
65 * Device tree parser code detects IMC pmu support and
66 * registers new IMC pmus. This structure will hold the
67 * pmu functions, events, counter memory information
68 * and attrs for each imc pmu and will be referenced at
69 * the time of pmu registration.
73 struct imc_mem_info *mem_info;
74 struct imc_events **events;
76 * Attribute groups for the PMU. Slot 0 used for
77 * format attribute, slot 1 used for cpusmask attribute,
78 * slot 2 used for event attribute. Slot 3 keep as
81 const struct attribute_group *attr_groups[4];
85 * flag to notify whether the memory is mmaped
86 * or allocated by kernel.
88 bool imc_counter_mmaped;
92 * Structure to hold id, lock and reference count for the imc events which
102 * In-Memory Collection Counters type.
103 * Data comes from Device tree.
104 * Three device type are supported.
108 IMC_TYPE_THREAD = 0x1,
110 IMC_TYPE_CHIP = 0x10,
114 * Domains for IMC PMUs
116 #define IMC_DOMAIN_NEST 1
117 #define IMC_DOMAIN_CORE 2
118 #define IMC_DOMAIN_THREAD 3
120 extern int init_imc_pmu(struct device_node *parent,
121 struct imc_pmu *pmu_ptr, int pmu_id);
122 extern void thread_imc_disable(void);
123 extern int get_max_nest_dev(void);
124 #endif /* __ASM_POWERPC_IMC_PMU_H */