1 #ifndef _ASM_POWERPC_EXCEPTION_H
2 #define _ASM_POWERPC_EXCEPTION_H
4 * Extracted from head_64.S
7 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
9 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
10 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
11 * Adapted for Power Macintosh by Paul Mackerras.
12 * Low-level exception handlers and MMU support
13 * rewritten by Paul Mackerras.
14 * Copyright (C) 1996 Paul Mackerras.
16 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
17 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
19 * This file contains the low-level support and setup for the
20 * PowerPC-64 platform, including trap and interrupt dispatch.
22 * This program is free software; you can redistribute it and/or
23 * modify it under the terms of the GNU General Public License
24 * as published by the Free Software Foundation; either version
25 * 2 of the License, or (at your option) any later version.
28 * The following macros define the code that appears as
29 * the prologue to each of the exception handlers. They
30 * are split into two parts to allow a single kernel binary
31 * to be used for pSeries and iSeries.
33 * We make as much of the exception code common between native
34 * exception handlers (including pSeries LPAR) and iSeries LPAR
35 * implementations as possible.
37 #include <asm/head-64.h>
38 #include <asm/feature-fixups.h>
40 /* PACA save area offsets (exgen, exmc, etc) */
51 #if defined(CONFIG_RELOCATABLE)
53 #define EX_SIZE 10 /* size in u64 units */
55 #define EX_SIZE 9 /* size in u64 units */
59 * maximum recursive depth of MCE exceptions
61 #define MAX_MCE_DEPTH 4
64 * EX_R3 is only used by the bad_stack handler. bad_stack reloads and
65 * saves DAR from SPRN_DAR, and EX_DAR is not used. So EX_R3 can overlap
72 #define STF_ENTRY_BARRIER_SLOT \
73 STF_ENTRY_BARRIER_FIXUP_SECTION; \
78 #define STF_EXIT_BARRIER_SLOT \
79 STF_EXIT_BARRIER_FIXUP_SECTION; \
88 * r10 must be free to use, r13 must be paca
90 #define INTERRUPT_TO_KERNEL \
91 STF_ENTRY_BARRIER_SLOT
94 * Macros for annotating the expected destination of (h)rfid
96 * The nop instructions allow us to insert one or more instructions to flush the
97 * L1-D cache when returning to userspace or a guest.
99 #define RFI_FLUSH_SLOT \
100 RFI_FLUSH_FIXUP_SECTION; \
105 #define RFI_TO_KERNEL \
108 #define RFI_TO_USER \
109 STF_EXIT_BARRIER_SLOT; \
114 #define RFI_TO_USER_OR_KERNEL \
115 STF_EXIT_BARRIER_SLOT; \
120 #define RFI_TO_GUEST \
121 STF_EXIT_BARRIER_SLOT; \
126 #define HRFI_TO_KERNEL \
129 #define HRFI_TO_USER \
130 STF_EXIT_BARRIER_SLOT; \
133 b hrfi_flush_fallback
135 #define HRFI_TO_USER_OR_KERNEL \
136 STF_EXIT_BARRIER_SLOT; \
139 b hrfi_flush_fallback
141 #define HRFI_TO_GUEST \
142 STF_EXIT_BARRIER_SLOT; \
145 b hrfi_flush_fallback
147 #define HRFI_TO_UNKNOWN \
148 STF_EXIT_BARRIER_SLOT; \
151 b hrfi_flush_fallback
154 * We're short on space and time in the exception prolog, so we can't
155 * use the normal LOAD_REG_IMMEDIATE macro to load the address of label.
156 * Instead we get the base of the kernel from paca->kernelbase and or in the low
157 * part of label. This requires that the label be within 64KB of kernelbase, and
158 * that kernelbase be 64K aligned.
160 #define LOAD_HANDLER(reg, label) \
161 ld reg,PACAKBASE(r13); /* get high part of &label */ \
162 ori reg,reg,FIXED_SYMBOL_ABS_ADDR(label)
164 #define __LOAD_HANDLER(reg, label) \
165 ld reg,PACAKBASE(r13); \
166 ori reg,reg,(ABS_ADDR(label))@l
169 * Branches from unrelocated code (e.g., interrupts) to labels outside
170 * head-y require >64K offsets.
172 #define __LOAD_FAR_HANDLER(reg, label) \
173 ld reg,PACAKBASE(r13); \
174 ori reg,reg,(ABS_ADDR(label))@l; \
175 addis reg,reg,(ABS_ADDR(label))@h
177 .macro EXCEPTION_PROLOG_2_REAL label, hsrr, set_ri
178 ld r10,PACAKMSR(r13) /* get MSR value for kernel */
180 xori r10,r10,MSR_RI /* Clear MSR_RI */
183 mfspr r11,SPRN_HSRR0 /* save HSRR0 */
185 mfspr r11,SPRN_SRR0 /* save SRR0 */
187 LOAD_HANDLER(r12, \label\())
190 mfspr r12,SPRN_HSRR1 /* and HSRR1 */
195 mfspr r12,SPRN_SRR1 /* and SRR1 */
199 b . /* prevent speculative execution */
202 .macro EXCEPTION_PROLOG_2_VIRT label, hsrr
203 #ifdef CONFIG_RELOCATABLE
205 mfspr r11,SPRN_HSRR0 /* save HSRR0 */
207 mfspr r11,SPRN_SRR0 /* save SRR0 */
209 LOAD_HANDLER(r12, \label\())
212 mfspr r12,SPRN_HSRR1 /* and HSRR1 */
214 mfspr r12,SPRN_SRR1 /* and HSRR1 */
217 mtmsrd r10,1 /* Set RI (EE=0) */
221 mfspr r11,SPRN_HSRR0 /* save HSRR0 */
222 mfspr r12,SPRN_HSRR1 /* and HSRR1 */
224 mfspr r11,SPRN_SRR0 /* save SRR0 */
225 mfspr r12,SPRN_SRR1 /* and SRR1 */
228 mtmsrd r10,1 /* Set RI (EE=0) */
233 /* Exception register prefixes */
237 #if defined(CONFIG_RELOCATABLE)
239 * If we support interrupts with relocation on AND we're a relocatable kernel,
240 * we need to use CTR to get to the 2nd level handler. So, save/restore it
243 #define SAVE_CTR(reg, area) mfctr reg ; std reg,area+EX_CTR(r13)
244 #define GET_CTR(reg, area) ld reg,area+EX_CTR(r13)
245 #define RESTORE_CTR(reg, area) ld reg,area+EX_CTR(r13) ; mtctr reg
247 /* ...else CTR is unused and in register. */
248 #define SAVE_CTR(reg, area)
249 #define GET_CTR(reg, area) mfctr reg
250 #define RESTORE_CTR(reg, area)
254 * PPR save/restore macros used in exceptions_64s.S
255 * Used for P7 or later processors
257 #define SAVE_PPR(area, ra) \
258 BEGIN_FTR_SECTION_NESTED(940) \
259 ld ra,area+EX_PPR(r13); /* Read PPR from paca */ \
261 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,940)
263 #define RESTORE_PPR_PACA(area, ra) \
264 BEGIN_FTR_SECTION_NESTED(941) \
265 ld ra,area+EX_PPR(r13); \
267 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,941)
270 * Get an SPR into a register if the CPU has the given feature
272 #define OPT_GET_SPR(ra, spr, ftr) \
273 BEGIN_FTR_SECTION_NESTED(943) \
275 END_FTR_SECTION_NESTED(ftr,ftr,943)
278 * Set an SPR from a register if the CPU has the given feature
280 #define OPT_SET_SPR(ra, spr, ftr) \
281 BEGIN_FTR_SECTION_NESTED(943) \
283 END_FTR_SECTION_NESTED(ftr,ftr,943)
286 * Save a register to the PACA if the CPU has the given feature
288 #define OPT_SAVE_REG_TO_PACA(offset, ra, ftr) \
289 BEGIN_FTR_SECTION_NESTED(943) \
290 std ra,offset(r13); \
291 END_FTR_SECTION_NESTED(ftr,ftr,943)
293 .macro EXCEPTION_PROLOG_0 area
295 std r9,\area\()+EX_R9(r13) /* save r9 */
296 OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR)
298 std r10,\area\()+EX_R10(r13) /* save r10 - r12 */
299 OPT_GET_SPR(r10, SPRN_CFAR, CPU_FTR_CFAR)
302 .macro EXCEPTION_PROLOG_1 hsrr, area, kvm, vec, bitmask
303 OPT_SAVE_REG_TO_PACA(\area\()+EX_PPR, r9, CPU_FTR_HAS_PPR)
304 OPT_SAVE_REG_TO_PACA(\area\()+EX_CFAR, r10, CPU_FTR_CFAR)
306 SAVE_CTR(r10, \area\())
313 lbz r10,PACAIRQSOFTMASK(r13)
314 andi. r10,r10,\bitmask
315 /* Associate vector numbers with bits in paca->irq_happened */
316 .if \vec == 0x500 || \vec == 0xea0
318 .elseif \vec == 0x900
320 .elseif \vec == 0xa00 || \vec == 0xe80
321 li r10,PACA_IRQ_DBELL
322 .elseif \vec == 0xe60
324 .elseif \vec == 0xf00
327 .abort "Bad maskable vector"
331 bne masked_Hinterrupt
337 std r11,\area\()+EX_R11(r13)
338 std r12,\area\()+EX_R12(r13)
340 std r10,\area\()+EX_R13(r13)
343 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
345 * If hv is possible, interrupts come into to the hv version
346 * of the kvmppc_interrupt code, which then jumps to the PR handler,
347 * kvmppc_interrupt_pr, if the guest is a PR guest.
349 #define kvmppc_interrupt kvmppc_interrupt_hv
351 #define kvmppc_interrupt kvmppc_interrupt_pr
355 * Branch to label using its 0xC000 address. This results in instruction
356 * address suitable for MSR[IR]=0 or 1, which allows relocation to be turned
357 * on using mtmsr rather than rfid.
359 * This could set the 0xc bits for !RELOCATABLE as an immediate, rather than
360 * load KBASE for a slight optimisation.
362 #define BRANCH_TO_C000(reg, label) \
363 __LOAD_HANDLER(reg, label); \
367 #ifdef CONFIG_RELOCATABLE
368 #define BRANCH_TO_COMMON(reg, label) \
369 __LOAD_HANDLER(reg, label); \
373 #define BRANCH_LINK_TO_FAR(label) \
374 __LOAD_FAR_HANDLER(r12, label); \
379 * KVM requires __LOAD_FAR_HANDLER.
381 * __BRANCH_TO_KVM_EXIT branches are also a special case because they
382 * explicitly use r9 then reload it from PACA before branching. Hence
383 * the double-underscore.
385 #define __BRANCH_TO_KVM_EXIT(area, label) \
387 std r9,HSTATE_SCRATCH1(r13); \
388 __LOAD_FAR_HANDLER(r9, label); \
390 ld r9,area+EX_R9(r13); \
394 #define BRANCH_TO_COMMON(reg, label) \
397 #define BRANCH_LINK_TO_FAR(label) \
400 #define __BRANCH_TO_KVM_EXIT(area, label) \
401 ld r9,area+EX_R9(r13); \
406 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
407 .macro KVMTEST hsrr, n
408 lbz r10,HSTATE_IN_GUEST(r13)
417 .macro KVM_HANDLER area, hsrr, n, skip
419 cmpwi r10,KVM_GUEST_MODE_SKIP
422 BEGIN_FTR_SECTION_NESTED(947)
423 ld r10,\area+EX_CFAR(r13)
424 std r10,HSTATE_CFAR(r13)
425 END_FTR_SECTION_NESTED(CPU_FTR_CFAR,CPU_FTR_CFAR,947)
428 BEGIN_FTR_SECTION_NESTED(948)
429 ld r10,\area+EX_PPR(r13)
430 std r10,HSTATE_PPR(r13)
431 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948)
432 ld r10,\area+EX_R10(r13)
433 std r12,HSTATE_SCRATCH0(r13)
435 /* HSRR variants have the 0x2 bit added to their trap number */
437 ori r12,r12,(\n + 0x2)
441 /* This reloads r9 before branching to kvmppc_interrupt */
442 __BRANCH_TO_KVM_EXIT(\area, kvmppc_interrupt)
446 ld r9,\area+EX_R9(r13)
447 ld r10,\area+EX_R10(r13)
449 b kvmppc_skip_Hinterrupt
451 b kvmppc_skip_interrupt
457 .macro KVMTEST hsrr, n
459 .macro KVM_HANDLER area, hsrr, n, skip
463 #define EXCEPTION_PROLOG_COMMON_1() \
464 std r9,_CCR(r1); /* save CR in stackframe */ \
465 std r11,_NIP(r1); /* save SRR0 in stackframe */ \
466 std r12,_MSR(r1); /* save SRR1 in stackframe */ \
467 std r10,0(r1); /* make stack chain pointer */ \
468 std r0,GPR0(r1); /* save r0 in stackframe */ \
469 std r10,GPR1(r1); /* save r1 in stackframe */ \
473 * The common exception prolog is used for all except a few exceptions
474 * such as a segment miss on a kernel address. We have to be prepared
475 * to take another exception from the point where we first touch the
476 * kernel stack onwards.
478 * On entry r13 points to the paca, r9-r13 are saved in the paca,
479 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and
480 * SRR1, and relocation is on.
482 #define EXCEPTION_PROLOG_COMMON(n, area) \
483 andi. r10,r12,MSR_PR; /* See if coming from user */ \
484 mr r10,r1; /* Save r1 */ \
485 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \
487 ld r1,PACAKSAVE(r13); /* kernel stack to use */ \
488 1: cmpdi cr1,r1,-INT_FRAME_SIZE; /* check if r1 is in userspace */ \
489 blt+ cr1,3f; /* abort if it is */ \
490 li r1,(n); /* will be reloaded later */ \
491 sth r1,PACA_TRAP_SAVE(r13); \
492 std r3,area+EX_R3(r13); \
493 addi r3,r13,area; /* r3 -> where regs are saved*/ \
494 RESTORE_CTR(r1, area); \
496 3: EXCEPTION_PROLOG_COMMON_1(); \
497 kuap_save_amr_and_lock r9, r10, cr1, cr0; \
498 beq 4f; /* if from kernel mode */ \
499 ACCOUNT_CPU_USER_ENTRY(r13, r9, r10); \
500 SAVE_PPR(area, r9); \
501 4: EXCEPTION_PROLOG_COMMON_2(area) \
502 EXCEPTION_PROLOG_COMMON_3(n) \
505 /* Save original regs values from save area to stack frame. */
506 #define EXCEPTION_PROLOG_COMMON_2(area) \
507 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \
508 ld r10,area+EX_R10(r13); \
511 ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \
512 ld r10,area+EX_R12(r13); \
513 ld r11,area+EX_R13(r13); \
517 BEGIN_FTR_SECTION_NESTED(66); \
518 ld r10,area+EX_CFAR(r13); \
519 std r10,ORIG_GPR3(r1); \
520 END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66); \
521 GET_CTR(r10, area); \
524 #define EXCEPTION_PROLOG_COMMON_3(n) \
525 std r2,GPR2(r1); /* save r2 in stackframe */ \
526 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
527 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
528 mflr r9; /* Get LR, later save to stack */ \
529 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
531 lbz r10,PACAIRQSOFTMASK(r13); \
532 mfspr r11,SPRN_XER; /* save XER in stackframe */ \
536 std r9,_TRAP(r1); /* set trap number */ \
538 ld r11,exception_marker@toc(r2); \
539 std r10,RESULT(r1); /* clear regs->result */ \
540 std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */
542 #define RUNLATCH_ON \
544 ld r3, PACA_THREAD_INFO(r13); \
545 ld r4,TI_LOCAL_FLAGS(r3); \
546 andi. r0,r4,_TLF_RUNLATCH; \
547 beql ppc64_runlatch_on_trampoline; \
548 END_FTR_SECTION_IFSET(CPU_FTR_CTRL)
550 #define EXCEPTION_COMMON(area, trap) \
551 EXCEPTION_PROLOG_COMMON(trap, area); \
554 * Exception where stack is already set in r1, r1 is saved in r10
556 #define EXCEPTION_COMMON_STACK(area, trap) \
557 EXCEPTION_PROLOG_COMMON_1(); \
558 kuap_save_amr_and_lock r9, r10, cr1; \
559 EXCEPTION_PROLOG_COMMON_2(area); \
560 EXCEPTION_PROLOG_COMMON_3(trap)
562 #define STD_EXCEPTION_COMMON(trap, hdlr) \
563 EXCEPTION_COMMON(PACA_EXGEN, trap); \
565 RECONCILE_IRQ_STATE(r10, r11); \
566 addi r3,r1,STACK_FRAME_OVERHEAD; \
571 * Like STD_EXCEPTION_COMMON, but for exceptions that can occur
572 * in the idle task and therefore need the special idle handling
573 * (finish nap and runlatch)
575 #define STD_EXCEPTION_COMMON_ASYNC(trap, hdlr) \
576 EXCEPTION_COMMON(PACA_EXGEN, trap); \
578 RECONCILE_IRQ_STATE(r10, r11); \
580 addi r3,r1,STACK_FRAME_OVERHEAD; \
582 b ret_from_except_lite
585 * When the idle code in power4_idle puts the CPU into NAP mode,
586 * it has to do so in a loop, and relies on the external interrupt
587 * and decrementer interrupt entry code to get it out of the loop.
588 * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags
589 * to signal that it is in the loop and needs help to get out.
591 #ifdef CONFIG_PPC_970_NAP
594 ld r11, PACA_THREAD_INFO(r13); \
595 ld r9,TI_LOCAL_FLAGS(r11); \
596 andi. r10,r9,_TLF_NAPPING; \
597 bnel power4_fixup_nap; \
598 END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
603 #endif /* __ASSEMBLY__ */
605 #endif /* _ASM_POWERPC_EXCEPTION_H */