1 #ifndef _ASM_POWERPC_EXCEPTION_H
2 #define _ASM_POWERPC_EXCEPTION_H
4 * Extracted from head_64.S
7 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
9 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
10 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
11 * Adapted for Power Macintosh by Paul Mackerras.
12 * Low-level exception handlers and MMU support
13 * rewritten by Paul Mackerras.
14 * Copyright (C) 1996 Paul Mackerras.
16 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
17 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
19 * This file contains the low-level support and setup for the
20 * PowerPC-64 platform, including trap and interrupt dispatch.
22 * This program is free software; you can redistribute it and/or
23 * modify it under the terms of the GNU General Public License
24 * as published by the Free Software Foundation; either version
25 * 2 of the License, or (at your option) any later version.
28 * The following macros define the code that appears as
29 * the prologue to each of the exception handlers. They
30 * are split into two parts to allow a single kernel binary
31 * to be used for pSeries and iSeries.
33 * We make as much of the exception code common between native
34 * exception handlers (including pSeries LPAR) and iSeries LPAR
35 * implementations as possible.
37 #include <asm/head-64.h>
38 #include <asm/feature-fixups.h>
40 /* PACA save area offsets (exgen, exmc, etc) */
51 #if defined(CONFIG_RELOCATABLE)
53 #define EX_SIZE 10 /* size in u64 units */
55 #define EX_SIZE 9 /* size in u64 units */
59 * maximum recursive depth of MCE exceptions
61 #define MAX_MCE_DEPTH 4
64 * EX_R3 is only used by the bad_stack handler. bad_stack reloads and
65 * saves DAR from SPRN_DAR, and EX_DAR is not used. So EX_R3 can overlap
72 #define STF_ENTRY_BARRIER_SLOT \
73 STF_ENTRY_BARRIER_FIXUP_SECTION; \
78 #define STF_EXIT_BARRIER_SLOT \
79 STF_EXIT_BARRIER_FIXUP_SECTION; \
88 * r10 must be free to use, r13 must be paca
90 #define INTERRUPT_TO_KERNEL \
91 STF_ENTRY_BARRIER_SLOT
94 * Macros for annotating the expected destination of (h)rfid
96 * The nop instructions allow us to insert one or more instructions to flush the
97 * L1-D cache when returning to userspace or a guest.
99 #define RFI_FLUSH_SLOT \
100 RFI_FLUSH_FIXUP_SECTION; \
105 #define RFI_TO_KERNEL \
108 #define RFI_TO_USER \
109 STF_EXIT_BARRIER_SLOT; \
114 #define RFI_TO_USER_OR_KERNEL \
115 STF_EXIT_BARRIER_SLOT; \
120 #define RFI_TO_GUEST \
121 STF_EXIT_BARRIER_SLOT; \
126 #define HRFI_TO_KERNEL \
129 #define HRFI_TO_USER \
130 STF_EXIT_BARRIER_SLOT; \
133 b hrfi_flush_fallback
135 #define HRFI_TO_USER_OR_KERNEL \
136 STF_EXIT_BARRIER_SLOT; \
139 b hrfi_flush_fallback
141 #define HRFI_TO_GUEST \
142 STF_EXIT_BARRIER_SLOT; \
145 b hrfi_flush_fallback
147 #define HRFI_TO_UNKNOWN \
148 STF_EXIT_BARRIER_SLOT; \
151 b hrfi_flush_fallback
154 * We're short on space and time in the exception prolog, so we can't
155 * use the normal LOAD_REG_IMMEDIATE macro to load the address of label.
156 * Instead we get the base of the kernel from paca->kernelbase and or in the low
157 * part of label. This requires that the label be within 64KB of kernelbase, and
158 * that kernelbase be 64K aligned.
160 #define LOAD_HANDLER(reg, label) \
161 ld reg,PACAKBASE(r13); /* get high part of &label */ \
162 ori reg,reg,FIXED_SYMBOL_ABS_ADDR(label)
164 #define __LOAD_HANDLER(reg, label) \
165 ld reg,PACAKBASE(r13); \
166 ori reg,reg,(ABS_ADDR(label))@l
169 * Branches from unrelocated code (e.g., interrupts) to labels outside
170 * head-y require >64K offsets.
172 #define __LOAD_FAR_HANDLER(reg, label) \
173 ld reg,PACAKBASE(r13); \
174 ori reg,reg,(ABS_ADDR(label))@l; \
175 addis reg,reg,(ABS_ADDR(label))@h
177 .macro EXCEPTION_PROLOG_2_REAL label, hsrr, set_ri
178 ld r10,PACAKMSR(r13) /* get MSR value for kernel */
180 xori r10,r10,MSR_RI /* Clear MSR_RI */
183 mfspr r11,SPRN_HSRR0 /* save HSRR0 */
185 mfspr r11,SPRN_SRR0 /* save SRR0 */
187 LOAD_HANDLER(r12, \label\())
190 mfspr r12,SPRN_HSRR1 /* and HSRR1 */
195 mfspr r12,SPRN_SRR1 /* and SRR1 */
199 b . /* prevent speculative execution */
202 .macro EXCEPTION_PROLOG_2_VIRT label, hsrr
203 #ifdef CONFIG_RELOCATABLE
205 mfspr r11,SPRN_HSRR0 /* save HSRR0 */
207 mfspr r11,SPRN_SRR0 /* save SRR0 */
209 LOAD_HANDLER(r12, \label\())
212 mfspr r12,SPRN_HSRR1 /* and HSRR1 */
214 mfspr r12,SPRN_SRR1 /* and HSRR1 */
217 mtmsrd r10,1 /* Set RI (EE=0) */
221 mfspr r11,SPRN_HSRR0 /* save HSRR0 */
222 mfspr r12,SPRN_HSRR1 /* and HSRR1 */
224 mfspr r11,SPRN_SRR0 /* save SRR0 */
225 mfspr r12,SPRN_SRR1 /* and SRR1 */
228 mtmsrd r10,1 /* Set RI (EE=0) */
234 * As EXCEPTION_PROLOG(), except we've already got relocation on so no need to
235 * rfid. Save CTR in case we're CONFIG_RELOCATABLE, in which case
236 * EXCEPTION_PROLOG_2_VIRT will be using CTR.
238 #define EXCEPTION_RELON_PROLOG(area, label, hsrr, extra, vec) \
239 SET_SCRATCH0(r13); /* save r13 */ \
240 EXCEPTION_PROLOG_0(area); \
241 EXCEPTION_PROLOG_1(area, extra, vec); \
242 EXCEPTION_PROLOG_2_VIRT label, hsrr
244 /* Exception register prefixes */
248 #if defined(CONFIG_RELOCATABLE)
250 * If we support interrupts with relocation on AND we're a relocatable kernel,
251 * we need to use CTR to get to the 2nd level handler. So, save/restore it
254 #define SAVE_CTR(reg, area) mfctr reg ; std reg,area+EX_CTR(r13)
255 #define GET_CTR(reg, area) ld reg,area+EX_CTR(r13)
256 #define RESTORE_CTR(reg, area) ld reg,area+EX_CTR(r13) ; mtctr reg
258 /* ...else CTR is unused and in register. */
259 #define SAVE_CTR(reg, area)
260 #define GET_CTR(reg, area) mfctr reg
261 #define RESTORE_CTR(reg, area)
265 * PPR save/restore macros used in exceptions_64s.S
266 * Used for P7 or later processors
268 #define SAVE_PPR(area, ra) \
269 BEGIN_FTR_SECTION_NESTED(940) \
270 ld ra,area+EX_PPR(r13); /* Read PPR from paca */ \
272 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,940)
274 #define RESTORE_PPR_PACA(area, ra) \
275 BEGIN_FTR_SECTION_NESTED(941) \
276 ld ra,area+EX_PPR(r13); \
278 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,941)
281 * Get an SPR into a register if the CPU has the given feature
283 #define OPT_GET_SPR(ra, spr, ftr) \
284 BEGIN_FTR_SECTION_NESTED(943) \
286 END_FTR_SECTION_NESTED(ftr,ftr,943)
289 * Set an SPR from a register if the CPU has the given feature
291 #define OPT_SET_SPR(ra, spr, ftr) \
292 BEGIN_FTR_SECTION_NESTED(943) \
294 END_FTR_SECTION_NESTED(ftr,ftr,943)
297 * Save a register to the PACA if the CPU has the given feature
299 #define OPT_SAVE_REG_TO_PACA(offset, ra, ftr) \
300 BEGIN_FTR_SECTION_NESTED(943) \
301 std ra,offset(r13); \
302 END_FTR_SECTION_NESTED(ftr,ftr,943)
304 #define EXCEPTION_PROLOG_0(area) \
306 std r9,area+EX_R9(r13); /* save r9 */ \
307 OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR); \
309 std r10,area+EX_R10(r13); /* save r10 - r12 */ \
310 OPT_GET_SPR(r10, SPRN_CFAR, CPU_FTR_CFAR)
312 #define __EXCEPTION_PROLOG_1_PRE(area) \
313 OPT_SAVE_REG_TO_PACA(area+EX_PPR, r9, CPU_FTR_HAS_PPR); \
314 OPT_SAVE_REG_TO_PACA(area+EX_CFAR, r10, CPU_FTR_CFAR); \
315 INTERRUPT_TO_KERNEL; \
316 SAVE_CTR(r10, area); \
319 #define __EXCEPTION_PROLOG_1_POST(area) \
320 std r11,area+EX_R11(r13); \
321 std r12,area+EX_R12(r13); \
323 std r10,area+EX_R13(r13)
326 * This version of the EXCEPTION_PROLOG_1 will carry
327 * addition parameter called "bitmask" to support
328 * checking of the interrupt maskable level in the SOFTEN_TEST.
329 * Intended to be used in MASKABLE_EXCPETION_* macros.
331 #define MASKABLE_EXCEPTION_PROLOG_1(area, extra, vec, bitmask) \
332 __EXCEPTION_PROLOG_1_PRE(area); \
333 extra(vec, bitmask); \
334 __EXCEPTION_PROLOG_1_POST(area)
337 * This version of the EXCEPTION_PROLOG_1 is intended
338 * to be used in STD_EXCEPTION* macros
340 #define _EXCEPTION_PROLOG_1(area, extra, vec) \
341 __EXCEPTION_PROLOG_1_PRE(area); \
343 __EXCEPTION_PROLOG_1_POST(area)
345 #define EXCEPTION_PROLOG_1(area, extra, vec) \
346 _EXCEPTION_PROLOG_1(area, extra, vec)
348 #define EXCEPTION_PROLOG(area, label, h, extra, vec) \
349 SET_SCRATCH0(r13); /* save r13 */ \
350 EXCEPTION_PROLOG_0(area); \
351 EXCEPTION_PROLOG_1(area, extra, vec); \
352 EXCEPTION_PROLOG_2_REAL label, h, 1
354 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
356 * If hv is possible, interrupts come into to the hv version
357 * of the kvmppc_interrupt code, which then jumps to the PR handler,
358 * kvmppc_interrupt_pr, if the guest is a PR guest.
360 #define kvmppc_interrupt kvmppc_interrupt_hv
362 #define kvmppc_interrupt kvmppc_interrupt_pr
366 * Branch to label using its 0xC000 address. This results in instruction
367 * address suitable for MSR[IR]=0 or 1, which allows relocation to be turned
368 * on using mtmsr rather than rfid.
370 * This could set the 0xc bits for !RELOCATABLE as an immediate, rather than
371 * load KBASE for a slight optimisation.
373 #define BRANCH_TO_C000(reg, label) \
374 __LOAD_HANDLER(reg, label); \
378 #ifdef CONFIG_RELOCATABLE
379 #define BRANCH_TO_COMMON(reg, label) \
380 __LOAD_HANDLER(reg, label); \
384 #define BRANCH_LINK_TO_FAR(label) \
385 __LOAD_FAR_HANDLER(r12, label); \
390 * KVM requires __LOAD_FAR_HANDLER.
392 * __BRANCH_TO_KVM_EXIT branches are also a special case because they
393 * explicitly use r9 then reload it from PACA before branching. Hence
394 * the double-underscore.
396 #define __BRANCH_TO_KVM_EXIT(area, label) \
398 std r9,HSTATE_SCRATCH1(r13); \
399 __LOAD_FAR_HANDLER(r9, label); \
401 ld r9,area+EX_R9(r13); \
405 #define BRANCH_TO_COMMON(reg, label) \
408 #define BRANCH_LINK_TO_FAR(label) \
411 #define __BRANCH_TO_KVM_EXIT(area, label) \
412 ld r9,area+EX_R9(r13); \
417 /* Do not enable RI */
418 #define EXCEPTION_PROLOG_NORI(area, label, h, extra, vec) \
419 EXCEPTION_PROLOG_0(area); \
420 EXCEPTION_PROLOG_1(area, extra, vec); \
421 EXCEPTION_PROLOG_2_REAL label, h, 0
423 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
424 .macro KVMTEST hsrr, n
425 lbz r10,HSTATE_IN_GUEST(r13)
434 .macro KVM_HANDLER area, hsrr, n
435 BEGIN_FTR_SECTION_NESTED(947)
436 ld r10,\area+EX_CFAR(r13)
437 std r10,HSTATE_CFAR(r13)
438 END_FTR_SECTION_NESTED(CPU_FTR_CFAR,CPU_FTR_CFAR,947)
439 BEGIN_FTR_SECTION_NESTED(948)
440 ld r10,\area+EX_PPR(r13)
441 std r10,HSTATE_PPR(r13)
442 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948)
443 ld r10,\area+EX_R10(r13)
444 std r12,HSTATE_SCRATCH0(r13)
447 /* This reloads r9 before branching to kvmppc_interrupt */
448 __BRANCH_TO_KVM_EXIT(\area, kvmppc_interrupt)
451 .macro KVM_HANDLER_SKIP area, hsrr, n
452 cmpwi r10,KVM_GUEST_MODE_SKIP
454 BEGIN_FTR_SECTION_NESTED(948)
455 ld r10,\area+EX_PPR(r13)
456 std r10,HSTATE_PPR(r13)
457 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948)
458 ld r10,\area+EX_R10(r13)
459 std r12,HSTATE_SCRATCH0(r13)
462 /* This reloads r9 before branching to kvmppc_interrupt */
463 __BRANCH_TO_KVM_EXIT(\area, kvmppc_interrupt)
465 ld r9,\area+EX_R9(r13)
466 ld r10,\area+EX_R10(r13)
468 b kvmppc_skip_Hinterrupt
470 b kvmppc_skip_interrupt
475 .macro KVMTEST hsrr, n
477 .macro KVM_HANDLER area, hsrr, n
479 .macro KVM_HANDLER_SKIP area, hsrr, n
485 #define EXCEPTION_PROLOG_COMMON_1() \
486 std r9,_CCR(r1); /* save CR in stackframe */ \
487 std r11,_NIP(r1); /* save SRR0 in stackframe */ \
488 std r12,_MSR(r1); /* save SRR1 in stackframe */ \
489 std r10,0(r1); /* make stack chain pointer */ \
490 std r0,GPR0(r1); /* save r0 in stackframe */ \
491 std r10,GPR1(r1); /* save r1 in stackframe */ \
495 * The common exception prolog is used for all except a few exceptions
496 * such as a segment miss on a kernel address. We have to be prepared
497 * to take another exception from the point where we first touch the
498 * kernel stack onwards.
500 * On entry r13 points to the paca, r9-r13 are saved in the paca,
501 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and
502 * SRR1, and relocation is on.
504 #define EXCEPTION_PROLOG_COMMON(n, area) \
505 andi. r10,r12,MSR_PR; /* See if coming from user */ \
506 mr r10,r1; /* Save r1 */ \
507 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \
509 ld r1,PACAKSAVE(r13); /* kernel stack to use */ \
510 1: cmpdi cr1,r1,-INT_FRAME_SIZE; /* check if r1 is in userspace */ \
511 blt+ cr1,3f; /* abort if it is */ \
512 li r1,(n); /* will be reloaded later */ \
513 sth r1,PACA_TRAP_SAVE(r13); \
514 std r3,area+EX_R3(r13); \
515 addi r3,r13,area; /* r3 -> where regs are saved*/ \
516 RESTORE_CTR(r1, area); \
518 3: EXCEPTION_PROLOG_COMMON_1(); \
519 kuap_save_amr_and_lock r9, r10, cr1, cr0; \
520 beq 4f; /* if from kernel mode */ \
521 ACCOUNT_CPU_USER_ENTRY(r13, r9, r10); \
522 SAVE_PPR(area, r9); \
523 4: EXCEPTION_PROLOG_COMMON_2(area) \
524 EXCEPTION_PROLOG_COMMON_3(n) \
527 /* Save original regs values from save area to stack frame. */
528 #define EXCEPTION_PROLOG_COMMON_2(area) \
529 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \
530 ld r10,area+EX_R10(r13); \
533 ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \
534 ld r10,area+EX_R12(r13); \
535 ld r11,area+EX_R13(r13); \
539 BEGIN_FTR_SECTION_NESTED(66); \
540 ld r10,area+EX_CFAR(r13); \
541 std r10,ORIG_GPR3(r1); \
542 END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66); \
543 GET_CTR(r10, area); \
546 #define EXCEPTION_PROLOG_COMMON_3(n) \
547 std r2,GPR2(r1); /* save r2 in stackframe */ \
548 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
549 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
550 mflr r9; /* Get LR, later save to stack */ \
551 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
553 lbz r10,PACAIRQSOFTMASK(r13); \
554 mfspr r11,SPRN_XER; /* save XER in stackframe */ \
558 std r9,_TRAP(r1); /* set trap number */ \
560 ld r11,exception_marker@toc(r2); \
561 std r10,RESULT(r1); /* clear regs->result */ \
562 std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */
567 #define STD_EXCEPTION(vec, label) \
568 EXCEPTION_PROLOG(PACA_EXGEN, label, EXC_STD, KVMTEST_PR, vec);
570 /* Version of above for when we have to branch out-of-line */
571 #define __OOL_EXCEPTION(vec, label, hdlr) \
573 EXCEPTION_PROLOG_0(PACA_EXGEN); \
576 #define STD_EXCEPTION_OOL(vec, label) \
577 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_PR, vec); \
578 EXCEPTION_PROLOG_2_REAL label, EXC_STD, 1
580 #define STD_EXCEPTION_HV(loc, vec, label) \
581 EXCEPTION_PROLOG(PACA_EXGEN, label, EXC_HV, KVMTEST_HV, vec)
583 #define STD_EXCEPTION_HV_OOL(vec, label) \
584 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, vec); \
585 EXCEPTION_PROLOG_2_REAL label, EXC_HV, 1
587 #define STD_RELON_EXCEPTION(loc, vec, label) \
588 /* No guest interrupts come through here */ \
589 EXCEPTION_RELON_PROLOG(PACA_EXGEN, label, EXC_STD, NOTEST, vec)
591 #define STD_RELON_EXCEPTION_OOL(vec, label) \
592 EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, vec); \
593 EXCEPTION_PROLOG_2_VIRT label, EXC_STD
595 #define STD_RELON_EXCEPTION_HV(loc, vec, label) \
596 EXCEPTION_RELON_PROLOG(PACA_EXGEN, label, EXC_HV, KVMTEST_HV, vec)
598 #define STD_RELON_EXCEPTION_HV_OOL(vec, label) \
599 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, vec); \
600 EXCEPTION_PROLOG_2_VIRT label, EXC_HV
602 .macro SOFTEN_TEST hsrr, vec, bitmask
603 lbz r10, PACAIRQSOFTMASK(r13)
604 andi. r10, r10, \bitmask
605 /* This associates vector numbers with bits in paca->irq_happened */
606 .if \vec == 0x500 || \vec == 0xea0
608 .elseif \vec == 0x900
610 .elseif \vec == 0xa00 || \vec == 0xe80
611 li r10, PACA_IRQ_DBELL
612 .elseif \vec == 0xe60
614 .elseif \vec == 0xf00
617 .abort "Bad maskable vector"
622 bne masked_Hinterrupt
628 #define SOFTEN_TEST_PR(vec, bitmask) \
629 KVMTEST EXC_STD, vec ; \
630 SOFTEN_TEST EXC_STD, vec, bitmask
632 #define SOFTEN_TEST_HV(vec, bitmask) \
633 KVMTEST EXC_HV, vec ; \
634 SOFTEN_TEST EXC_HV, vec, bitmask
636 #define KVMTEST_PR(vec) \
639 #define KVMTEST_HV(vec) \
642 #define SOFTEN_NOTEST_PR(vec, bitmask) SOFTEN_TEST EXC_STD, vec, bitmask
643 #define SOFTEN_NOTEST_HV(vec, bitmask) SOFTEN_TEST EXC_HV, vec, bitmask
645 #define __MASKABLE_EXCEPTION(vec, label, h, extra, bitmask) \
646 SET_SCRATCH0(r13); /* save r13 */ \
647 EXCEPTION_PROLOG_0(PACA_EXGEN); \
648 MASKABLE_EXCEPTION_PROLOG_1(PACA_EXGEN, extra, vec, bitmask); \
649 EXCEPTION_PROLOG_2_REAL label, h, 1
651 #define MASKABLE_EXCEPTION(vec, label, bitmask) \
652 __MASKABLE_EXCEPTION(vec, label, EXC_STD, SOFTEN_TEST_PR, bitmask)
654 #define MASKABLE_EXCEPTION_OOL(vec, label, bitmask) \
655 MASKABLE_EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_TEST_PR, vec, bitmask);\
656 EXCEPTION_PROLOG_2_REAL label, EXC_STD, 1
658 #define MASKABLE_EXCEPTION_HV(vec, label, bitmask) \
659 __MASKABLE_EXCEPTION(vec, label, EXC_HV, SOFTEN_TEST_HV, bitmask)
661 #define MASKABLE_EXCEPTION_HV_OOL(vec, label, bitmask) \
662 MASKABLE_EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_TEST_HV, vec, bitmask);\
663 EXCEPTION_PROLOG_2_REAL label, EXC_HV, 1
665 #define __MASKABLE_RELON_EXCEPTION(vec, label, h, extra, bitmask) \
666 SET_SCRATCH0(r13); /* save r13 */ \
667 EXCEPTION_PROLOG_0(PACA_EXGEN); \
668 MASKABLE_EXCEPTION_PROLOG_1(PACA_EXGEN, extra, vec, bitmask); \
669 EXCEPTION_PROLOG_2_VIRT label, h
671 #define MASKABLE_RELON_EXCEPTION(vec, label, bitmask) \
672 __MASKABLE_RELON_EXCEPTION(vec, label, EXC_STD, SOFTEN_NOTEST_PR, bitmask)
674 #define MASKABLE_RELON_EXCEPTION_OOL(vec, label, bitmask) \
675 MASKABLE_EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_NOTEST_PR, vec, bitmask);\
676 EXCEPTION_PROLOG_2_REAL label, EXC_STD, 1
678 #define MASKABLE_RELON_EXCEPTION_HV(vec, label, bitmask) \
679 __MASKABLE_RELON_EXCEPTION(vec, label, EXC_HV, SOFTEN_TEST_HV, bitmask)
681 #define MASKABLE_RELON_EXCEPTION_HV_OOL(vec, label, bitmask) \
682 MASKABLE_EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_TEST_HV, vec, bitmask);\
683 EXCEPTION_PROLOG_2_VIRT label, EXC_HV
686 * Our exception common code can be passed various "additions"
687 * to specify the behaviour of interrupts, whether to kick the
692 * This addition reconciles our actual IRQ state with the various software
693 * flags that track it. This may call C code.
695 #define ADD_RECONCILE RECONCILE_IRQ_STATE(r10,r11)
700 #define RUNLATCH_ON \
702 ld r3, PACA_THREAD_INFO(r13); \
703 ld r4,TI_LOCAL_FLAGS(r3); \
704 andi. r0,r4,_TLF_RUNLATCH; \
705 beql ppc64_runlatch_on_trampoline; \
706 END_FTR_SECTION_IFSET(CPU_FTR_CTRL)
708 #define EXCEPTION_COMMON(area, trap, label, hdlr, ret, additions) \
709 EXCEPTION_PROLOG_COMMON(trap, area); \
710 /* Volatile regs are potentially clobbered here */ \
712 addi r3,r1,STACK_FRAME_OVERHEAD; \
717 * Exception where stack is already set in r1, r1 is saved in r10, and it
718 * continues rather than returns.
720 #define EXCEPTION_COMMON_NORET_STACK(area, trap, label, hdlr, additions) \
721 EXCEPTION_PROLOG_COMMON_1(); \
722 kuap_save_amr_and_lock r9, r10, cr1; \
723 EXCEPTION_PROLOG_COMMON_2(area); \
724 EXCEPTION_PROLOG_COMMON_3(trap); \
725 /* Volatile regs are potentially clobbered here */ \
727 addi r3,r1,STACK_FRAME_OVERHEAD; \
730 #define STD_EXCEPTION_COMMON(trap, label, hdlr) \
731 EXCEPTION_COMMON(PACA_EXGEN, trap, label, hdlr, \
732 ret_from_except, ADD_NVGPRS;ADD_RECONCILE)
735 * Like STD_EXCEPTION_COMMON, but for exceptions that can occur
736 * in the idle task and therefore need the special idle handling
737 * (finish nap and runlatch)
739 #define STD_EXCEPTION_COMMON_ASYNC(trap, label, hdlr) \
740 EXCEPTION_COMMON(PACA_EXGEN, trap, label, hdlr, \
741 ret_from_except_lite, FINISH_NAP;ADD_RECONCILE;RUNLATCH_ON)
744 * When the idle code in power4_idle puts the CPU into NAP mode,
745 * it has to do so in a loop, and relies on the external interrupt
746 * and decrementer interrupt entry code to get it out of the loop.
747 * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags
748 * to signal that it is in the loop and needs help to get out.
750 #ifdef CONFIG_PPC_970_NAP
753 ld r11, PACA_THREAD_INFO(r13); \
754 ld r9,TI_LOCAL_FLAGS(r11); \
755 andi. r10,r9,_TLF_NAPPING; \
756 bnel power4_fixup_nap; \
757 END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
762 #endif /* __ASSEMBLY__ */
764 #endif /* _ASM_POWERPC_EXCEPTION_H */