1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_POWERPC_PGTABLE_RADIX_H
3 #define _ASM_POWERPC_PGTABLE_RADIX_H
5 #include <asm/asm-const.h>
8 #include <asm/cmpxchg.h>
11 #ifdef CONFIG_PPC_64K_PAGES
12 #include <asm/book3s/64/radix-64k.h>
14 #include <asm/book3s/64/radix-4k.h>
18 #include <asm/book3s/64/tlbflush-radix.h>
19 #include <asm/cpu_has_feature.h>
22 /* An empty PTE can still have a R or C writeback */
23 #define RADIX_PTE_NONE_MASK (_PAGE_DIRTY | _PAGE_ACCESSED)
25 /* Bits to set in a RPMD/RPUD/RPGD */
26 #define RADIX_PMD_VAL_BITS (0x8000000000000000UL | RADIX_PTE_INDEX_SIZE)
27 #define RADIX_PUD_VAL_BITS (0x8000000000000000UL | RADIX_PMD_INDEX_SIZE)
28 #define RADIX_PGD_VAL_BITS (0x8000000000000000UL | RADIX_PUD_INDEX_SIZE)
30 /* Don't have anything in the reserved bits and leaf bits */
31 #define RADIX_PMD_BAD_BITS 0x60000000000000e0UL
32 #define RADIX_PUD_BAD_BITS 0x60000000000000e0UL
33 #define RADIX_PGD_BAD_BITS 0x60000000000000e0UL
35 #define RADIX_PMD_SHIFT (PAGE_SHIFT + RADIX_PTE_INDEX_SIZE)
36 #define RADIX_PUD_SHIFT (RADIX_PMD_SHIFT + RADIX_PMD_INDEX_SIZE)
37 #define RADIX_PGD_SHIFT (RADIX_PUD_SHIFT + RADIX_PUD_INDEX_SIZE)
39 * Size of EA range mapped by our pagetables.
41 #define RADIX_PGTABLE_EADDR_SIZE (RADIX_PTE_INDEX_SIZE + RADIX_PMD_INDEX_SIZE + \
42 RADIX_PUD_INDEX_SIZE + RADIX_PGD_INDEX_SIZE + PAGE_SHIFT)
43 #define RADIX_PGTABLE_RANGE (ASM_CONST(1) << RADIX_PGTABLE_EADDR_SIZE)
46 * We support 52 bit address space, Use top bit for kernel
47 * virtual mapping. Also make sure kernel fit in the top
50 * +------------------+
51 * +------------------+ Kernel virtual map (0xc008000000000000)
55 * 0b11......+------------------+ Kernel linear map (0xc....)
59 * 0b10......+------------------+
63 * 0b01......+------------------+
67 * 0b00......+------------------+
70 * 3rd quadrant expanded:
71 * +------------------------------+
75 * +------------------------------+ Kernel vmemmap end (0xc010000000000000)
79 * +------------------------------+ Kernel IO map end/vmemap start
83 * +------------------------------+ Kernel vmap end/ IO map start
87 * +------------------------------+ Kernel virt start (0xc008000000000000)
91 * +------------------------------+ Kernel linear (0xc.....)
94 #define RADIX_KERN_VIRT_START ASM_CONST(0xc008000000000000)
96 * 49 = MAX_EA_BITS_PER_CONTEXT (hash specific). To make sure we pick
97 * the same value as hash.
99 #define RADIX_KERN_MAP_SIZE (1UL << 49)
101 #define RADIX_VMALLOC_START RADIX_KERN_VIRT_START
102 #define RADIX_VMALLOC_SIZE RADIX_KERN_MAP_SIZE
103 #define RADIX_VMALLOC_END (RADIX_VMALLOC_START + RADIX_VMALLOC_SIZE)
105 #define RADIX_KERN_IO_START RADIX_VMALLOC_END
106 #define RADIX_KERN_IO_SIZE RADIX_KERN_MAP_SIZE
107 #define RADIX_KERN_IO_END (RADIX_KERN_IO_START + RADIX_KERN_IO_SIZE)
109 #define RADIX_VMEMMAP_START RADIX_KERN_IO_END
110 #define RADIX_VMEMMAP_SIZE RADIX_KERN_MAP_SIZE
111 #define RADIX_VMEMMAP_END (RADIX_VMEMMAP_START + RADIX_VMEMMAP_SIZE)
114 #define RADIX_PTE_TABLE_SIZE (sizeof(pte_t) << RADIX_PTE_INDEX_SIZE)
115 #define RADIX_PMD_TABLE_SIZE (sizeof(pmd_t) << RADIX_PMD_INDEX_SIZE)
116 #define RADIX_PUD_TABLE_SIZE (sizeof(pud_t) << RADIX_PUD_INDEX_SIZE)
117 #define RADIX_PGD_TABLE_SIZE (sizeof(pgd_t) << RADIX_PGD_INDEX_SIZE)
119 #ifdef CONFIG_STRICT_KERNEL_RWX
120 extern void radix__mark_rodata_ro(void);
121 extern void radix__mark_initmem_nx(void);
124 extern void radix__ptep_set_access_flags(struct vm_area_struct *vma, pte_t *ptep,
125 pte_t entry, unsigned long address,
128 extern void radix__ptep_modify_prot_commit(struct vm_area_struct *vma,
129 unsigned long addr, pte_t *ptep,
130 pte_t old_pte, pte_t pte);
132 static inline unsigned long __radix_pte_update(pte_t *ptep, unsigned long clr,
135 __be64 old_be, tmp_be;
137 __asm__ __volatile__(
138 "1: ldarx %0,0,%3 # pte_update\n"
143 : "=&r" (old_be), "=&r" (tmp_be), "=m" (*ptep)
144 : "r" (ptep), "r" (cpu_to_be64(set)), "r" (cpu_to_be64(clr))
147 return be64_to_cpu(old_be);
150 static inline unsigned long radix__pte_update(struct mm_struct *mm,
152 pte_t *ptep, unsigned long clr,
156 unsigned long old_pte;
158 old_pte = __radix_pte_update(ptep, clr, set);
160 assert_pte_locked(mm, addr);
165 static inline pte_t radix__ptep_get_and_clear_full(struct mm_struct *mm,
167 pte_t *ptep, int full)
169 unsigned long old_pte;
172 old_pte = pte_val(*ptep);
175 old_pte = radix__pte_update(mm, addr, ptep, ~0ul, 0, 0);
177 return __pte(old_pte);
180 static inline int radix__pte_same(pte_t pte_a, pte_t pte_b)
182 return ((pte_raw(pte_a) ^ pte_raw(pte_b)) == 0);
185 static inline int radix__pte_none(pte_t pte)
187 return (pte_val(pte) & ~RADIX_PTE_NONE_MASK) == 0;
190 static inline void radix__set_pte_at(struct mm_struct *mm, unsigned long addr,
191 pte_t *ptep, pte_t pte, int percpu)
196 * The architecture suggests a ptesync after setting the pte, which
197 * orders the store that updates the pte with subsequent page table
198 * walk accesses which may load the pte. Without this it may be
199 * possible for a subsequent access to result in spurious fault.
201 * This is not necessary for correctness, because a spurious fault
202 * is tolerated by the page fault handler, and this store will
203 * eventually be seen. In testing, there was no noticable increase
204 * in user faults on POWER9. Avoiding ptesync here is a significant
205 * win for things like fork. If a future microarchitecture benefits
206 * from ptesync, it should probably go into update_mmu_cache, rather
207 * than set_pte_at (which is used to set ptes unrelated to faults).
209 * Spurious faults to vmalloc region are not tolerated, so there is
210 * a ptesync in flush_cache_vmap.
214 static inline int radix__pmd_bad(pmd_t pmd)
216 return !!(pmd_val(pmd) & RADIX_PMD_BAD_BITS);
219 static inline int radix__pmd_same(pmd_t pmd_a, pmd_t pmd_b)
221 return ((pmd_raw(pmd_a) ^ pmd_raw(pmd_b)) == 0);
224 static inline int radix__pud_bad(pud_t pud)
226 return !!(pud_val(pud) & RADIX_PUD_BAD_BITS);
230 static inline int radix__pgd_bad(pgd_t pgd)
232 return !!(pgd_val(pgd) & RADIX_PGD_BAD_BITS);
235 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
237 static inline int radix__pmd_trans_huge(pmd_t pmd)
239 return (pmd_val(pmd) & (_PAGE_PTE | _PAGE_DEVMAP)) == _PAGE_PTE;
242 static inline pmd_t radix__pmd_mkhuge(pmd_t pmd)
244 return __pmd(pmd_val(pmd) | _PAGE_PTE);
247 extern unsigned long radix__pmd_hugepage_update(struct mm_struct *mm, unsigned long addr,
248 pmd_t *pmdp, unsigned long clr,
250 extern pmd_t radix__pmdp_collapse_flush(struct vm_area_struct *vma,
251 unsigned long address, pmd_t *pmdp);
252 extern void radix__pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
254 extern pgtable_t radix__pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
255 extern pmd_t radix__pmdp_huge_get_and_clear(struct mm_struct *mm,
256 unsigned long addr, pmd_t *pmdp);
257 extern int radix__has_transparent_hugepage(void);
260 extern int __meminit radix__vmemmap_create_mapping(unsigned long start,
261 unsigned long page_size,
263 extern void radix__vmemmap_remove_mapping(unsigned long start,
264 unsigned long page_size);
266 extern int radix__map_kernel_page(unsigned long ea, unsigned long pa,
267 pgprot_t flags, unsigned int psz);
269 extern int radix__ioremap_range(unsigned long ea, phys_addr_t pa,
270 unsigned long size, pgprot_t prot, int nid);
272 static inline unsigned long radix__get_tree_size(void)
274 unsigned long rts_field;
276 * We support 52 bits, hence:
277 * bits 52 - 31 = 21, 0b10101
278 * RTS encoding details
279 * bits 0 - 3 of rts -> bits 6 - 8 unsigned long
280 * bits 4 - 5 of rts -> bits 62 - 63 of unsigned long
282 rts_field = (0x5UL << 5); /* 6 - 8 bits */
283 rts_field |= (0x2UL << 61);
288 #ifdef CONFIG_MEMORY_HOTPLUG
289 int radix__create_section_mapping(unsigned long start, unsigned long end, int nid);
290 int radix__remove_section_mapping(unsigned long start, unsigned long end);
291 #endif /* CONFIG_MEMORY_HOTPLUG */
292 #endif /* __ASSEMBLY__ */