1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_
3 #define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_
5 #include <asm-generic/5level-fixup.h>
8 #include <linux/mmdebug.h>
13 * Common bits between hash and Radix page table
15 #define _PAGE_BIT_SWAP_TYPE 0
21 #define _PAGE_EXEC 0x00001 /* execute permission */
22 #define _PAGE_WRITE 0x00002 /* write access allowed */
23 #define _PAGE_READ 0x00004 /* read access allowed */
24 #define _PAGE_RW (_PAGE_READ | _PAGE_WRITE)
25 #define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC)
26 #define _PAGE_PRIVILEGED 0x00008 /* kernel access only */
27 #define _PAGE_SAO 0x00010 /* Strong access order */
28 #define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */
29 #define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */
30 #define _PAGE_DIRTY 0x00080 /* C: page changed */
31 #define _PAGE_ACCESSED 0x00100 /* R: page referenced */
35 #define _RPAGE_SW0 0x2000000000000000UL
36 #define _RPAGE_SW1 0x00800
37 #define _RPAGE_SW2 0x00400
38 #define _RPAGE_SW3 0x00200
39 #define _RPAGE_RSV1 0x1000000000000000UL
40 #define _RPAGE_RSV2 0x0800000000000000UL
41 #define _RPAGE_RSV3 0x0400000000000000UL
42 #define _RPAGE_RSV4 0x0200000000000000UL
43 #define _RPAGE_RSV5 0x00040UL
45 #define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */
46 #define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */
49 * Top and bottom bits of RPN which can be used by hash
50 * translation mode, because we expect them to be zero
53 #define _RPAGE_RPN0 0x01000
54 #define _RPAGE_RPN1 0x02000
55 #define _RPAGE_RPN44 0x0100000000000000UL
56 #define _RPAGE_RPN43 0x0080000000000000UL
57 #define _RPAGE_RPN42 0x0040000000000000UL
58 #define _RPAGE_RPN41 0x0020000000000000UL
60 /* Max physical address bit as per radix table */
61 #define _RPAGE_PA_MAX 57
64 * Max physical address bit we will use for now.
66 * This is mostly a hardware limitation and for now Power9 has
69 * This is different from the number of physical bit required to address
70 * the last byte of memory. That is defined by MAX_PHYSMEM_BITS.
71 * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum
72 * number of sections we can support (SECTIONS_SHIFT).
74 * This is different from Radix page table limitation above and
75 * should always be less than that. The limit is done such that
76 * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX
77 * for hash linux page table specific bits.
79 * In order to be compatible with future hardware generations we keep
80 * some offsets and limit this for now to 53
82 #define _PAGE_PA_MAX 53
84 #define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */
85 #define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */
86 #define _PAGE_DEVMAP _RPAGE_SW1 /* software: ZONE_DEVICE page */
87 #define __HAVE_ARCH_PTE_DEVMAP
90 * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE
91 * Instead of fixing all of them, add an alternate define which
92 * maps CI pte mapping.
94 #define _PAGE_NO_CACHE _PAGE_TOLERANT
96 * We support _RPAGE_PA_MAX bit real address in pte. On the linux side
97 * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX
98 * and every thing below PAGE_SHIFT;
100 #define PTE_RPN_MASK (((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK))
102 * set of bits not changed in pmd_modify. Even though we have hash specific bits
103 * in here, on radix we expect them to be zero.
105 #define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
106 _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \
109 * user access blocked by key
111 #define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY)
112 #define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ)
113 #define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | \
114 _PAGE_RW | _PAGE_EXEC)
116 * No page size encoding in the linux PTE
118 #define _PAGE_PSIZE 0
120 * _PAGE_CHG_MASK masks of bits that are to be preserved across
123 #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
124 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \
127 #define H_PTE_PKEY (H_PTE_PKEY_BIT0 | H_PTE_PKEY_BIT1 | H_PTE_PKEY_BIT2 | \
128 H_PTE_PKEY_BIT3 | H_PTE_PKEY_BIT4)
130 * Mask of bits returned by pte_pgprot()
132 #define PAGE_PROT_BITS (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT | \
133 H_PAGE_4K_PFN | _PAGE_PRIVILEGED | _PAGE_ACCESSED | \
134 _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_EXEC | \
135 _PAGE_SOFT_DIRTY | H_PTE_PKEY)
137 * We define 2 sets of base prot bits, one for basic pages (ie,
138 * cacheable kernel and user pages) and one for non cacheable
139 * pages. We always set _PAGE_COHERENT when SMP is enabled or
140 * the processor might need it for DMA coherency.
142 #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE)
143 #define _PAGE_BASE (_PAGE_BASE_NC)
145 /* Permission masks used to generate the __P and __S table,
147 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h
149 * Write permissions imply read permissions for now (we could make write-only
150 * pages on BookE but we don't bother for now). Execute permission control is
151 * possible on platforms that define _PAGE_EXEC
153 * Note due to the way vm flags are laid out, the bits are XWR
155 #define PAGE_NONE __pgprot(_PAGE_BASE | _PAGE_PRIVILEGED)
156 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW)
157 #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_EXEC)
158 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_READ)
159 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC)
160 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_READ)
161 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC)
163 #define __P000 PAGE_NONE
164 #define __P001 PAGE_READONLY
165 #define __P010 PAGE_COPY
166 #define __P011 PAGE_COPY
167 #define __P100 PAGE_READONLY_X
168 #define __P101 PAGE_READONLY_X
169 #define __P110 PAGE_COPY_X
170 #define __P111 PAGE_COPY_X
172 #define __S000 PAGE_NONE
173 #define __S001 PAGE_READONLY
174 #define __S010 PAGE_SHARED
175 #define __S011 PAGE_SHARED
176 #define __S100 PAGE_READONLY_X
177 #define __S101 PAGE_READONLY_X
178 #define __S110 PAGE_SHARED_X
179 #define __S111 PAGE_SHARED_X
181 /* Permission masks used for kernel mappings */
182 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW)
183 #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
185 #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
186 _PAGE_NON_IDEMPOTENT)
187 #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX)
188 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO)
189 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX)
192 * Protection used for kernel text. We want the debuggers to be able to
193 * set breakpoints anywhere, so don't write protect the kernel text
194 * on platforms where such control is possible.
196 #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) || \
197 defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE)
198 #define PAGE_KERNEL_TEXT PAGE_KERNEL_X
200 #define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX
203 /* Make modules code happy. We don't set RO yet */
204 #define PAGE_KERNEL_EXEC PAGE_KERNEL_X
205 #define PAGE_AGP (PAGE_KERNEL_NC)
211 extern unsigned long __pte_index_size;
212 extern unsigned long __pmd_index_size;
213 extern unsigned long __pud_index_size;
214 extern unsigned long __pgd_index_size;
215 extern unsigned long __pmd_cache_index;
216 extern unsigned long __pud_cache_index;
217 #define PTE_INDEX_SIZE __pte_index_size
218 #define PMD_INDEX_SIZE __pmd_index_size
219 #define PUD_INDEX_SIZE __pud_index_size
220 #define PGD_INDEX_SIZE __pgd_index_size
221 #define PMD_CACHE_INDEX __pmd_cache_index
222 #define PUD_CACHE_INDEX __pud_cache_index
224 * Because of use of pte fragments and THP, size of page table
225 * are not always derived out of index size above.
227 extern unsigned long __pte_table_size;
228 extern unsigned long __pmd_table_size;
229 extern unsigned long __pud_table_size;
230 extern unsigned long __pgd_table_size;
231 #define PTE_TABLE_SIZE __pte_table_size
232 #define PMD_TABLE_SIZE __pmd_table_size
233 #define PUD_TABLE_SIZE __pud_table_size
234 #define PGD_TABLE_SIZE __pgd_table_size
236 extern unsigned long __pmd_val_bits;
237 extern unsigned long __pud_val_bits;
238 extern unsigned long __pgd_val_bits;
239 #define PMD_VAL_BITS __pmd_val_bits
240 #define PUD_VAL_BITS __pud_val_bits
241 #define PGD_VAL_BITS __pgd_val_bits
243 extern unsigned long __pte_frag_nr;
244 #define PTE_FRAG_NR __pte_frag_nr
245 extern unsigned long __pte_frag_size_shift;
246 #define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift
247 #define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT)
249 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
250 #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE)
251 #define PTRS_PER_PUD (1 << PUD_INDEX_SIZE)
252 #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
254 /* PMD_SHIFT determines what a second-level page table entry can map */
255 #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
256 #define PMD_SIZE (1UL << PMD_SHIFT)
257 #define PMD_MASK (~(PMD_SIZE-1))
259 /* PUD_SHIFT determines what a third-level page table entry can map */
260 #define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE)
261 #define PUD_SIZE (1UL << PUD_SHIFT)
262 #define PUD_MASK (~(PUD_SIZE-1))
264 /* PGDIR_SHIFT determines what a fourth-level page table entry can map */
265 #define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE)
266 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
267 #define PGDIR_MASK (~(PGDIR_SIZE-1))
269 /* Bits to mask out from a PMD to get to the PTE page */
270 #define PMD_MASKED_BITS 0xc0000000000000ffUL
271 /* Bits to mask out from a PUD to get to the PMD page */
272 #define PUD_MASKED_BITS 0xc0000000000000ffUL
273 /* Bits to mask out from a PGD to get to the PUD page */
274 #define PGD_MASKED_BITS 0xc0000000000000ffUL
276 extern unsigned long __vmalloc_start;
277 extern unsigned long __vmalloc_end;
278 #define VMALLOC_START __vmalloc_start
279 #define VMALLOC_END __vmalloc_end
281 extern unsigned long __kernel_virt_start;
282 extern unsigned long __kernel_virt_size;
283 extern unsigned long __kernel_io_start;
284 #define KERN_VIRT_START __kernel_virt_start
285 #define KERN_VIRT_SIZE __kernel_virt_size
286 #define KERN_IO_START __kernel_io_start
287 extern struct page *vmemmap;
288 extern unsigned long ioremap_bot;
289 extern unsigned long pci_io_base;
290 #endif /* __ASSEMBLY__ */
292 #include <asm/book3s/64/hash.h>
293 #include <asm/book3s/64/radix.h>
295 #ifdef CONFIG_PPC_64K_PAGES
296 #include <asm/book3s/64/pgtable-64k.h>
298 #include <asm/book3s/64/pgtable-4k.h>
301 #include <asm/barrier.h>
303 * The second half of the kernel virtual space is used for IO mappings,
304 * it's itself carved into the PIO region (ISA and PHB IO space) and
307 * ISA_IO_BASE = KERN_IO_START, 64K reserved area
308 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces
309 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE
311 #define FULL_IO_SIZE 0x80000000ul
312 #define ISA_IO_BASE (KERN_IO_START)
313 #define ISA_IO_END (KERN_IO_START + 0x10000ul)
314 #define PHB_IO_BASE (ISA_IO_END)
315 #define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE)
316 #define IOREMAP_BASE (PHB_IO_END)
317 #define IOREMAP_END (KERN_VIRT_START + KERN_VIRT_SIZE)
319 /* Advertise special mapping type for AGP */
320 #define HAVE_PAGE_AGP
322 /* Advertise support for _PAGE_SPECIAL */
323 #define __HAVE_ARCH_PTE_SPECIAL
328 * This is the default implementation of various PTE accessors, it's
329 * used in all cases except Book3S with 64K pages where we have a
330 * concept of sub-pages
334 #define __real_pte(e, p, o) ((real_pte_t){(e)})
335 #define __rpte_to_pte(r) ((r).pte)
336 #define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT)
338 #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \
341 shift = mmu_psize_defs[psize].shift; \
343 #define pte_iterate_hashed_end() } while(0)
346 * We expect this to be called only for user addresses or kernel virtual
347 * addresses other than the linear mapping.
349 #define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K
351 #endif /* __real_pte */
353 static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr,
354 pte_t *ptep, unsigned long clr,
355 unsigned long set, int huge)
358 return radix__pte_update(mm, addr, ptep, clr, set, huge);
359 return hash__pte_update(mm, addr, ptep, clr, set, huge);
362 * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update.
363 * We currently remove entries from the hashtable regardless of whether
364 * the entry was young or dirty.
366 * We should be more intelligent about this but for the moment we override
367 * these functions and force a tlb flush unconditionally
368 * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same
369 * function for both hash and radix.
371 static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
372 unsigned long addr, pte_t *ptep)
376 if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0)
378 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0);
379 return (old & _PAGE_ACCESSED) != 0;
382 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
383 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \
386 __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \
390 static inline int __pte_write(pte_t pte)
392 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_WRITE));
395 #ifdef CONFIG_NUMA_BALANCING
396 #define pte_savedwrite pte_savedwrite
397 static inline bool pte_savedwrite(pte_t pte)
400 * Saved write ptes are prot none ptes that doesn't have
401 * privileged bit sit. We mark prot none as one which has
402 * present and pviliged bit set and RWX cleared. To mark
403 * protnone which used to have _PAGE_WRITE set we clear
404 * the privileged bit.
406 return !(pte_raw(pte) & cpu_to_be64(_PAGE_RWX | _PAGE_PRIVILEGED));
409 #define pte_savedwrite pte_savedwrite
410 static inline bool pte_savedwrite(pte_t pte)
416 static inline int pte_write(pte_t pte)
418 return __pte_write(pte) || pte_savedwrite(pte);
421 static inline int pte_read(pte_t pte)
423 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_READ));
426 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
427 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
430 if (__pte_write(*ptep))
431 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0);
432 else if (unlikely(pte_savedwrite(*ptep)))
433 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 0);
436 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
437 unsigned long addr, pte_t *ptep)
440 * We should not find protnone for hugetlb, but this complete the
443 if (__pte_write(*ptep))
444 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1);
445 else if (unlikely(pte_savedwrite(*ptep)))
446 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 1);
449 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
450 static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
451 unsigned long addr, pte_t *ptep)
453 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0);
457 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
458 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
460 pte_t *ptep, int full)
462 if (full && radix_enabled()) {
464 * Let's skip the DD1 style pte update here. We know that
465 * this is a full mm pte clear and hence can be sure there is
466 * no parallel set_pte.
468 return radix__ptep_get_and_clear_full(mm, addr, ptep, full);
470 return ptep_get_and_clear(mm, addr, ptep);
474 static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
477 pte_update(mm, addr, ptep, ~0UL, 0, 0);
480 static inline int pte_dirty(pte_t pte)
482 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DIRTY));
485 static inline int pte_young(pte_t pte)
487 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_ACCESSED));
490 static inline int pte_special(pte_t pte)
492 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SPECIAL));
495 static inline pgprot_t pte_pgprot(pte_t pte) { return __pgprot(pte_val(pte) & PAGE_PROT_BITS); }
497 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
498 static inline bool pte_soft_dirty(pte_t pte)
500 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SOFT_DIRTY));
503 static inline pte_t pte_mksoft_dirty(pte_t pte)
505 return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY);
508 static inline pte_t pte_clear_soft_dirty(pte_t pte)
510 return __pte(pte_val(pte) & ~_PAGE_SOFT_DIRTY);
512 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
514 #ifdef CONFIG_NUMA_BALANCING
515 static inline int pte_protnone(pte_t pte)
517 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE | _PAGE_RWX)) ==
518 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE);
521 #define pte_mk_savedwrite pte_mk_savedwrite
522 static inline pte_t pte_mk_savedwrite(pte_t pte)
525 * Used by Autonuma subsystem to preserve the write bit
526 * while marking the pte PROT_NONE. Only allow this
529 VM_BUG_ON((pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_RWX | _PAGE_PRIVILEGED)) !=
530 cpu_to_be64(_PAGE_PRESENT | _PAGE_PRIVILEGED));
531 return __pte(pte_val(pte) & ~_PAGE_PRIVILEGED);
534 #define pte_clear_savedwrite pte_clear_savedwrite
535 static inline pte_t pte_clear_savedwrite(pte_t pte)
538 * Used by KSM subsystem to make a protnone pte readonly.
540 VM_BUG_ON(!pte_protnone(pte));
541 return __pte(pte_val(pte) | _PAGE_PRIVILEGED);
544 #define pte_clear_savedwrite pte_clear_savedwrite
545 static inline pte_t pte_clear_savedwrite(pte_t pte)
548 return __pte(pte_val(pte) & ~_PAGE_WRITE);
550 #endif /* CONFIG_NUMA_BALANCING */
552 static inline int pte_present(pte_t pte)
554 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT));
557 #ifdef CONFIG_PPC_MEM_KEYS
558 extern bool arch_pte_access_permitted(u64 pte, bool write, bool execute);
560 static inline bool arch_pte_access_permitted(u64 pte, bool write, bool execute)
564 #endif /* CONFIG_PPC_MEM_KEYS */
566 #define pte_access_permitted pte_access_permitted
567 static inline bool pte_access_permitted(pte_t pte, bool write)
569 unsigned long pteval = pte_val(pte);
570 /* Also check for pte_user */
571 unsigned long clear_pte_bits = _PAGE_PRIVILEGED;
573 * _PAGE_READ is needed for any access and will be
574 * cleared for PROT_NONE
576 unsigned long need_pte_bits = _PAGE_PRESENT | _PAGE_READ;
579 need_pte_bits |= _PAGE_WRITE;
581 if ((pteval & need_pte_bits) != need_pte_bits)
584 if ((pteval & clear_pte_bits) == clear_pte_bits)
587 return arch_pte_access_permitted(pte_val(pte), write, 0);
591 * Conversion functions: convert a page and protection to a page entry,
592 * and a page entry and page directory to the page they refer to.
594 * Even if PTEs can be unsigned long long, a PFN is always an unsigned
597 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
599 return __pte((((pte_basic_t)(pfn) << PAGE_SHIFT) & PTE_RPN_MASK) |
603 static inline unsigned long pte_pfn(pte_t pte)
605 return (pte_val(pte) & PTE_RPN_MASK) >> PAGE_SHIFT;
608 /* Generic modifiers for PTE bits */
609 static inline pte_t pte_wrprotect(pte_t pte)
611 if (unlikely(pte_savedwrite(pte)))
612 return pte_clear_savedwrite(pte);
613 return __pte(pte_val(pte) & ~_PAGE_WRITE);
616 static inline pte_t pte_mkclean(pte_t pte)
618 return __pte(pte_val(pte) & ~_PAGE_DIRTY);
621 static inline pte_t pte_mkold(pte_t pte)
623 return __pte(pte_val(pte) & ~_PAGE_ACCESSED);
626 static inline pte_t pte_mkwrite(pte_t pte)
629 * write implies read, hence set both
631 return __pte(pte_val(pte) | _PAGE_RW);
634 static inline pte_t pte_mkdirty(pte_t pte)
636 return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY);
639 static inline pte_t pte_mkyoung(pte_t pte)
641 return __pte(pte_val(pte) | _PAGE_ACCESSED);
644 static inline pte_t pte_mkspecial(pte_t pte)
646 return __pte(pte_val(pte) | _PAGE_SPECIAL);
649 static inline pte_t pte_mkhuge(pte_t pte)
654 static inline pte_t pte_mkdevmap(pte_t pte)
656 return __pte(pte_val(pte) | _PAGE_SPECIAL|_PAGE_DEVMAP);
660 * This is potentially called with a pmd as the argument, in which case it's not
661 * safe to check _PAGE_DEVMAP unless we also confirm that _PAGE_PTE is set.
662 * That's because the bit we use for _PAGE_DEVMAP is not reserved for software
663 * use in page directory entries (ie. non-ptes).
665 static inline int pte_devmap(pte_t pte)
667 u64 mask = cpu_to_be64(_PAGE_DEVMAP | _PAGE_PTE);
669 return (pte_raw(pte) & mask) == mask;
672 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
674 /* FIXME!! check whether this need to be a conditional */
675 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
678 static inline bool pte_user(pte_t pte)
680 return !(pte_raw(pte) & cpu_to_be64(_PAGE_PRIVILEGED));
683 /* Encode and de-code a swap entry */
684 #define MAX_SWAPFILES_CHECK() do { \
685 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \
687 * Don't have overlapping bits with _PAGE_HPTEFLAGS \
688 * We filter HPTEFLAGS on set_pte. \
690 BUILD_BUG_ON(_PAGE_HPTEFLAGS & (0x1f << _PAGE_BIT_SWAP_TYPE)); \
691 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \
694 * on pte we don't need handle RADIX_TREE_EXCEPTIONAL_SHIFT;
696 #define SWP_TYPE_BITS 5
697 #define __swp_type(x) (((x).val >> _PAGE_BIT_SWAP_TYPE) \
698 & ((1UL << SWP_TYPE_BITS) - 1))
699 #define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT)
700 #define __swp_entry(type, offset) ((swp_entry_t) { \
701 ((type) << _PAGE_BIT_SWAP_TYPE) \
702 | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)})
704 * swp_entry_t must be independent of pte bits. We build a swp_entry_t from
705 * swap type and offset we get from swap and convert that to pte to find a
706 * matching pte in linux page table.
707 * Clear bits not found in swap entries here.
709 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE })
710 #define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE)
712 #ifdef CONFIG_MEM_SOFT_DIRTY
713 #define _PAGE_SWP_SOFT_DIRTY (1UL << (SWP_TYPE_BITS + _PAGE_BIT_SWAP_TYPE))
715 #define _PAGE_SWP_SOFT_DIRTY 0UL
716 #endif /* CONFIG_MEM_SOFT_DIRTY */
718 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
719 static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
721 return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY);
724 static inline bool pte_swp_soft_dirty(pte_t pte)
726 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_SOFT_DIRTY));
729 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
731 return __pte(pte_val(pte) & ~_PAGE_SWP_SOFT_DIRTY);
733 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
735 static inline bool check_pte_access(unsigned long access, unsigned long ptev)
738 * This check for _PAGE_RWX and _PAGE_PRESENT bits
743 * This check for access to privilege space
745 if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED))
751 * Generic functions with hash/radix callbacks
754 static inline void __ptep_set_access_flags(struct mm_struct *mm,
755 pte_t *ptep, pte_t entry,
756 unsigned long address)
759 return radix__ptep_set_access_flags(mm, ptep, entry, address);
760 return hash__ptep_set_access_flags(ptep, entry);
763 #define __HAVE_ARCH_PTE_SAME
764 static inline int pte_same(pte_t pte_a, pte_t pte_b)
767 return radix__pte_same(pte_a, pte_b);
768 return hash__pte_same(pte_a, pte_b);
771 static inline int pte_none(pte_t pte)
774 return radix__pte_none(pte);
775 return hash__pte_none(pte);
778 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
779 pte_t *ptep, pte_t pte, int percpu)
782 return radix__set_pte_at(mm, addr, ptep, pte, percpu);
783 return hash__set_pte_at(mm, addr, ptep, pte, percpu);
786 #define _PAGE_CACHE_CTL (_PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT)
788 #define pgprot_noncached pgprot_noncached
789 static inline pgprot_t pgprot_noncached(pgprot_t prot)
791 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
792 _PAGE_NON_IDEMPOTENT);
795 #define pgprot_noncached_wc pgprot_noncached_wc
796 static inline pgprot_t pgprot_noncached_wc(pgprot_t prot)
798 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
802 #define pgprot_cached pgprot_cached
803 static inline pgprot_t pgprot_cached(pgprot_t prot)
805 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL));
808 #define pgprot_writecombine pgprot_writecombine
809 static inline pgprot_t pgprot_writecombine(pgprot_t prot)
811 return pgprot_noncached_wc(prot);
814 * check a pte mapping have cache inhibited property
816 static inline bool pte_ci(pte_t pte)
818 unsigned long pte_v = pte_val(pte);
820 if (((pte_v & _PAGE_CACHE_CTL) == _PAGE_TOLERANT) ||
821 ((pte_v & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT))
826 static inline void pmd_set(pmd_t *pmdp, unsigned long val)
831 static inline void pmd_clear(pmd_t *pmdp)
836 static inline int pmd_none(pmd_t pmd)
838 return !pmd_raw(pmd);
841 static inline int pmd_present(pmd_t pmd)
844 return !pmd_none(pmd);
847 static inline int pmd_bad(pmd_t pmd)
850 return radix__pmd_bad(pmd);
851 return hash__pmd_bad(pmd);
854 static inline void pud_set(pud_t *pudp, unsigned long val)
859 static inline void pud_clear(pud_t *pudp)
864 static inline int pud_none(pud_t pud)
866 return !pud_raw(pud);
869 static inline int pud_present(pud_t pud)
871 return !pud_none(pud);
874 extern struct page *pud_page(pud_t pud);
875 extern struct page *pmd_page(pmd_t pmd);
876 static inline pte_t pud_pte(pud_t pud)
878 return __pte_raw(pud_raw(pud));
881 static inline pud_t pte_pud(pte_t pte)
883 return __pud_raw(pte_raw(pte));
885 #define pud_write(pud) pte_write(pud_pte(pud))
887 static inline int pud_bad(pud_t pud)
890 return radix__pud_bad(pud);
891 return hash__pud_bad(pud);
894 #define pud_access_permitted pud_access_permitted
895 static inline bool pud_access_permitted(pud_t pud, bool write)
897 return pte_access_permitted(pud_pte(pud), write);
900 #define pgd_write(pgd) pte_write(pgd_pte(pgd))
901 static inline void pgd_set(pgd_t *pgdp, unsigned long val)
906 static inline void pgd_clear(pgd_t *pgdp)
911 static inline int pgd_none(pgd_t pgd)
913 return !pgd_raw(pgd);
916 static inline int pgd_present(pgd_t pgd)
918 return !pgd_none(pgd);
921 static inline pte_t pgd_pte(pgd_t pgd)
923 return __pte_raw(pgd_raw(pgd));
926 static inline pgd_t pte_pgd(pte_t pte)
928 return __pgd_raw(pte_raw(pte));
931 static inline int pgd_bad(pgd_t pgd)
934 return radix__pgd_bad(pgd);
935 return hash__pgd_bad(pgd);
938 #define pgd_access_permitted pgd_access_permitted
939 static inline bool pgd_access_permitted(pgd_t pgd, bool write)
941 return pte_access_permitted(pgd_pte(pgd), write);
944 extern struct page *pgd_page(pgd_t pgd);
946 /* Pointers in the page table tree are physical addresses */
947 #define __pgtable_ptr_val(ptr) __pa(ptr)
949 #define pmd_page_vaddr(pmd) __va(pmd_val(pmd) & ~PMD_MASKED_BITS)
950 #define pud_page_vaddr(pud) __va(pud_val(pud) & ~PUD_MASKED_BITS)
951 #define pgd_page_vaddr(pgd) __va(pgd_val(pgd) & ~PGD_MASKED_BITS)
953 #define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & (PTRS_PER_PGD - 1))
954 #define pud_index(address) (((address) >> (PUD_SHIFT)) & (PTRS_PER_PUD - 1))
955 #define pmd_index(address) (((address) >> (PMD_SHIFT)) & (PTRS_PER_PMD - 1))
956 #define pte_index(address) (((address) >> (PAGE_SHIFT)) & (PTRS_PER_PTE - 1))
959 * Find an entry in a page-table-directory. We combine the address region
960 * (the high order N bits) and the pgd portion of the address.
963 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
965 #define pud_offset(pgdp, addr) \
966 (((pud_t *) pgd_page_vaddr(*(pgdp))) + pud_index(addr))
967 #define pmd_offset(pudp,addr) \
968 (((pmd_t *) pud_page_vaddr(*(pudp))) + pmd_index(addr))
969 #define pte_offset_kernel(dir,addr) \
970 (((pte_t *) pmd_page_vaddr(*(dir))) + pte_index(addr))
972 #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr))
973 #define pte_unmap(pte) do { } while(0)
975 /* to find an entry in a kernel page-table-directory */
976 /* This now only contains the vmalloc pages */
977 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
979 #define pte_ERROR(e) \
980 pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
981 #define pmd_ERROR(e) \
982 pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
983 #define pud_ERROR(e) \
984 pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e))
985 #define pgd_ERROR(e) \
986 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
988 static inline int map_kernel_page(unsigned long ea, unsigned long pa,
991 if (radix_enabled()) {
992 #if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM)
993 unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift;
994 WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE");
996 return radix__map_kernel_page(ea, pa, __pgprot(flags), PAGE_SIZE);
998 return hash__map_kernel_page(ea, pa, flags);
1001 static inline int __meminit vmemmap_create_mapping(unsigned long start,
1002 unsigned long page_size,
1005 if (radix_enabled())
1006 return radix__vmemmap_create_mapping(start, page_size, phys);
1007 return hash__vmemmap_create_mapping(start, page_size, phys);
1010 #ifdef CONFIG_MEMORY_HOTPLUG
1011 static inline void vmemmap_remove_mapping(unsigned long start,
1012 unsigned long page_size)
1014 if (radix_enabled())
1015 return radix__vmemmap_remove_mapping(start, page_size);
1016 return hash__vmemmap_remove_mapping(start, page_size);
1019 struct page *realmode_pfn_to_page(unsigned long pfn);
1021 static inline pte_t pmd_pte(pmd_t pmd)
1023 return __pte_raw(pmd_raw(pmd));
1026 static inline pmd_t pte_pmd(pte_t pte)
1028 return __pmd_raw(pte_raw(pte));
1031 static inline pte_t *pmdp_ptep(pmd_t *pmd)
1033 return (pte_t *)pmd;
1035 #define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd))
1036 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd))
1037 #define pmd_young(pmd) pte_young(pmd_pte(pmd))
1038 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd)))
1039 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd)))
1040 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd)))
1041 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd)))
1042 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd)))
1043 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd)))
1044 #define pmd_mk_savedwrite(pmd) pte_pmd(pte_mk_savedwrite(pmd_pte(pmd)))
1045 #define pmd_clear_savedwrite(pmd) pte_pmd(pte_clear_savedwrite(pmd_pte(pmd)))
1047 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
1048 #define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd))
1049 #define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd)))
1050 #define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd)))
1051 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
1053 #ifdef CONFIG_NUMA_BALANCING
1054 static inline int pmd_protnone(pmd_t pmd)
1056 return pte_protnone(pmd_pte(pmd));
1058 #endif /* CONFIG_NUMA_BALANCING */
1060 #define pmd_write(pmd) pte_write(pmd_pte(pmd))
1061 #define __pmd_write(pmd) __pte_write(pmd_pte(pmd))
1062 #define pmd_savedwrite(pmd) pte_savedwrite(pmd_pte(pmd))
1064 #define pmd_access_permitted pmd_access_permitted
1065 static inline bool pmd_access_permitted(pmd_t pmd, bool write)
1067 return pte_access_permitted(pmd_pte(pmd), write);
1070 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
1071 extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot);
1072 extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot);
1073 extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot);
1074 extern void set_pmd_at(struct mm_struct *mm, unsigned long addr,
1075 pmd_t *pmdp, pmd_t pmd);
1076 extern void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
1078 extern int hash__has_transparent_hugepage(void);
1079 static inline int has_transparent_hugepage(void)
1081 if (radix_enabled())
1082 return radix__has_transparent_hugepage();
1083 return hash__has_transparent_hugepage();
1085 #define has_transparent_hugepage has_transparent_hugepage
1087 static inline unsigned long
1088 pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp,
1089 unsigned long clr, unsigned long set)
1091 if (radix_enabled())
1092 return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set);
1093 return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set);
1096 static inline int pmd_large(pmd_t pmd)
1098 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE));
1101 static inline pmd_t pmd_mknotpresent(pmd_t pmd)
1103 return __pmd(pmd_val(pmd) & ~_PAGE_PRESENT);
1106 * For radix we should always find H_PAGE_HASHPTE zero. Hence
1107 * the below will work for radix too
1109 static inline int __pmdp_test_and_clear_young(struct mm_struct *mm,
1110 unsigned long addr, pmd_t *pmdp)
1114 if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0)
1116 old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0);
1117 return ((old & _PAGE_ACCESSED) != 0);
1120 #define __HAVE_ARCH_PMDP_SET_WRPROTECT
1121 static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr,
1124 if (__pmd_write((*pmdp)))
1125 pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0);
1126 else if (unlikely(pmd_savedwrite(*pmdp)))
1127 pmd_hugepage_update(mm, addr, pmdp, 0, _PAGE_PRIVILEGED);
1130 static inline int pmd_trans_huge(pmd_t pmd)
1132 if (radix_enabled())
1133 return radix__pmd_trans_huge(pmd);
1134 return hash__pmd_trans_huge(pmd);
1137 #define __HAVE_ARCH_PMD_SAME
1138 static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b)
1140 if (radix_enabled())
1141 return radix__pmd_same(pmd_a, pmd_b);
1142 return hash__pmd_same(pmd_a, pmd_b);
1145 static inline pmd_t pmd_mkhuge(pmd_t pmd)
1147 if (radix_enabled())
1148 return radix__pmd_mkhuge(pmd);
1149 return hash__pmd_mkhuge(pmd);
1152 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
1153 extern int pmdp_set_access_flags(struct vm_area_struct *vma,
1154 unsigned long address, pmd_t *pmdp,
1155 pmd_t entry, int dirty);
1157 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
1158 extern int pmdp_test_and_clear_young(struct vm_area_struct *vma,
1159 unsigned long address, pmd_t *pmdp);
1161 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
1162 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
1163 unsigned long addr, pmd_t *pmdp)
1165 if (radix_enabled())
1166 return radix__pmdp_huge_get_and_clear(mm, addr, pmdp);
1167 return hash__pmdp_huge_get_and_clear(mm, addr, pmdp);
1170 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
1171 unsigned long address, pmd_t *pmdp)
1173 if (radix_enabled())
1174 return radix__pmdp_collapse_flush(vma, address, pmdp);
1175 return hash__pmdp_collapse_flush(vma, address, pmdp);
1177 #define pmdp_collapse_flush pmdp_collapse_flush
1179 #define __HAVE_ARCH_PGTABLE_DEPOSIT
1180 static inline void pgtable_trans_huge_deposit(struct mm_struct *mm,
1181 pmd_t *pmdp, pgtable_t pgtable)
1183 if (radix_enabled())
1184 return radix__pgtable_trans_huge_deposit(mm, pmdp, pgtable);
1185 return hash__pgtable_trans_huge_deposit(mm, pmdp, pgtable);
1188 #define __HAVE_ARCH_PGTABLE_WITHDRAW
1189 static inline pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm,
1192 if (radix_enabled())
1193 return radix__pgtable_trans_huge_withdraw(mm, pmdp);
1194 return hash__pgtable_trans_huge_withdraw(mm, pmdp);
1197 #define __HAVE_ARCH_PMDP_INVALIDATE
1198 extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address,
1201 #define pmd_move_must_withdraw pmd_move_must_withdraw
1203 static inline int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl,
1204 struct spinlock *old_pmd_ptl,
1205 struct vm_area_struct *vma)
1207 if (radix_enabled())
1210 * Archs like ppc64 use pgtable to store per pmd
1211 * specific information. So when we switch the pmd,
1212 * we should also withdraw and deposit the pgtable
1218 #define arch_needs_pgtable_deposit arch_needs_pgtable_deposit
1219 static inline bool arch_needs_pgtable_deposit(void)
1221 if (radix_enabled())
1225 extern void serialize_against_pte_lookup(struct mm_struct *mm);
1228 static inline pmd_t pmd_mkdevmap(pmd_t pmd)
1230 return __pmd(pmd_val(pmd) | (_PAGE_PTE | _PAGE_DEVMAP));
1233 static inline int pmd_devmap(pmd_t pmd)
1235 return pte_devmap(pmd_pte(pmd));
1238 static inline int pud_devmap(pud_t pud)
1243 static inline int pgd_devmap(pgd_t pgd)
1247 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1249 static inline const int pud_pfn(pud_t pud)
1252 * Currently all calls to pud_pfn() are gated around a pud_devmap()
1253 * check so this should never be used. If it grows another user we
1254 * want to know about it.
1260 #endif /* __ASSEMBLY__ */
1261 #endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */