1 #ifndef _ASM_POWERPC_BOOK3S_64_HASH_H
2 #define _ASM_POWERPC_BOOK3S_64_HASH_H
6 * Common bits between 4K and 64K pages in a linux-style PTE.
7 * These match the bits in the (hardware-defined) PowerPC PTE as closely
8 * as possible. Additional bits may be defined in pgtable-hash64-*.h
10 * Note: We only support user read/write permissions. Supervisor always
11 * have full read/write to pages above PAGE_OFFSET (pages below that
12 * always use the user access permissions).
14 * We could create separate kernel read-only if we used the 3 PP bits
15 * combinations that newer processors provide but we currently don't.
17 #define _PAGE_PTE 0x00001
18 #define _PAGE_PRESENT 0x00002 /* software: pte contains a translation */
19 #define _PAGE_BIT_SWAP_TYPE 2
20 #define _PAGE_USER 0x00004 /* matches one of the PP bits */
21 #define _PAGE_EXEC 0x00008 /* No execute on POWER4 and newer (we invert) */
22 #define _PAGE_GUARDED 0x00010
23 /* We can derive Memory coherence from _PAGE_NO_CACHE */
24 #define _PAGE_COHERENT 0x0
25 #define _PAGE_NO_CACHE 0x00020 /* I: cache inhibit */
26 #define _PAGE_WRITETHRU 0x00040 /* W: cache write-through */
27 #define _PAGE_DIRTY 0x00080 /* C: page changed */
28 #define _PAGE_ACCESSED 0x00100 /* R: page referenced */
29 #define _PAGE_RW 0x00200 /* software: user write access allowed */
30 #define _PAGE_HASHPTE 0x00400 /* software: pte has an associated HPTE */
31 #define _PAGE_BUSY 0x00800 /* software: PTE & hash are busy */
32 #define _PAGE_F_GIX 0x07000 /* full page: hidx bits */
33 #define _PAGE_F_GIX_SHIFT 12
34 #define _PAGE_F_SECOND 0x08000 /* Whether to use secondary hash or not */
35 #define _PAGE_SPECIAL 0x10000 /* software: special page */
38 * THP pages can't be special. So use the _PAGE_SPECIAL
40 #define _PAGE_SPLITTING _PAGE_SPECIAL
43 * We need to differentiate between explicit huge page and THP huge
44 * page, since THP huge page also need to track real subpage details
46 #define _PAGE_THP_HUGE _PAGE_4K_PFN
49 * set of bits not changed in pmd_modify.
51 #define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | \
52 _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_SPLITTING | \
53 _PAGE_THP_HUGE | _PAGE_PTE)
55 #ifdef CONFIG_PPC_64K_PAGES
56 #include <asm/book3s/64/hash-64k.h>
58 #include <asm/book3s/64/hash-4k.h>
62 * Size of EA range mapped by our pagetables.
64 #define PGTABLE_EADDR_SIZE (PTE_INDEX_SIZE + PMD_INDEX_SIZE + \
65 PUD_INDEX_SIZE + PGD_INDEX_SIZE + PAGE_SHIFT)
66 #define PGTABLE_RANGE (ASM_CONST(1) << PGTABLE_EADDR_SIZE)
68 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
69 #define PMD_CACHE_INDEX (PMD_INDEX_SIZE + 1)
71 #define PMD_CACHE_INDEX PMD_INDEX_SIZE
74 * Define the address range of the kernel non-linear virtual area
76 #define KERN_VIRT_START ASM_CONST(0xD000000000000000)
77 #define KERN_VIRT_SIZE ASM_CONST(0x0000100000000000)
80 * The vmalloc space starts at the beginning of that region, and
81 * occupies half of it on hash CPUs and a quarter of it on Book3E
82 * (we keep a quarter for the virtual memmap)
84 #define VMALLOC_START KERN_VIRT_START
85 #define VMALLOC_SIZE (KERN_VIRT_SIZE >> 1)
86 #define VMALLOC_END (VMALLOC_START + VMALLOC_SIZE)
91 #define REGION_SHIFT 60UL
92 #define REGION_MASK (0xfUL << REGION_SHIFT)
93 #define REGION_ID(ea) (((unsigned long)(ea)) >> REGION_SHIFT)
95 #define VMALLOC_REGION_ID (REGION_ID(VMALLOC_START))
96 #define KERNEL_REGION_ID (REGION_ID(PAGE_OFFSET))
97 #define VMEMMAP_REGION_ID (0xfUL) /* Server only */
98 #define USER_REGION_ID (0UL)
101 * Defines the address of the vmemap area, in its own region on
104 #define VMEMMAP_BASE (VMEMMAP_REGION_ID << REGION_SHIFT)
106 #ifdef CONFIG_PPC_MM_SLICES
107 #define HAVE_ARCH_UNMAPPED_AREA
108 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
109 #endif /* CONFIG_PPC_MM_SLICES */
111 /* No separate kernel read-only */
112 #define _PAGE_KERNEL_RW (_PAGE_RW | _PAGE_DIRTY) /* user access blocked by key */
113 #define _PAGE_KERNEL_RO _PAGE_KERNEL_RW
114 #define _PAGE_KERNEL_RWX (_PAGE_DIRTY | _PAGE_RW | _PAGE_EXEC)
116 /* Strong Access Ordering */
117 #define _PAGE_SAO (_PAGE_WRITETHRU | _PAGE_NO_CACHE | _PAGE_COHERENT)
119 /* No page size encoding in the linux PTE */
120 #define _PAGE_PSIZE 0
123 #define _PTEIDX_SECONDARY 0x8
124 #define _PTEIDX_GROUP_IX 0x7
126 /* Hash table based platforms need atomic updates of the linux PTE */
127 #define PTE_ATOMIC_UPDATES 1
128 #define _PTE_NONE_MASK _PAGE_HPTEFLAGS
130 * The mask convered by the RPN must be a ULL on 32-bit platforms with
133 #define PTE_RPN_MASK (~((1UL << PTE_RPN_SHIFT) - 1))
135 * _PAGE_CHG_MASK masks of bits that are to be preserved across
138 #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
139 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE)
141 * Mask of bits returned by pte_pgprot()
143 #define PAGE_PROT_BITS (_PAGE_GUARDED | _PAGE_COHERENT | _PAGE_NO_CACHE | \
144 _PAGE_WRITETHRU | _PAGE_4K_PFN | \
145 _PAGE_USER | _PAGE_ACCESSED | \
146 _PAGE_RW | _PAGE_DIRTY | _PAGE_EXEC)
148 * We define 2 sets of base prot bits, one for basic pages (ie,
149 * cacheable kernel and user pages) and one for non cacheable
150 * pages. We always set _PAGE_COHERENT when SMP is enabled or
151 * the processor might need it for DMA coherency.
153 #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE)
154 #define _PAGE_BASE (_PAGE_BASE_NC | _PAGE_COHERENT)
156 /* Permission masks used to generate the __P and __S table,
158 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h
160 * Write permissions imply read permissions for now (we could make write-only
161 * pages on BookE but we don't bother for now). Execute permission control is
162 * possible on platforms that define _PAGE_EXEC
164 * Note due to the way vm flags are laid out, the bits are XWR
166 #define PAGE_NONE __pgprot(_PAGE_BASE)
167 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
168 #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | \
170 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER )
171 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
172 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER )
173 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
175 #define __P000 PAGE_NONE
176 #define __P001 PAGE_READONLY
177 #define __P010 PAGE_COPY
178 #define __P011 PAGE_COPY
179 #define __P100 PAGE_READONLY_X
180 #define __P101 PAGE_READONLY_X
181 #define __P110 PAGE_COPY_X
182 #define __P111 PAGE_COPY_X
184 #define __S000 PAGE_NONE
185 #define __S001 PAGE_READONLY
186 #define __S010 PAGE_SHARED
187 #define __S011 PAGE_SHARED
188 #define __S100 PAGE_READONLY_X
189 #define __S101 PAGE_READONLY_X
190 #define __S110 PAGE_SHARED_X
191 #define __S111 PAGE_SHARED_X
193 /* Permission masks used for kernel mappings */
194 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW)
195 #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
197 #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
198 _PAGE_NO_CACHE | _PAGE_GUARDED)
199 #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX)
200 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO)
201 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX)
203 /* Protection used for kernel text. We want the debuggers to be able to
204 * set breakpoints anywhere, so don't write protect the kernel text
205 * on platforms where such control is possible.
207 #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) ||\
208 defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE)
209 #define PAGE_KERNEL_TEXT PAGE_KERNEL_X
211 #define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX
214 /* Make modules code happy. We don't set RO yet */
215 #define PAGE_KERNEL_EXEC PAGE_KERNEL_X
216 #define PAGE_AGP (PAGE_KERNEL_NC)
218 #define PMD_BAD_BITS (PTE_TABLE_SIZE-1)
219 #define PUD_BAD_BITS (PMD_TABLE_SIZE-1)
222 #define pmd_bad(pmd) (!is_kernel_addr(pmd_val(pmd)) \
223 || (pmd_val(pmd) & PMD_BAD_BITS))
224 #define pmd_page_vaddr(pmd) (pmd_val(pmd) & ~PMD_MASKED_BITS)
226 #define pud_bad(pud) (!is_kernel_addr(pud_val(pud)) \
227 || (pud_val(pud) & PUD_BAD_BITS))
228 #define pud_page_vaddr(pud) (pud_val(pud) & ~PUD_MASKED_BITS)
230 #define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & (PTRS_PER_PGD - 1))
231 #define pmd_index(address) (((address) >> (PMD_SHIFT)) & (PTRS_PER_PMD - 1))
232 #define pte_index(address) (((address) >> (PAGE_SHIFT)) & (PTRS_PER_PTE - 1))
234 extern void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
235 pte_t *ptep, unsigned long pte, int huge);
236 extern unsigned long htab_convert_pte_flags(unsigned long pteflags);
237 /* Atomic PTE updates */
238 static inline unsigned long pte_update(struct mm_struct *mm,
240 pte_t *ptep, unsigned long clr,
244 unsigned long old, tmp;
246 __asm__ __volatile__(
247 "1: ldarx %0,0,%3 # pte_update\n\
254 : "=&r" (old), "=&r" (tmp), "=m" (*ptep)
255 : "r" (ptep), "r" (clr), "m" (*ptep), "i" (_PAGE_BUSY), "r" (set)
257 /* huge pages use the old page table lock */
259 assert_pte_locked(mm, addr);
261 if (old & _PAGE_HASHPTE)
262 hpte_need_flush(mm, addr, ptep, old, huge);
267 static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
268 unsigned long addr, pte_t *ptep)
272 if ((pte_val(*ptep) & (_PAGE_ACCESSED | _PAGE_HASHPTE)) == 0)
274 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0);
275 return (old & _PAGE_ACCESSED) != 0;
277 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
278 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \
281 __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \
285 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
286 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
290 if ((pte_val(*ptep) & _PAGE_RW) == 0)
293 pte_update(mm, addr, ptep, _PAGE_RW, 0, 0);
296 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
297 unsigned long addr, pte_t *ptep)
299 if ((pte_val(*ptep) & _PAGE_RW) == 0)
302 pte_update(mm, addr, ptep, _PAGE_RW, 0, 1);
306 * We currently remove entries from the hashtable regardless of whether
307 * the entry was young or dirty. The generic routines only flush if the
308 * entry was young or dirty which is not good enough.
310 * We should be more intelligent about this but for the moment we override
311 * these functions and force a tlb flush unconditionally
313 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
314 #define ptep_clear_flush_young(__vma, __address, __ptep) \
316 int __young = __ptep_test_and_clear_young((__vma)->vm_mm, __address, \
321 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
322 static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
323 unsigned long addr, pte_t *ptep)
325 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0);
329 static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
332 pte_update(mm, addr, ptep, ~0UL, 0, 0);
336 /* Set the dirty and/or accessed bits atomically in a linux PTE, this
337 * function doesn't need to flush the hash entry
339 static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry)
341 unsigned long bits = pte_val(entry) &
342 (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC);
344 unsigned long old, tmp;
346 __asm__ __volatile__(
353 :"=&r" (old), "=&r" (tmp), "=m" (*ptep)
354 :"r" (bits), "r" (ptep), "m" (*ptep), "i" (_PAGE_BUSY)
358 #define __HAVE_ARCH_PTE_SAME
359 #define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HPTEFLAGS) == 0)
361 /* Generic accessors to PTE bits */
362 static inline int pte_write(pte_t pte) { return !!(pte_val(pte) & _PAGE_RW);}
363 static inline int pte_dirty(pte_t pte) { return !!(pte_val(pte) & _PAGE_DIRTY); }
364 static inline int pte_young(pte_t pte) { return !!(pte_val(pte) & _PAGE_ACCESSED); }
365 static inline int pte_special(pte_t pte) { return !!(pte_val(pte) & _PAGE_SPECIAL); }
366 static inline int pte_none(pte_t pte) { return (pte_val(pte) & ~_PTE_NONE_MASK) == 0; }
367 static inline pgprot_t pte_pgprot(pte_t pte) { return __pgprot(pte_val(pte) & PAGE_PROT_BITS); }
369 #ifdef CONFIG_NUMA_BALANCING
371 * These work without NUMA balancing but the kernel does not care. See the
372 * comment in include/asm-generic/pgtable.h . On powerpc, this will only
373 * work for user pages and always return true for kernel pages.
375 static inline int pte_protnone(pte_t pte)
377 return (pte_val(pte) &
378 (_PAGE_PRESENT | _PAGE_USER)) == _PAGE_PRESENT;
380 #endif /* CONFIG_NUMA_BALANCING */
382 static inline int pte_present(pte_t pte)
384 return pte_val(pte) & _PAGE_PRESENT;
387 /* Conversion functions: convert a page and protection to a page entry,
388 * and a page entry and page directory to the page they refer to.
390 * Even if PTEs can be unsigned long long, a PFN is always an unsigned
393 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
395 return __pte(((pte_basic_t)(pfn) << PTE_RPN_SHIFT) |
399 static inline unsigned long pte_pfn(pte_t pte)
401 return pte_val(pte) >> PTE_RPN_SHIFT;
404 /* Generic modifiers for PTE bits */
405 static inline pte_t pte_wrprotect(pte_t pte)
407 return __pte(pte_val(pte) & ~_PAGE_RW);
410 static inline pte_t pte_mkclean(pte_t pte)
412 return __pte(pte_val(pte) & ~_PAGE_DIRTY);
415 static inline pte_t pte_mkold(pte_t pte)
417 return __pte(pte_val(pte) & ~_PAGE_ACCESSED);
420 static inline pte_t pte_mkwrite(pte_t pte)
422 return __pte(pte_val(pte) | _PAGE_RW);
425 static inline pte_t pte_mkdirty(pte_t pte)
427 return __pte(pte_val(pte) | _PAGE_DIRTY);
430 static inline pte_t pte_mkyoung(pte_t pte)
432 return __pte(pte_val(pte) | _PAGE_ACCESSED);
435 static inline pte_t pte_mkspecial(pte_t pte)
437 return __pte(pte_val(pte) | _PAGE_SPECIAL);
440 static inline pte_t pte_mkhuge(pte_t pte)
445 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
447 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
450 /* This low level function performs the actual PTE insertion
451 * Setting the PTE depends on the MMU type and other factors. It's
452 * an horrible mess that I'm not going to try to clean up now but
453 * I'm keeping it in one place rather than spread around
455 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
456 pte_t *ptep, pte_t pte, int percpu)
459 * Anything else just stores the PTE normally. That covers all 64-bit
460 * cases, and 32-bit non-hash with 32-bit PTEs.
466 * Macro to mark a page protection value as "uncacheable".
469 #define _PAGE_CACHE_CTL (_PAGE_COHERENT | _PAGE_GUARDED | _PAGE_NO_CACHE | \
472 #define pgprot_noncached pgprot_noncached
473 static inline pgprot_t pgprot_noncached(pgprot_t prot)
475 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
476 _PAGE_NO_CACHE | _PAGE_GUARDED);
479 #define pgprot_noncached_wc pgprot_noncached_wc
480 static inline pgprot_t pgprot_noncached_wc(pgprot_t prot)
482 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
486 #define pgprot_cached pgprot_cached
487 static inline pgprot_t pgprot_cached(pgprot_t prot)
489 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
493 #define pgprot_cached_wthru pgprot_cached_wthru
494 static inline pgprot_t pgprot_cached_wthru(pgprot_t prot)
496 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
497 _PAGE_COHERENT | _PAGE_WRITETHRU);
500 #define pgprot_cached_noncoherent pgprot_cached_noncoherent
501 static inline pgprot_t pgprot_cached_noncoherent(pgprot_t prot)
503 return __pgprot(pgprot_val(prot) & ~_PAGE_CACHE_CTL);
506 #define pgprot_writecombine pgprot_writecombine
507 static inline pgprot_t pgprot_writecombine(pgprot_t prot)
509 return pgprot_noncached_wc(prot);
512 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
513 extern void hpte_do_hugepage_flush(struct mm_struct *mm, unsigned long addr,
514 pmd_t *pmdp, unsigned long old_pmd);
516 static inline void hpte_do_hugepage_flush(struct mm_struct *mm,
517 unsigned long addr, pmd_t *pmdp,
518 unsigned long old_pmd)
520 WARN(1, "%s called with THP disabled\n", __func__);
522 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
524 #endif /* !__ASSEMBLY__ */
525 #endif /* __KERNEL__ */
526 #endif /* _ASM_POWERPC_BOOK3S_64_HASH_H */