2 * MPC8641 HPCN Device Tree Source
4 * Copyright 2006 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
15 model = "MPC8641HPCN";
16 compatible = "fsl,mpc8641hpcn";
30 * Only one of Rapid IO or PCI can be present due to HW limitations and
31 * due to the fact that the 2 now share address space in the new memory
32 * map. The most likely case is that we have PCI, so comment out the
33 * rapidio node. Leave it here for reference.
35 /* rapidio0 = &rapidio0; */
45 d-cache-line-size = <32>;
46 i-cache-line-size = <32>;
47 d-cache-size = <32768>; // L1
48 i-cache-size = <32768>; // L1
49 timebase-frequency = <0>; // From uboot
50 bus-frequency = <0>; // From uboot
51 clock-frequency = <0>; // From uboot
56 d-cache-line-size = <32>;
57 i-cache-line-size = <32>;
58 d-cache-size = <32768>;
59 i-cache-size = <32768>;
60 timebase-frequency = <0>; // From uboot
61 bus-frequency = <0>; // From uboot
62 clock-frequency = <0>; // From uboot
67 device_type = "memory";
68 reg = <0x00000000 0x40000000>; // 1G at 0x0
74 compatible = "fsl,mpc8641-localbus", "simple-bus";
75 reg = <0xffe05000 0x1000>;
77 interrupt-parent = <&mpic>;
79 ranges = <0 0 0xef800000 0x00800000
80 2 0 0xffdf8000 0x00008000
81 3 0 0xffdf0000 0x00008000>;
84 compatible = "cfi-flash";
85 reg = <0 0 0x00800000>;
92 reg = <0x00000000 0x00300000>;
96 reg = <0x00300000 0x00100000>;
101 reg = <0x00400000 0x00300000>;
104 label = "firmware a";
105 reg = <0x00700000 0x00100000>;
112 #address-cells = <1>;
115 compatible = "simple-bus";
116 ranges = <0x00000000 0xffe00000 0x00100000>;
117 reg = <0xffe00000 0x00001000>; // CCSRBAR
121 #address-cells = <1>;
124 compatible = "fsl-i2c";
125 reg = <0x3000 0x100>;
127 interrupt-parent = <&mpic>;
132 #address-cells = <1>;
135 compatible = "fsl-i2c";
136 reg = <0x3100 0x100>;
138 interrupt-parent = <&mpic>;
143 #address-cells = <1>;
145 compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
147 ranges = <0x0 0x21100 0x200>;
150 compatible = "fsl,mpc8641-dma-channel",
151 "fsl,eloplus-dma-channel";
154 interrupt-parent = <&mpic>;
158 compatible = "fsl,mpc8641-dma-channel",
159 "fsl,eloplus-dma-channel";
162 interrupt-parent = <&mpic>;
166 compatible = "fsl,mpc8641-dma-channel",
167 "fsl,eloplus-dma-channel";
170 interrupt-parent = <&mpic>;
174 compatible = "fsl,mpc8641-dma-channel",
175 "fsl,eloplus-dma-channel";
178 interrupt-parent = <&mpic>;
184 #address-cells = <1>;
186 compatible = "fsl,gianfar-mdio";
187 reg = <0x24520 0x20>;
189 phy0: ethernet-phy@0 {
190 interrupt-parent = <&mpic>;
193 device_type = "ethernet-phy";
195 phy1: ethernet-phy@1 {
196 interrupt-parent = <&mpic>;
199 device_type = "ethernet-phy";
201 phy2: ethernet-phy@2 {
202 interrupt-parent = <&mpic>;
205 device_type = "ethernet-phy";
207 phy3: ethernet-phy@3 {
208 interrupt-parent = <&mpic>;
211 device_type = "ethernet-phy";
215 enet0: ethernet@24000 {
217 device_type = "network";
219 compatible = "gianfar";
220 reg = <0x24000 0x1000>;
221 local-mac-address = [ 00 00 00 00 00 00 ];
222 interrupts = <29 2 30 2 34 2>;
223 interrupt-parent = <&mpic>;
224 phy-handle = <&phy0>;
225 phy-connection-type = "rgmii-id";
228 enet1: ethernet@25000 {
230 device_type = "network";
232 compatible = "gianfar";
233 reg = <0x25000 0x1000>;
234 local-mac-address = [ 00 00 00 00 00 00 ];
235 interrupts = <35 2 36 2 40 2>;
236 interrupt-parent = <&mpic>;
237 phy-handle = <&phy1>;
238 phy-connection-type = "rgmii-id";
241 enet2: ethernet@26000 {
243 device_type = "network";
245 compatible = "gianfar";
246 reg = <0x26000 0x1000>;
247 local-mac-address = [ 00 00 00 00 00 00 ];
248 interrupts = <31 2 32 2 33 2>;
249 interrupt-parent = <&mpic>;
250 phy-handle = <&phy2>;
251 phy-connection-type = "rgmii-id";
254 enet3: ethernet@27000 {
256 device_type = "network";
258 compatible = "gianfar";
259 reg = <0x27000 0x1000>;
260 local-mac-address = [ 00 00 00 00 00 00 ];
261 interrupts = <37 2 38 2 39 2>;
262 interrupt-parent = <&mpic>;
263 phy-handle = <&phy3>;
264 phy-connection-type = "rgmii-id";
267 serial0: serial@4500 {
269 device_type = "serial";
270 compatible = "ns16550";
271 reg = <0x4500 0x100>;
272 clock-frequency = <0>;
274 interrupt-parent = <&mpic>;
277 serial1: serial@4600 {
279 device_type = "serial";
280 compatible = "ns16550";
281 reg = <0x4600 0x100>;
282 clock-frequency = <0>;
284 interrupt-parent = <&mpic>;
288 interrupt-controller;
289 #address-cells = <0>;
290 #interrupt-cells = <2>;
291 reg = <0x40000 0x40000>;
292 compatible = "chrp,open-pic";
293 device_type = "open-pic";
296 global-utilities@e0000 {
297 compatible = "fsl,mpc8641-guts";
298 reg = <0xe0000 0x1000>;
303 pci0: pcie@ffe08000 {
305 compatible = "fsl,mpc8641-pcie";
307 #interrupt-cells = <1>;
309 #address-cells = <3>;
310 reg = <0xffe08000 0x1000>;
311 bus-range = <0x0 0xff>;
312 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
313 0x01000000 0x0 0x00000000 0xffc00000 0x0 0x00010000>;
314 clock-frequency = <33333333>;
315 interrupt-parent = <&mpic>;
317 interrupt-map-mask = <0xff00 0 0 7>;
319 /* IDSEL 0x11 func 0 - PCI slot 1 */
320 0x8800 0 0 1 &mpic 2 1
321 0x8800 0 0 2 &mpic 3 1
322 0x8800 0 0 3 &mpic 4 1
323 0x8800 0 0 4 &mpic 1 1
325 /* IDSEL 0x11 func 1 - PCI slot 1 */
326 0x8900 0 0 1 &mpic 2 1
327 0x8900 0 0 2 &mpic 3 1
328 0x8900 0 0 3 &mpic 4 1
329 0x8900 0 0 4 &mpic 1 1
331 /* IDSEL 0x11 func 2 - PCI slot 1 */
332 0x8a00 0 0 1 &mpic 2 1
333 0x8a00 0 0 2 &mpic 3 1
334 0x8a00 0 0 3 &mpic 4 1
335 0x8a00 0 0 4 &mpic 1 1
337 /* IDSEL 0x11 func 3 - PCI slot 1 */
338 0x8b00 0 0 1 &mpic 2 1
339 0x8b00 0 0 2 &mpic 3 1
340 0x8b00 0 0 3 &mpic 4 1
341 0x8b00 0 0 4 &mpic 1 1
343 /* IDSEL 0x11 func 4 - PCI slot 1 */
344 0x8c00 0 0 1 &mpic 2 1
345 0x8c00 0 0 2 &mpic 3 1
346 0x8c00 0 0 3 &mpic 4 1
347 0x8c00 0 0 4 &mpic 1 1
349 /* IDSEL 0x11 func 5 - PCI slot 1 */
350 0x8d00 0 0 1 &mpic 2 1
351 0x8d00 0 0 2 &mpic 3 1
352 0x8d00 0 0 3 &mpic 4 1
353 0x8d00 0 0 4 &mpic 1 1
355 /* IDSEL 0x11 func 6 - PCI slot 1 */
356 0x8e00 0 0 1 &mpic 2 1
357 0x8e00 0 0 2 &mpic 3 1
358 0x8e00 0 0 3 &mpic 4 1
359 0x8e00 0 0 4 &mpic 1 1
361 /* IDSEL 0x11 func 7 - PCI slot 1 */
362 0x8f00 0 0 1 &mpic 2 1
363 0x8f00 0 0 2 &mpic 3 1
364 0x8f00 0 0 3 &mpic 4 1
365 0x8f00 0 0 4 &mpic 1 1
367 /* IDSEL 0x12 func 0 - PCI slot 2 */
368 0x9000 0 0 1 &mpic 3 1
369 0x9000 0 0 2 &mpic 4 1
370 0x9000 0 0 3 &mpic 1 1
371 0x9000 0 0 4 &mpic 2 1
373 /* IDSEL 0x12 func 1 - PCI slot 2 */
374 0x9100 0 0 1 &mpic 3 1
375 0x9100 0 0 2 &mpic 4 1
376 0x9100 0 0 3 &mpic 1 1
377 0x9100 0 0 4 &mpic 2 1
379 /* IDSEL 0x12 func 2 - PCI slot 2 */
380 0x9200 0 0 1 &mpic 3 1
381 0x9200 0 0 2 &mpic 4 1
382 0x9200 0 0 3 &mpic 1 1
383 0x9200 0 0 4 &mpic 2 1
385 /* IDSEL 0x12 func 3 - PCI slot 2 */
386 0x9300 0 0 1 &mpic 3 1
387 0x9300 0 0 2 &mpic 4 1
388 0x9300 0 0 3 &mpic 1 1
389 0x9300 0 0 4 &mpic 2 1
391 /* IDSEL 0x12 func 4 - PCI slot 2 */
392 0x9400 0 0 1 &mpic 3 1
393 0x9400 0 0 2 &mpic 4 1
394 0x9400 0 0 3 &mpic 1 1
395 0x9400 0 0 4 &mpic 2 1
397 /* IDSEL 0x12 func 5 - PCI slot 2 */
398 0x9500 0 0 1 &mpic 3 1
399 0x9500 0 0 2 &mpic 4 1
400 0x9500 0 0 3 &mpic 1 1
401 0x9500 0 0 4 &mpic 2 1
403 /* IDSEL 0x12 func 6 - PCI slot 2 */
404 0x9600 0 0 1 &mpic 3 1
405 0x9600 0 0 2 &mpic 4 1
406 0x9600 0 0 3 &mpic 1 1
407 0x9600 0 0 4 &mpic 2 1
409 /* IDSEL 0x12 func 7 - PCI slot 2 */
410 0x9700 0 0 1 &mpic 3 1
411 0x9700 0 0 2 &mpic 4 1
412 0x9700 0 0 3 &mpic 1 1
413 0x9700 0 0 4 &mpic 2 1
416 0xe000 0 0 1 &i8259 12 2
417 0xe100 0 0 2 &i8259 9 2
418 0xe200 0 0 3 &i8259 10 2
419 0xe300 0 0 4 &i8259 11 2
422 0xe800 0 0 1 &i8259 6 2
425 0xf000 0 0 1 &i8259 7 2
426 0xf100 0 0 1 &i8259 7 2
428 // IDSEL 0x1f IDE/SATA
429 0xf800 0 0 1 &i8259 14 2
430 0xf900 0 0 1 &i8259 5 2
436 #address-cells = <3>;
438 ranges = <0x02000000 0x0 0x80000000
439 0x02000000 0x0 0x80000000
442 0x01000000 0x0 0x00000000
443 0x01000000 0x0 0x00000000
448 #address-cells = <3>;
449 ranges = <0x02000000 0x0 0x80000000
450 0x02000000 0x0 0x80000000
452 0x01000000 0x0 0x00000000
453 0x01000000 0x0 0x00000000
457 #interrupt-cells = <2>;
459 #address-cells = <2>;
460 reg = <0xf000 0 0 0 0>;
461 ranges = <1 0 0x01000000 0 0
463 interrupt-parent = <&i8259>;
465 i8259: interrupt-controller@20 {
469 interrupt-controller;
470 device_type = "interrupt-controller";
471 #address-cells = <0>;
472 #interrupt-cells = <2>;
473 compatible = "chrp,iic";
475 interrupt-parent = <&mpic>;
480 #address-cells = <1>;
481 reg = <1 0x60 1 1 0x64 1>;
482 interrupts = <1 3 12 3>;
488 compatible = "pnpPNP,303";
493 compatible = "pnpPNP,f03";
504 reg = <1 0x400 0x80>;
512 pci1: pcie@ffe09000 {
514 compatible = "fsl,mpc8641-pcie";
516 #interrupt-cells = <1>;
518 #address-cells = <3>;
519 reg = <0xffe09000 0x1000>;
520 bus-range = <0 0xff>;
521 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
522 0x01000000 0x0 0x00000000 0xffc10000 0x0 0x00010000>;
523 clock-frequency = <33333333>;
524 interrupt-parent = <&mpic>;
526 interrupt-map-mask = <0xf800 0 0 7>;
529 0x0000 0 0 1 &mpic 4 1
530 0x0000 0 0 2 &mpic 5 1
531 0x0000 0 0 3 &mpic 6 1
532 0x0000 0 0 4 &mpic 7 1
537 #address-cells = <3>;
539 ranges = <0x02000000 0x0 0xa0000000
540 0x02000000 0x0 0xa0000000
543 0x01000000 0x0 0x00000000
544 0x01000000 0x0 0x00000000
549 rapidio0: rapidio@ffec0000 {
550 #address-cells = <2>;
552 compatible = "fsl,rapidio-delta";
553 reg = <0xffec0000 0x20000>;
554 ranges = <0 0 0x80000000 0 0x20000000>;
555 interrupt-parent = <&mpic>;
556 // err_irq bell_outb_irq bell_inb_irq
557 // msg1_tx_irq msg1_rx_irq msg2_tx_irq msg2_rx_irq
558 interrupts = <48 2 49 2 50 2 53 2 54 2 55 2 56 2>;