2 * MPC8572 DS Device Tree Source
4 * Copyright 2007, 2008 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
14 model = "fsl,MPC8572DS";
15 compatible = "fsl,MPC8572DS";
38 d-cache-line-size = <32>; // 32 bytes
39 i-cache-line-size = <32>; // 32 bytes
40 d-cache-size = <0x8000>; // L1, 32K
41 i-cache-size = <0x8000>; // L1, 32K
42 timebase-frequency = <0>;
44 clock-frequency = <0>;
45 next-level-cache = <&L2>;
51 d-cache-line-size = <32>; // 32 bytes
52 i-cache-line-size = <32>; // 32 bytes
53 d-cache-size = <0x8000>; // L1, 32K
54 i-cache-size = <0x8000>; // L1, 32K
55 timebase-frequency = <0>;
57 clock-frequency = <0>;
58 next-level-cache = <&L2>;
63 device_type = "memory";
69 compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
70 reg = <0 0xffe05000 0 0x1000>;
72 interrupt-parent = <&mpic>;
74 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
75 0x1 0x0 0x0 0xe0000000 0x08000000
76 0x2 0x0 0x0 0xffa00000 0x00040000
77 0x3 0x0 0x0 0xffdf0000 0x00008000
78 0x4 0x0 0x0 0xffa40000 0x00040000
79 0x5 0x0 0x0 0xffa80000 0x00040000
80 0x6 0x0 0x0 0xffac0000 0x00040000>;
85 compatible = "cfi-flash";
86 reg = <0x0 0x0 0x8000000>;
91 reg = <0x0 0x03000000>;
96 reg = <0x03000000 0x00e00000>;
101 reg = <0x03e00000 0x00200000>;
106 reg = <0x04000000 0x00400000>;
111 reg = <0x04400000 0x03b00000>;
115 reg = <0x07f00000 0x00080000>;
120 reg = <0x07f80000 0x00080000>;
126 #address-cells = <1>;
128 compatible = "fsl,mpc8572-fcm-nand",
130 reg = <0x2 0x0 0x40000>;
133 reg = <0x0 0x02000000>;
138 reg = <0x02000000 0x10000000>;
142 reg = <0x12000000 0x08000000>;
147 reg = <0x1a000000 0x04000000>;
151 reg = <0x1e000000 0x01000000>;
156 reg = <0x1f000000 0x21000000>;
161 compatible = "fsl,mpc8572-fcm-nand",
163 reg = <0x4 0x0 0x40000>;
167 compatible = "fsl,mpc8572-fcm-nand",
169 reg = <0x5 0x0 0x40000>;
173 compatible = "fsl,mpc8572-fcm-nand",
175 reg = <0x6 0x0 0x40000>;
180 #address-cells = <1>;
183 compatible = "simple-bus";
184 ranges = <0x0 0 0xffe00000 0x100000>;
185 reg = <0 0xffe00000 0 0x1000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed
186 bus-frequency = <0>; // Filled out by uboot.
188 memory-controller@2000 {
189 compatible = "fsl,mpc8572-memory-controller";
190 reg = <0x2000 0x1000>;
191 interrupt-parent = <&mpic>;
195 memory-controller@6000 {
196 compatible = "fsl,mpc8572-memory-controller";
197 reg = <0x6000 0x1000>;
198 interrupt-parent = <&mpic>;
202 L2: l2-cache-controller@20000 {
203 compatible = "fsl,mpc8572-l2-cache-controller";
204 reg = <0x20000 0x1000>;
205 cache-line-size = <32>; // 32 bytes
206 cache-size = <0x100000>; // L2, 1M
207 interrupt-parent = <&mpic>;
212 #address-cells = <1>;
215 compatible = "fsl-i2c";
216 reg = <0x3000 0x100>;
218 interrupt-parent = <&mpic>;
223 #address-cells = <1>;
226 compatible = "fsl-i2c";
227 reg = <0x3100 0x100>;
229 interrupt-parent = <&mpic>;
234 #address-cells = <1>;
236 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
238 ranges = <0x0 0xc100 0x200>;
241 compatible = "fsl,mpc8572-dma-channel",
242 "fsl,eloplus-dma-channel";
245 interrupt-parent = <&mpic>;
249 compatible = "fsl,mpc8572-dma-channel",
250 "fsl,eloplus-dma-channel";
253 interrupt-parent = <&mpic>;
257 compatible = "fsl,mpc8572-dma-channel",
258 "fsl,eloplus-dma-channel";
261 interrupt-parent = <&mpic>;
265 compatible = "fsl,mpc8572-dma-channel",
266 "fsl,eloplus-dma-channel";
269 interrupt-parent = <&mpic>;
275 #address-cells = <1>;
277 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
279 ranges = <0x0 0x21100 0x200>;
282 compatible = "fsl,mpc8572-dma-channel",
283 "fsl,eloplus-dma-channel";
286 interrupt-parent = <&mpic>;
290 compatible = "fsl,mpc8572-dma-channel",
291 "fsl,eloplus-dma-channel";
294 interrupt-parent = <&mpic>;
298 compatible = "fsl,mpc8572-dma-channel",
299 "fsl,eloplus-dma-channel";
302 interrupt-parent = <&mpic>;
306 compatible = "fsl,mpc8572-dma-channel",
307 "fsl,eloplus-dma-channel";
310 interrupt-parent = <&mpic>;
316 #address-cells = <1>;
318 compatible = "fsl,gianfar-mdio";
319 reg = <0x24520 0x20>;
321 phy0: ethernet-phy@0 {
322 interrupt-parent = <&mpic>;
326 phy1: ethernet-phy@1 {
327 interrupt-parent = <&mpic>;
331 phy2: ethernet-phy@2 {
332 interrupt-parent = <&mpic>;
336 phy3: ethernet-phy@3 {
337 interrupt-parent = <&mpic>;
343 enet0: ethernet@24000 {
345 device_type = "network";
347 compatible = "gianfar";
348 reg = <0x24000 0x1000>;
349 local-mac-address = [ 00 00 00 00 00 00 ];
350 interrupts = <29 2 30 2 34 2>;
351 interrupt-parent = <&mpic>;
352 phy-handle = <&phy0>;
353 phy-connection-type = "rgmii-id";
356 enet1: ethernet@25000 {
358 device_type = "network";
360 compatible = "gianfar";
361 reg = <0x25000 0x1000>;
362 local-mac-address = [ 00 00 00 00 00 00 ];
363 interrupts = <35 2 36 2 40 2>;
364 interrupt-parent = <&mpic>;
365 phy-handle = <&phy1>;
366 phy-connection-type = "rgmii-id";
369 enet2: ethernet@26000 {
371 device_type = "network";
373 compatible = "gianfar";
374 reg = <0x26000 0x1000>;
375 local-mac-address = [ 00 00 00 00 00 00 ];
376 interrupts = <31 2 32 2 33 2>;
377 interrupt-parent = <&mpic>;
378 phy-handle = <&phy2>;
379 phy-connection-type = "rgmii-id";
382 enet3: ethernet@27000 {
384 device_type = "network";
386 compatible = "gianfar";
387 reg = <0x27000 0x1000>;
388 local-mac-address = [ 00 00 00 00 00 00 ];
389 interrupts = <37 2 38 2 39 2>;
390 interrupt-parent = <&mpic>;
391 phy-handle = <&phy3>;
392 phy-connection-type = "rgmii-id";
395 serial0: serial@4500 {
397 device_type = "serial";
398 compatible = "ns16550";
399 reg = <0x4500 0x100>;
400 clock-frequency = <0>;
402 interrupt-parent = <&mpic>;
405 serial1: serial@4600 {
407 device_type = "serial";
408 compatible = "ns16550";
409 reg = <0x4600 0x100>;
410 clock-frequency = <0>;
412 interrupt-parent = <&mpic>;
415 global-utilities@e0000 { //global utilities block
416 compatible = "fsl,mpc8572-guts";
417 reg = <0xe0000 0x1000>;
422 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
423 reg = <0x41600 0x80>;
424 msi-available-ranges = <0 0x100>;
434 interrupt-parent = <&mpic>;
438 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
439 "fsl,sec2.1", "fsl,sec2.0";
440 reg = <0x30000 0x10000>;
441 interrupts = <45 2 58 2>;
442 interrupt-parent = <&mpic>;
443 fsl,num-channels = <4>;
444 fsl,channel-fifo-len = <24>;
445 fsl,exec-units-mask = <0x9fe>;
446 fsl,descriptor-types-mask = <0x3ab0ebf>;
450 interrupt-controller;
451 #address-cells = <0>;
452 #interrupt-cells = <2>;
453 reg = <0x40000 0x40000>;
454 compatible = "chrp,open-pic";
455 device_type = "open-pic";
459 pci0: pcie@ffe08000 {
461 compatible = "fsl,mpc8548-pcie";
463 #interrupt-cells = <1>;
465 #address-cells = <3>;
466 reg = <0 0xffe08000 0 0x1000>;
468 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
469 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x00010000>;
470 clock-frequency = <33333333>;
471 interrupt-parent = <&mpic>;
473 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
475 /* IDSEL 0x11 func 0 - PCI slot 1 */
476 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
477 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
478 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
479 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
481 /* IDSEL 0x11 func 1 - PCI slot 1 */
482 0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
483 0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
484 0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
485 0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
487 /* IDSEL 0x11 func 2 - PCI slot 1 */
488 0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
489 0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
490 0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
491 0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
493 /* IDSEL 0x11 func 3 - PCI slot 1 */
494 0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
495 0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
496 0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
497 0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
499 /* IDSEL 0x11 func 4 - PCI slot 1 */
500 0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
501 0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
502 0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
503 0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
505 /* IDSEL 0x11 func 5 - PCI slot 1 */
506 0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
507 0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
508 0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
509 0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
511 /* IDSEL 0x11 func 6 - PCI slot 1 */
512 0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
513 0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
514 0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
515 0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
517 /* IDSEL 0x11 func 7 - PCI slot 1 */
518 0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
519 0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
520 0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
521 0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
523 /* IDSEL 0x12 func 0 - PCI slot 2 */
524 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
525 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
526 0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
527 0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
529 /* IDSEL 0x12 func 1 - PCI slot 2 */
530 0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
531 0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
532 0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
533 0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
535 /* IDSEL 0x12 func 2 - PCI slot 2 */
536 0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
537 0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
538 0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
539 0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
541 /* IDSEL 0x12 func 3 - PCI slot 2 */
542 0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
543 0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
544 0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
545 0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
547 /* IDSEL 0x12 func 4 - PCI slot 2 */
548 0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
549 0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
550 0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
551 0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
553 /* IDSEL 0x12 func 5 - PCI slot 2 */
554 0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
555 0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
556 0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
557 0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
559 /* IDSEL 0x12 func 6 - PCI slot 2 */
560 0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
561 0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
562 0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
563 0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
565 /* IDSEL 0x12 func 7 - PCI slot 2 */
566 0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
567 0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
568 0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
569 0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
572 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
573 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
574 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
575 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
578 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
581 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
582 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
584 // IDSEL 0x1f IDE/SATA
585 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
586 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
591 reg = <0x0 0x0 0x0 0x0 0x0>;
593 #address-cells = <3>;
595 ranges = <0x2000000 0x0 0x80000000
596 0x2000000 0x0 0x80000000
603 reg = <0x0 0x0 0x0 0x0 0x0>;
605 #address-cells = <3>;
606 ranges = <0x2000000 0x0 0x80000000
607 0x2000000 0x0 0x80000000
615 #interrupt-cells = <2>;
617 #address-cells = <2>;
618 reg = <0xf000 0x0 0x0 0x0 0x0>;
619 ranges = <0x1 0x0 0x1000000 0x0 0x0
621 interrupt-parent = <&i8259>;
623 i8259: interrupt-controller@20 {
627 interrupt-controller;
628 device_type = "interrupt-controller";
629 #address-cells = <0>;
630 #interrupt-cells = <2>;
631 compatible = "chrp,iic";
633 interrupt-parent = <&mpic>;
638 #address-cells = <1>;
639 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
640 interrupts = <1 3 12 3>;
646 compatible = "pnpPNP,303";
651 compatible = "pnpPNP,f03";
656 compatible = "pnpPNP,b00";
657 reg = <0x1 0x70 0x2>;
661 reg = <0x1 0x400 0x80>;
669 pci1: pcie@ffe09000 {
671 compatible = "fsl,mpc8548-pcie";
673 #interrupt-cells = <1>;
675 #address-cells = <3>;
676 reg = <0 0xffe09000 0 0x1000>;
678 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
679 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x00010000>;
680 clock-frequency = <33333333>;
681 interrupt-parent = <&mpic>;
683 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
686 0000 0x0 0x0 0x1 &mpic 0x4 0x1
687 0000 0x0 0x0 0x2 &mpic 0x5 0x1
688 0000 0x0 0x0 0x3 &mpic 0x6 0x1
689 0000 0x0 0x0 0x4 &mpic 0x7 0x1
692 reg = <0x0 0x0 0x0 0x0 0x0>;
694 #address-cells = <3>;
696 ranges = <0x2000000 0x0 0xa0000000
697 0x2000000 0x0 0xa0000000
706 pci2: pcie@ffe0a000 {
708 compatible = "fsl,mpc8548-pcie";
710 #interrupt-cells = <1>;
712 #address-cells = <3>;
713 reg = <0 0xffe0a000 0 0x1000>;
715 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
716 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x00010000>;
717 clock-frequency = <33333333>;
718 interrupt-parent = <&mpic>;
720 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
723 0000 0x0 0x0 0x1 &mpic 0x0 0x1
724 0000 0x0 0x0 0x2 &mpic 0x1 0x1
725 0000 0x0 0x0 0x3 &mpic 0x2 0x1
726 0000 0x0 0x0 0x4 &mpic 0x3 0x1
729 reg = <0x0 0x0 0x0 0x0 0x0>;
731 #address-cells = <3>;
733 ranges = <0x2000000 0x0 0xc0000000
734 0x2000000 0x0 0xc0000000