2 * MPC832x RDB Device Tree Source
4 * Copyright 2007 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
13 model = "MPC8323ERDB";
14 compatible = "MPC8323ERDB", "MPC832xRDB", "MPC83xxRDB";
33 d-cache-line-size = <20>; // 32 bytes
34 i-cache-line-size = <20>; // 32 bytes
35 d-cache-size = <4000>; // L1, 16K
36 i-cache-size = <4000>; // L1, 16K
37 timebase-frequency = <0>;
39 clock-frequency = <0>;
44 device_type = "memory";
45 reg = <00000000 04000000>;
52 ranges = <0 e0000000 00100000>;
53 reg = <e0000000 00000200>;
57 device_type = "watchdog";
58 compatible = "mpc83xx_wdt";
66 compatible = "fsl-i2c";
69 interrupt-parent = <&pic>;
73 serial0: serial@4500 {
75 device_type = "serial";
76 compatible = "ns16550";
78 clock-frequency = <0>;
80 interrupt-parent = <&pic>;
83 serial1: serial@4600 {
85 device_type = "serial";
86 compatible = "ns16550";
88 clock-frequency = <0>;
90 interrupt-parent = <&pic>;
94 device_type = "crypto";
96 compatible = "talitos";
99 interrupt-parent = <&pic>;
102 channel-fifo-len = <18>;
103 exec-units-mask = <0000004c>;
104 descriptor-types-mask = <0122003f>;
108 interrupt-controller;
109 #address-cells = <0>;
110 #interrupt-cells = <2>;
112 device_type = "ipic";
117 device_type = "par_io";
122 /* port pin dir open_drain assignment has_irq */
123 3 4 3 0 2 0 /* MDIO */
124 3 5 1 0 2 0 /* MDC */
125 3 15 2 0 1 0 /* RX_CLK (CLK16) */
126 3 17 2 0 1 0 /* TX_CLK (CLK3) */
127 0 12 1 0 1 0 /* TxD0 */
128 0 13 1 0 1 0 /* TxD1 */
129 0 14 1 0 1 0 /* TxD2 */
130 0 15 1 0 1 0 /* TxD3 */
131 0 16 2 0 1 0 /* RxD0 */
132 0 17 2 0 1 0 /* RxD1 */
133 0 18 2 0 1 0 /* RxD2 */
134 0 19 2 0 1 0 /* RxD3 */
135 0 1a 2 0 1 0 /* RX_ER */
136 0 1b 1 0 1 0 /* TX_ER */
137 0 1c 2 0 1 0 /* RX_DV */
138 0 1d 2 0 1 0 /* COL */
139 0 1e 1 0 1 0 /* TX_EN */
140 0 1f 2 0 1 0>; /* CRS */
144 /* port pin dir open_drain assignment has_irq */
145 0 d 2 0 1 0 /* RX_CLK (CLK9) */
146 3 18 2 0 1 0 /* TX_CLK (CLK10) */
147 1 0 1 0 1 0 /* TxD0 */
148 1 1 1 0 1 0 /* TxD1 */
149 1 2 1 0 1 0 /* TxD2 */
150 1 3 1 0 1 0 /* TxD3 */
151 1 4 2 0 1 0 /* RxD0 */
152 1 5 2 0 1 0 /* RxD1 */
153 1 6 2 0 1 0 /* RxD2 */
154 1 7 2 0 1 0 /* RxD3 */
155 1 8 2 0 1 0 /* RX_ER */
156 1 9 1 0 1 0 /* TX_ER */
157 1 a 2 0 1 0 /* RX_DV */
158 1 b 2 0 1 0 /* COL */
159 1 c 1 0 1 0 /* TX_EN */
160 1 d 2 0 1 0>; /* CRS */
166 #address-cells = <1>;
169 compatible = "fsl,qe";
170 ranges = <0 e0100000 00100000>;
171 reg = <e0100000 480>;
173 bus-frequency = <BCD3D80>;
176 #address-cells = <1>;
178 compatible = "fsl,qe-muram", "fsl,cpm-muram";
179 ranges = <0 00010000 00004000>;
182 compatible = "fsl,qe-muram-data",
183 "fsl,cpm-muram-data";
190 compatible = "fsl,spi";
193 interrupt-parent = <&qeic>;
199 compatible = "fsl,spi";
202 interrupt-parent = <&qeic>;
207 device_type = "network";
208 compatible = "ucc_geth";
214 interrupt-parent = <&qeic>;
215 local-mac-address = [ 00 00 00 00 00 00 ];
216 rx-clock-name = "clk16";
217 tx-clock-name = "clk3";
218 phy-handle = <&phy00>;
219 pio-handle = <&ucc2pio>;
223 device_type = "network";
224 compatible = "ucc_geth";
230 interrupt-parent = <&qeic>;
231 local-mac-address = [ 00 00 00 00 00 00 ];
232 rx-clock-name = "clk9";
233 tx-clock-name = "clk10";
234 phy-handle = <&phy04>;
235 pio-handle = <&ucc3pio>;
239 #address-cells = <1>;
242 compatible = "fsl,ucc-mdio";
244 phy00:ethernet-phy@00 {
245 interrupt-parent = <&pic>;
248 device_type = "ethernet-phy";
250 phy04:ethernet-phy@04 {
251 interrupt-parent = <&pic>;
254 device_type = "ethernet-phy";
258 qeic:interrupt-controller@80 {
259 interrupt-controller;
260 compatible = "fsl,qe-ic";
261 #address-cells = <0>;
262 #interrupt-cells = <1>;
265 interrupts = <20 8 21 8>; //high:32 low:33
266 interrupt-parent = <&pic>;
272 interrupt-map-mask = <f800 0 0 7>;
274 /* IDSEL 0x10 AD16 (USB) */
277 /* IDSEL 0x11 AD17 (Mini1)*/
283 /* IDSEL 0x12 AD18 (PCI/Mini2) */
287 9000 0 0 4 &pic 11 8>;
289 interrupt-parent = <&pic>;
292 ranges = <42000000 0 80000000 80000000 0 10000000
293 02000000 0 90000000 90000000 0 10000000
294 01000000 0 d0000000 d0000000 0 04000000>;
295 clock-frequency = <0>;
296 #interrupt-cells = <1>;
298 #address-cells = <3>;
299 reg = <e0008500 100>;
300 compatible = "fsl,mpc8349-pci";