arch/parisc/kernel/unaligned.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *    Unaligned memory access handler
   4  *
   5  *    Copyright (C) 2001 Randolph Chung <tausq@debian.org>
   6  *    Copyright (C) 2022 Helge Deller <deller@gmx.de>
   7  *    Significantly tweaked by LaMont Jones <lamont@debian.org>
   8  */
   9
  10 #include <linux/sched/signal.h>
  11 #include <linux/signal.h>
  12 #include <linux/ratelimit.h>
  13 #include <linux/uaccess.h>
  14 #include <asm/hardirq.h>
  15 #include <asm/traps.h>
  16
  17 /* #define DEBUG_UNALIGNED 1 */
  18
  19 #ifdef DEBUG_UNALIGNED
  20 #define DPRINTF(fmt, args...) do { printk(KERN_DEBUG "%s:%d:%s ", __FILE__, __LINE__, __func__ ); printk(KERN_DEBUG fmt, ##args ); } while (0)
  21 #else
  22 #define DPRINTF(fmt, args...)
  23 #endif
  24
  25 #define RFMT "%#08lx"
  26
  27 /* 1111 1100 0000 0000 0001 0011 1100 0000 */
  28 #define OPCODE1(a,b,c)  ((a)<<26|(b)<<12|(c)<<6)
  29 #define OPCODE2(a,b)    ((a)<<26|(b)<<1)
  30 #define OPCODE3(a,b)    ((a)<<26|(b)<<2)
  31 #define OPCODE4(a)      ((a)<<26)
  32 #define OPCODE1_MASK    OPCODE1(0x3f,1,0xf)
  33 #define OPCODE2_MASK    OPCODE2(0x3f,1)
  34 #define OPCODE3_MASK    OPCODE3(0x3f,1)
  35 #define OPCODE4_MASK    OPCODE4(0x3f)
  36
  37 /* skip LDB - never unaligned (index) */
  38 #define OPCODE_LDH_I    OPCODE1(0x03,0,0x1)
  39 #define OPCODE_LDW_I    OPCODE1(0x03,0,0x2)
  40 #define OPCODE_LDD_I    OPCODE1(0x03,0,0x3)
  41 #define OPCODE_LDDA_I   OPCODE1(0x03,0,0x4)
  42 #define OPCODE_LDCD_I   OPCODE1(0x03,0,0x5)
  43 #define OPCODE_LDWA_I   OPCODE1(0x03,0,0x6)
  44 #define OPCODE_LDCW_I   OPCODE1(0x03,0,0x7)
  45 /* skip LDB - never unaligned (short) */
  46 #define OPCODE_LDH_S    OPCODE1(0x03,1,0x1)
  47 #define OPCODE_LDW_S    OPCODE1(0x03,1,0x2)
  48 #define OPCODE_LDD_S    OPCODE1(0x03,1,0x3)
  49 #define OPCODE_LDDA_S   OPCODE1(0x03,1,0x4)
  50 #define OPCODE_LDCD_S   OPCODE1(0x03,1,0x5)
  51 #define OPCODE_LDWA_S   OPCODE1(0x03,1,0x6)
  52 #define OPCODE_LDCW_S   OPCODE1(0x03,1,0x7)
  53 /* skip STB - never unaligned */
  54 #define OPCODE_STH      OPCODE1(0x03,1,0x9)
  55 #define OPCODE_STW      OPCODE1(0x03,1,0xa)
  56 #define OPCODE_STD      OPCODE1(0x03,1,0xb)
  57 /* skip STBY - never unaligned */
  58 /* skip STDBY - never unaligned */
  59 #define OPCODE_STWA     OPCODE1(0x03,1,0xe)
  60 #define OPCODE_STDA     OPCODE1(0x03,1,0xf)
  61
  62 #define OPCODE_FLDWX    OPCODE1(0x09,0,0x0)
  63 #define OPCODE_FLDWXR   OPCODE1(0x09,0,0x1)
  64 #define OPCODE_FSTWX    OPCODE1(0x09,0,0x8)
  65 #define OPCODE_FSTWXR   OPCODE1(0x09,0,0x9)
  66 #define OPCODE_FLDWS    OPCODE1(0x09,1,0x0)
  67 #define OPCODE_FLDWSR   OPCODE1(0x09,1,0x1)
  68 #define OPCODE_FSTWS    OPCODE1(0x09,1,0x8)
  69 #define OPCODE_FSTWSR   OPCODE1(0x09,1,0x9)
  70 #define OPCODE_FLDDX    OPCODE1(0x0b,0,0x0)
  71 #define OPCODE_FSTDX    OPCODE1(0x0b,0,0x8)
  72 #define OPCODE_FLDDS    OPCODE1(0x0b,1,0x0)
  73 #define OPCODE_FSTDS    OPCODE1(0x0b,1,0x8)
  74
  75 #define OPCODE_LDD_L    OPCODE2(0x14,0)
  76 #define OPCODE_FLDD_L   OPCODE2(0x14,1)
  77 #define OPCODE_STD_L    OPCODE2(0x1c,0)
  78 #define OPCODE_FSTD_L   OPCODE2(0x1c,1)
  79
  80 #define OPCODE_LDW_M    OPCODE3(0x17,1)
  81 #define OPCODE_FLDW_L   OPCODE3(0x17,0)
  82 #define OPCODE_FSTW_L   OPCODE3(0x1f,0)
  83 #define OPCODE_STW_M    OPCODE3(0x1f,1)
  84
  85 #define OPCODE_LDH_L    OPCODE4(0x11)
  86 #define OPCODE_LDW_L    OPCODE4(0x12)
  87 #define OPCODE_LDWM     OPCODE4(0x13)
  88 #define OPCODE_STH_L    OPCODE4(0x19)
  89 #define OPCODE_STW_L    OPCODE4(0x1A)
  90 #define OPCODE_STWM     OPCODE4(0x1B)
  91
  92 #define MAJOR_OP(i) (((i)>>26)&0x3f)
  93 #define R1(i) (((i)>>21)&0x1f)
  94 #define R2(i) (((i)>>16)&0x1f)
  95 #define R3(i) ((i)&0x1f)
  96 #define FR3(i) ((((i)<<1)&0x1f)|(((i)>>6)&1))
  97 #define IM(i,n) (((i)>>1&((1<<(n-1))-1))|((i)&1?((0-1L)<<(n-1)):0))
  98 #define IM5_2(i) IM((i)>>16,5)
  99 #define IM5_3(i) IM((i),5)
 100 #define IM14(i) IM((i),14)
 101
 102 #define ERR_NOTHANDLED  -1
 103
 104 int unaligned_enabled __read_mostly = 1;
 105
 106 static int emulate_ldh(struct pt_regs *regs, int toreg)
 107 {
 108         unsigned long saddr = regs->ior;
 109         unsigned long val = 0, temp1;
 110         ASM_EXCEPTIONTABLE_VAR(ret);
 111
 112         DPRINTF("load " RFMT ":" RFMT " to r%d for 2 bytes\n",
 113                 regs->isr, regs->ior, toreg);
 114
 115         __asm__ __volatile__  (
 116 "       mtsp    %4, %%sr1\n"
 117 "1:     ldbs    0(%%sr1,%3), %2\n"
 118 "2:     ldbs    1(%%sr1,%3), %0\n"
 119 "       depw    %2, 23, 24, %0\n"
 120 "3:     \n"
 121         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b)
 122         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b)
 123         : "+r" (val), "+r" (ret), "=&r" (temp1)
 124         : "r" (saddr), "r" (regs->isr) );
 125
 126         DPRINTF("val = " RFMT "\n", val);
 127
 128         if (toreg)
 129                 regs->gr[toreg] = val;
 130
 131         return ret;
 132 }
 133
 134 static int emulate_ldw(struct pt_regs *regs, int toreg, int flop)
 135 {
 136         unsigned long saddr = regs->ior;
 137         unsigned long val = 0, temp1, temp2;
 138         ASM_EXCEPTIONTABLE_VAR(ret);
 139
 140         DPRINTF("load " RFMT ":" RFMT " to r%d for 4 bytes\n",
 141                 regs->isr, regs->ior, toreg);
 142
 143         __asm__ __volatile__  (
 144 "       zdep    %4,28,2,%2\n"           /* r19=(ofs&3)*8 */
 145 "       mtsp    %5, %%sr1\n"
 146 "       depw    %%r0,31,2,%4\n"
 147 "1:     ldw     0(%%sr1,%4),%0\n"
 148 "2:     ldw     4(%%sr1,%4),%3\n"
 149 "       subi    32,%2,%2\n"
 150 "       mtctl   %2,11\n"
 151 "       vshd    %0,%3,%0\n"
 152 "3:     \n"
 153         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b)
 154         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b)
 155         : "+r" (val), "+r" (ret), "=&r" (temp1), "=&r" (temp2)
 156         : "r" (saddr), "r" (regs->isr) );
 157
 158         DPRINTF("val = " RFMT "\n", val);
 159
 160         if (flop)
 161                 ((__u32*)(regs->fr))[toreg] = val;
 162         else if (toreg)
 163                 regs->gr[toreg] = val;
 164
 165         return ret;
 166 }
 167 static int emulate_ldd(struct pt_regs *regs, int toreg, int flop)
 168 {
 169         unsigned long saddr = regs->ior;
 170         __u64 val = 0;
 171         ASM_EXCEPTIONTABLE_VAR(ret);
 172
 173         DPRINTF("load " RFMT ":" RFMT " to r%d for 8 bytes\n",
 174                 regs->isr, regs->ior, toreg);
 175
 176         if (!IS_ENABLED(CONFIG_64BIT) && !flop)
 177                 return ERR_NOTHANDLED;
 178
 179 #ifdef CONFIG_64BIT
 180         __asm__ __volatile__  (
 181 "       depd,z  %3,60,3,%%r19\n"                /* r19=(ofs&7)*8 */
 182 "       mtsp    %4, %%sr1\n"
 183 "       depd    %%r0,63,3,%3\n"
 184 "1:     ldd     0(%%sr1,%3),%0\n"
 185 "2:     ldd     8(%%sr1,%3),%%r20\n"
 186 "       subi    64,%%r19,%%r19\n"
 187 "       mtsar   %%r19\n"
 188 "       shrpd   %0,%%r20,%%sar,%0\n"
 189 "3:     \n"
 190         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b)
 191         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b)
 192         : "=r" (val), "+r" (ret)
 193         : "0" (val), "r" (saddr), "r" (regs->isr)
 194         : "r19", "r20" );
 195 #else
 196     {
 197         unsigned long shift, temp1;
 198         __asm__ __volatile__  (
 199 "       zdep    %2,29,2,%3\n"           /* r19=(ofs&3)*8 */
 200 "       mtsp    %5, %%sr1\n"
 201 "       dep     %%r0,31,2,%2\n"
 202 "1:     ldw     0(%%sr1,%2),%0\n"
 203 "2:     ldw     4(%%sr1,%2),%R0\n"
 204 "3:     ldw     8(%%sr1,%2),%4\n"
 205 "       subi    32,%3,%3\n"
 206 "       mtsar   %3\n"
 207 "       vshd    %0,%R0,%0\n"
 208 "       vshd    %R0,%4,%R0\n"
 209 "4:     \n"
 210         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 4b)
 211         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 4b)
 212         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 4b)
 213         : "+r" (val), "+r" (ret), "+r" (saddr), "=&r" (shift), "=&r" (temp1)
 214         : "r" (regs->isr) );
 215     }
 216 #endif
 217
 218         DPRINTF("val = 0x%llx\n", val);
 219
 220         if (flop)
 221                 regs->fr[toreg] = val;
 222         else if (toreg)
 223                 regs->gr[toreg] = val;
 224
 225         return ret;
 226 }
 227
 228 static int emulate_sth(struct pt_regs *regs, int frreg)
 229 {
 230         unsigned long val = regs->gr[frreg], temp1;
 231         ASM_EXCEPTIONTABLE_VAR(ret);
 232
 233         if (!frreg)
 234                 val = 0;
 235
 236         DPRINTF("store r%d (" RFMT ") to " RFMT ":" RFMT " for 2 bytes\n", frreg,
 237                 val, regs->isr, regs->ior);
 238
 239         __asm__ __volatile__ (
 240 "       mtsp %4, %%sr1\n"
 241 "       extrw,u %2, 23, 8, %1\n"
 242 "1:     stb %1, 0(%%sr1, %3)\n"
 243 "2:     stb %2, 1(%%sr1, %3)\n"
 244 "3:     \n"
 245         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b)
 246         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b)
 247         : "+r" (ret), "=&r" (temp1)
 248         : "r" (val), "r" (regs->ior), "r" (regs->isr) );
 249
 250         return ret;
 251 }
 252
 253 static int emulate_stw(struct pt_regs *regs, int frreg, int flop)
 254 {
 255         unsigned long val;
 256         ASM_EXCEPTIONTABLE_VAR(ret);
 257
 258         if (flop)
 259                 val = ((__u32*)(regs->fr))[frreg];
 260         else if (frreg)
 261                 val = regs->gr[frreg];
 262         else
 263                 val = 0;
 264
 265         DPRINTF("store r%d (" RFMT ") to " RFMT ":" RFMT " for 4 bytes\n", frreg,
 266                 val, regs->isr, regs->ior);
 267
 268
 269         __asm__ __volatile__ (
 270 "       mtsp %3, %%sr1\n"
 271 "       zdep    %2, 28, 2, %%r19\n"
 272 "       dep     %%r0, 31, 2, %2\n"
 273 "       mtsar   %%r19\n"
 274 "       depwi,z -2, %%sar, 32, %%r19\n"
 275 "1:     ldw     0(%%sr1,%2),%%r20\n"
 276 "2:     ldw     4(%%sr1,%2),%%r21\n"
 277 "       vshd    %%r0, %1, %%r22\n"
 278 "       vshd    %1, %%r0, %%r1\n"
 279 "       and     %%r20, %%r19, %%r20\n"
 280 "       andcm   %%r21, %%r19, %%r21\n"
 281 "       or      %%r22, %%r20, %%r20\n"
 282 "       or      %%r1, %%r21, %%r21\n"
 283 "       stw     %%r20,0(%%sr1,%2)\n"
 284 "       stw     %%r21,4(%%sr1,%2)\n"
 285 "3:     \n"
 286         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b)
 287         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b)
 288         : "+r" (ret)
 289         : "r" (val), "r" (regs->ior), "r" (regs->isr)
 290         : "r19", "r20", "r21", "r22", "r1" );
 291
 292         return ret;
 293 }
 294 static int emulate_std(struct pt_regs *regs, int frreg, int flop)
 295 {
 296         __u64 val;
 297         ASM_EXCEPTIONTABLE_VAR(ret);
 298
 299         if (flop)
 300                 val = regs->fr[frreg];
 301         else if (frreg)
 302                 val = regs->gr[frreg];
 303         else
 304                 val = 0;
 305
 306         DPRINTF("store r%d (0x%016llx) to " RFMT ":" RFMT " for 8 bytes\n", frreg,
 307                 val,  regs->isr, regs->ior);
 308
 309         if (!IS_ENABLED(CONFIG_64BIT) && !flop)
 310                 return ERR_NOTHANDLED;
 311
 312 #ifdef CONFIG_64BIT
 313         __asm__ __volatile__ (
 314 "       mtsp %3, %%sr1\n"
 315 "       depd,z  %2, 60, 3, %%r19\n"
 316 "       depd    %%r0, 63, 3, %2\n"
 317 "       mtsar   %%r19\n"
 318 "       depdi,z -2, %%sar, 64, %%r19\n"
 319 "1:     ldd     0(%%sr1,%2),%%r20\n"
 320 "2:     ldd     8(%%sr1,%2),%%r21\n"
 321 "       shrpd   %%r0, %1, %%sar, %%r22\n"
 322 "       shrpd   %1, %%r0, %%sar, %%r1\n"
 323 "       and     %%r20, %%r19, %%r20\n"
 324 "       andcm   %%r21, %%r19, %%r21\n"
 325 "       or      %%r22, %%r20, %%r20\n"
 326 "       or      %%r1, %%r21, %%r21\n"
 327 "3:     std     %%r20,0(%%sr1,%2)\n"
 328 "4:     std     %%r21,8(%%sr1,%2)\n"
 329 "5:     \n"
 330         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 5b)
 331         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 5b)
 332         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 5b)
 333         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(4b, 5b)
 334         : "+r" (ret)
 335         : "r" (val), "r" (regs->ior), "r" (regs->isr)
 336         : "r19", "r20", "r21", "r22", "r1" );
 337 #else
 338     {
 339         unsigned long valh=(val>>32),vall=(val&0xffffffffl);
 340         __asm__ __volatile__ (
 341 "       mtsp    %4, %%sr1\n"
 342 "       zdep    %2, 29, 2, %%r19\n"
 343 "       dep     %%r0, 31, 2, %3\n"
 344 "       mtsar   %%r19\n"
 345 "       zvdepi  -2, 32, %%r19\n"
 346 "1:     ldw     0(%%sr1,%3),%%r20\n"
 347 "2:     ldw     8(%%sr1,%3),%%r21\n"
 348 "       vshd    %1, %2, %%r1\n"
 349 "       vshd    %%r0, %1, %1\n"
 350 "       vshd    %2, %%r0, %2\n"
 351 "       and     %%r20, %%r19, %%r20\n"
 352 "       andcm   %%r21, %%r19, %%r21\n"
 353 "       or      %1, %%r20, %1\n"
 354 "       or      %2, %%r21, %2\n"
 355 "3:     stw     %1,0(%%sr1,%3)\n"
 356 "4:     stw     %%r1,4(%%sr1,%3)\n"
 357 "5:     stw     %2,8(%%sr1,%3)\n"
 358 "6:     \n"
 359         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 6b)
 360         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 6b)
 361         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 6b)
 362         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(4b, 6b)
 363         ASM_EXCEPTIONTABLE_ENTRY_EFAULT(5b, 6b)
 364         : "+r" (ret)
 365         : "r" (valh), "r" (vall), "r" (regs->ior), "r" (regs->isr)
 366         : "r19", "r20", "r21", "r1" );
 367     }
 368 #endif
 369
 370         return ret;
 371 }
 372
 373 void handle_unaligned(struct pt_regs *regs)
 374 {
 375         static DEFINE_RATELIMIT_STATE(ratelimit, 5 * HZ, 5);
 376         unsigned long newbase = R1(regs->iir)?regs->gr[R1(regs->iir)]:0;
 377         int modify = 0;
 378         int ret = ERR_NOTHANDLED;
 379
 380         __inc_irq_stat(irq_unaligned_count);
 381
 382         /* log a message with pacing */
 383         if (user_mode(regs)) {
 384                 if (current->thread.flags & PARISC_UAC_SIGBUS) {
 385                         goto force_sigbus;
 386                 }
 387
 388                 if (!(current->thread.flags & PARISC_UAC_NOPRINT) &&
 389                         __ratelimit(&ratelimit)) {
 390                         printk(KERN_WARNING "%s(%d): unaligned access to " RFMT
 391                                 " at ip " RFMT " (iir " RFMT ")\n",
 392                                 current->comm, task_pid_nr(current), regs->ior,
 393                                 regs->iaoq[0], regs->iir);
 394 #ifdef DEBUG_UNALIGNED
 395                         show_regs(regs);
 396 #endif
 397                 }
 398
 399                 if (!unaligned_enabled)
 400                         goto force_sigbus;
 401         }
 402
 403         /* handle modification - OK, it's ugly, see the instruction manual */
 404         switch (MAJOR_OP(regs->iir))
 405         {
 406         case 0x03:
 407         case 0x09:
 408         case 0x0b:
 409                 if (regs->iir&0x20)
 410                 {
 411                         modify = 1;
 412                         if (regs->iir&0x1000)           /* short loads */
 413                                 if (regs->iir&0x200)
 414                                         newbase += IM5_3(regs->iir);
 415                                 else
 416                                         newbase += IM5_2(regs->iir);
 417                         else if (regs->iir&0x2000)      /* scaled indexed */
 418                         {
 419                                 int shift=0;
 420                                 switch (regs->iir & OPCODE1_MASK)
 421                                 {
 422                                 case OPCODE_LDH_I:
 423                                         shift= 1; break;
 424                                 case OPCODE_LDW_I:
 425                                         shift= 2; break;
 426                                 case OPCODE_LDD_I:
 427                                 case OPCODE_LDDA_I:
 428                                         shift= 3; break;
 429                                 }
 430                                 newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0)<<shift;
 431                         } else                          /* simple indexed */
 432                                 newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0);
 433                 }
 434                 break;
 435         case 0x13:
 436         case 0x1b:
 437                 modify = 1;
 438                 newbase += IM14(regs->iir);
 439                 break;
 440         case 0x14:
 441         case 0x1c:
 442                 if (regs->iir&8)
 443                 {
 444                         modify = 1;
 445                         newbase += IM14(regs->iir&~0xe);
 446                 }
 447                 break;
 448         case 0x16:
 449         case 0x1e:
 450                 modify = 1;
 451                 newbase += IM14(regs->iir&6);
 452                 break;
 453         case 0x17:
 454         case 0x1f:
 455                 if (regs->iir&4)
 456                 {
 457                         modify = 1;
 458                         newbase += IM14(regs->iir&~4);
 459                 }
 460                 break;
 461         }
 462
 463         /* TODO: make this cleaner... */
 464         switch (regs->iir & OPCODE1_MASK)
 465         {
 466         case OPCODE_LDH_I:
 467         case OPCODE_LDH_S:
 468                 ret = emulate_ldh(regs, R3(regs->iir));
 469                 break;
 470
 471         case OPCODE_LDW_I:
 472         case OPCODE_LDWA_I:
 473         case OPCODE_LDW_S:
 474         case OPCODE_LDWA_S:
 475                 ret = emulate_ldw(regs, R3(regs->iir),0);
 476                 break;
 477
 478         case OPCODE_STH:
 479                 ret = emulate_sth(regs, R2(regs->iir));
 480                 break;
 481
 482         case OPCODE_STW:
 483         case OPCODE_STWA:
 484                 ret = emulate_stw(regs, R2(regs->iir),0);
 485                 break;
 486
 487 #ifdef CONFIG_64BIT
 488         case OPCODE_LDD_I:
 489         case OPCODE_LDDA_I:
 490         case OPCODE_LDD_S:
 491         case OPCODE_LDDA_S:
 492                 ret = emulate_ldd(regs, R3(regs->iir),0);
 493                 break;
 494
 495         case OPCODE_STD:
 496         case OPCODE_STDA:
 497                 ret = emulate_std(regs, R2(regs->iir),0);
 498                 break;
 499 #endif
 500
 501         case OPCODE_FLDWX:
 502         case OPCODE_FLDWS:
 503         case OPCODE_FLDWXR:
 504         case OPCODE_FLDWSR:
 505                 ret = emulate_ldw(regs,FR3(regs->iir),1);
 506                 break;
 507
 508         case OPCODE_FLDDX:
 509         case OPCODE_FLDDS:
 510                 ret = emulate_ldd(regs,R3(regs->iir),1);
 511                 break;
 512
 513         case OPCODE_FSTWX:
 514         case OPCODE_FSTWS:
 515         case OPCODE_FSTWXR:
 516         case OPCODE_FSTWSR:
 517                 ret = emulate_stw(regs,FR3(regs->iir),1);
 518                 break;
 519
 520         case OPCODE_FSTDX:
 521         case OPCODE_FSTDS:
 522                 ret = emulate_std(regs,R3(regs->iir),1);
 523                 break;
 524
 525         case OPCODE_LDCD_I:
 526         case OPCODE_LDCW_I:
 527         case OPCODE_LDCD_S:
 528         case OPCODE_LDCW_S:
 529                 ret = ERR_NOTHANDLED;   /* "undefined", but lets kill them. */
 530                 break;
 531         }
 532         switch (regs->iir & OPCODE2_MASK)
 533         {
 534         case OPCODE_FLDD_L:
 535                 ret = emulate_ldd(regs,R2(regs->iir),1);
 536                 break;
 537         case OPCODE_FSTD_L:
 538                 ret = emulate_std(regs, R2(regs->iir),1);
 539                 break;
 540 #ifdef CONFIG_64BIT
 541         case OPCODE_LDD_L:
 542                 ret = emulate_ldd(regs, R2(regs->iir),0);
 543                 break;
 544         case OPCODE_STD_L:
 545                 ret = emulate_std(regs, R2(regs->iir),0);
 546                 break;
 547 #endif
 548         }
 549         switch (regs->iir & OPCODE3_MASK)
 550         {
 551         case OPCODE_FLDW_L:
 552                 ret = emulate_ldw(regs, R2(regs->iir), 1);
 553                 break;
 554         case OPCODE_LDW_M:
 555                 ret = emulate_ldw(regs, R2(regs->iir), 0);
 556                 break;
 557
 558         case OPCODE_FSTW_L:
 559                 ret = emulate_stw(regs, R2(regs->iir),1);
 560                 break;
 561         case OPCODE_STW_M:
 562                 ret = emulate_stw(regs, R2(regs->iir),0);
 563                 break;
 564         }
 565         switch (regs->iir & OPCODE4_MASK)
 566         {
 567         case OPCODE_LDH_L:
 568                 ret = emulate_ldh(regs, R2(regs->iir));
 569                 break;
 570         case OPCODE_LDW_L:
 571         case OPCODE_LDWM:
 572                 ret = emulate_ldw(regs, R2(regs->iir),0);
 573                 break;
 574         case OPCODE_STH_L:
 575                 ret = emulate_sth(regs, R2(regs->iir));
 576                 break;
 577         case OPCODE_STW_L:
 578         case OPCODE_STWM:
 579                 ret = emulate_stw(regs, R2(regs->iir),0);
 580                 break;
 581         }
 582
 583         if (ret == 0 && modify && R1(regs->iir))
 584                 regs->gr[R1(regs->iir)] = newbase;
 585
 586
 587         if (ret == ERR_NOTHANDLED)
 588                 printk(KERN_CRIT "Not-handled unaligned insn 0x%08lx\n", regs->iir);
 589
 590         DPRINTF("ret = %d\n", ret);
 591
 592         if (ret)
 593         {
 594                 /*
 595                  * The unaligned handler failed.
 596                  * If we were called by __get_user() or __put_user() jump
 597                  * to it's exception fixup handler instead of crashing.
 598                  */
 599                 if (!user_mode(regs) && fixup_exception(regs))
 600                         return;
 601
 602                 printk(KERN_CRIT "Unaligned handler failed, ret = %d\n", ret);
 603                 die_if_kernel("Unaligned data reference", regs, 28);
 604
 605                 if (ret == -EFAULT)
 606                 {
 607                         force_sig_fault(SIGSEGV, SEGV_MAPERR,
 608                                         (void __user *)regs->ior);
 609                 }
 610                 else
 611                 {
 612 force_sigbus:
 613                         /* couldn't handle it ... */
 614                         force_sig_fault(SIGBUS, BUS_ADRALN,
 615                                         (void __user *)regs->ior);
 616                 }
 617
 618                 return;
 619         }
 620
 621         /* else we handled it, let life go on. */
 622         regs->gr[0]|=PSW_N;
 623 }
 624
 625 /*
 626  * NB: check_unaligned() is only used for PCXS processors right
 627  * now, so we only check for PA1.1 encodings at this point.
 628  */
 629
 630 int
 631 check_unaligned(struct pt_regs *regs)
 632 {
 633         unsigned long align_mask;
 634
 635         /* Get alignment mask */
 636
 637         align_mask = 0UL;
 638         switch (regs->iir & OPCODE1_MASK) {
 639
 640         case OPCODE_LDH_I:
 641         case OPCODE_LDH_S:
 642         case OPCODE_STH:
 643                 align_mask = 1UL;
 644                 break;
 645
 646         case OPCODE_LDW_I:
 647         case OPCODE_LDWA_I:
 648         case OPCODE_LDW_S:
 649         case OPCODE_LDWA_S:
 650         case OPCODE_STW:
 651         case OPCODE_STWA:
 652                 align_mask = 3UL;
 653                 break;
 654
 655         default:
 656                 switch (regs->iir & OPCODE4_MASK) {
 657                 case OPCODE_LDH_L:
 658                 case OPCODE_STH_L:
 659                         align_mask = 1UL;
 660                         break;
 661                 case OPCODE_LDW_L:
 662                 case OPCODE_LDWM:
 663                 case OPCODE_STW_L:
 664                 case OPCODE_STWM:
 665                         align_mask = 3UL;
 666                         break;
 667                 }
 668                 break;
 669         }
 670
 671         return (int)(regs->ior & align_mask);
 672 }
 673