2 * linux/arch/parisc/kernel/time.c
4 * Copyright (C) 1991, 1992, 1995 Linus Torvalds
5 * Modifications for ARM (C) 1994, 1995, 1996,1997 Russell King
6 * Copyright (C) 1999 SuSE GmbH, (Philipp Rumpf, prumpf@tux.org)
8 * 1994-07-02 Alan Modra
9 * fixed set_rtc_mmss, fixed time.year for >= 2000, new mktime
10 * 1998-12-20 Updated NTP code according to technical memorandum Jan '96
11 * "A Kernel Model for Precision Timekeeping" by Dave Mills
13 #include <linux/errno.h>
14 #include <linux/module.h>
15 #include <linux/rtc.h>
16 #include <linux/sched.h>
17 #include <linux/sched_clock.h>
18 #include <linux/kernel.h>
19 #include <linux/param.h>
20 #include <linux/string.h>
22 #include <linux/interrupt.h>
23 #include <linux/time.h>
24 #include <linux/init.h>
25 #include <linux/smp.h>
26 #include <linux/profile.h>
27 #include <linux/clocksource.h>
28 #include <linux/platform_device.h>
29 #include <linux/ftrace.h>
31 #include <asm/uaccess.h>
35 #include <asm/param.h>
39 #include <linux/timex.h>
41 static unsigned long clocktick __read_mostly; /* timer cycles per tick */
44 * We keep time on PA-RISC Linux by using the Interval Timer which is
45 * a pair of registers; one is read-only and one is write-only; both
46 * accessed through CR16. The read-only register is 32 or 64 bits wide,
47 * and increments by 1 every CPU clock tick. The architecture only
48 * guarantees us a rate between 0.5 and 2, but all implementations use a
49 * rate of 1. The write-only register is 32-bits wide. When the lowest
50 * 32 bits of the read-only register compare equal to the write-only
51 * register, it raises a maskable external interrupt. Each processor has
52 * an Interval Timer of its own and they are not synchronised.
54 * We want to generate an interrupt every 1/HZ seconds. So we program
55 * CR16 to interrupt every @clocktick cycles. The it_value in cpu_data
56 * is programmed with the intended time of the next tick. We can be
57 * held off for an arbitrarily long period of time by interrupts being
58 * disabled, so we may miss one or more ticks.
60 irqreturn_t __irq_entry timer_interrupt(int irq, void *dev_id)
62 unsigned long now, now2;
63 unsigned long next_tick;
64 unsigned long cycles_elapsed, ticks_elapsed = 1;
65 unsigned long cycles_remainder;
66 unsigned int cpu = smp_processor_id();
67 struct cpuinfo_parisc *cpuinfo = &per_cpu(cpu_data, cpu);
69 /* gcc can optimize for "read-only" case with a local clocktick */
70 unsigned long cpt = clocktick;
72 profile_tick(CPU_PROFILING);
74 /* Initialize next_tick to the expected tick time. */
75 next_tick = cpuinfo->it_value;
77 /* Get current cycle counter (Control Register 16). */
80 cycles_elapsed = now - next_tick;
82 if ((cycles_elapsed >> 6) < cpt) {
83 /* use "cheap" math (add/subtract) instead
84 * of the more expensive div/mul method
86 cycles_remainder = cycles_elapsed;
87 while (cycles_remainder > cpt) {
88 cycles_remainder -= cpt;
92 /* TODO: Reduce this to one fdiv op */
93 cycles_remainder = cycles_elapsed % cpt;
94 ticks_elapsed += cycles_elapsed / cpt;
97 /* convert from "division remainder" to "remainder of clock tick" */
98 cycles_remainder = cpt - cycles_remainder;
100 /* Determine when (in CR16 cycles) next IT interrupt will fire.
101 * We want IT to fire modulo clocktick even if we miss/skip some.
102 * But those interrupts don't in fact get delivered that regularly.
104 next_tick = now + cycles_remainder;
106 cpuinfo->it_value = next_tick;
108 /* Program the IT when to deliver the next interrupt.
109 * Only bottom 32-bits of next_tick are writable in CR16!
111 mtctl(next_tick, 16);
113 /* Skip one clocktick on purpose if we missed next_tick.
114 * The new CR16 must be "later" than current CR16 otherwise
115 * itimer would not fire until CR16 wrapped - e.g 4 seconds
116 * later on a 1Ghz processor. We'll account for the missed
117 * tick on the next timer interrupt.
119 * "next_tick - now" will always give the difference regardless
120 * if one or the other wrapped. If "now" is "bigger" we'll end up
121 * with a very large unsigned number.
124 if (next_tick - now2 > cpt)
125 mtctl(next_tick+cpt, 16);
129 * GGG: DEBUG code for how many cycles programming CR16 used.
131 if (unlikely(now2 - now > 0x3000)) /* 12K cycles */
132 printk (KERN_CRIT "timer_interrupt(CPU %d): SLOW! 0x%lx cycles!"
134 " next/now %lX/%lX\n",
135 cpu, now2 - now, cycles_elapsed, cycles_remainder,
139 /* Can we differentiate between "early CR16" (aka Scenario 1) and
140 * "long delay" (aka Scenario 3)? I don't think so.
142 * Timer_interrupt will be delivered at least a few hundred cycles
143 * after the IT fires. But it's arbitrary how much time passes
144 * before we call it "late". I've picked one second.
146 * It's important NO printk's are between reading CR16 and
147 * setting up the next value. May introduce huge variance.
149 if (unlikely(ticks_elapsed > HZ)) {
150 /* Scenario 3: very long delay? bad in any case */
151 printk (KERN_CRIT "timer_interrupt(CPU %d): delayed!"
152 " cycles %lX rem %lX "
153 " next/now %lX/%lX\n",
155 cycles_elapsed, cycles_remainder,
159 /* Done mucking with unreliable delivery of interrupts.
160 * Go do system house keeping.
163 if (!--cpuinfo->prof_counter) {
164 cpuinfo->prof_counter = cpuinfo->prof_multiplier;
165 update_process_times(user_mode(get_irq_regs()));
169 xtime_update(ticks_elapsed);
175 unsigned long profile_pc(struct pt_regs *regs)
177 unsigned long pc = instruction_pointer(regs);
179 if (regs->gr[0] & PSW_N)
183 if (in_lock_functions(pc))
189 EXPORT_SYMBOL(profile_pc);
192 /* clock source code */
194 static cycle_t notrace read_cr16(struct clocksource *cs)
199 static struct clocksource clocksource_cr16 = {
203 .mask = CLOCKSOURCE_MASK(BITS_PER_LONG),
204 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
207 void __init start_cpu_itimer(void)
209 unsigned int cpu = smp_processor_id();
210 unsigned long next_tick = mfctl(16) + clocktick;
212 mtctl(next_tick, 16); /* kick off Interval Timer (CR16) */
214 per_cpu(cpu_data, cpu).it_value = next_tick;
217 #if IS_ENABLED(CONFIG_RTC_DRV_GENERIC)
218 static int rtc_generic_get_time(struct device *dev, struct rtc_time *tm)
220 struct pdc_tod tod_data;
222 memset(tm, 0, sizeof(*tm));
223 if (pdc_tod_read(&tod_data) < 0)
226 /* we treat tod_sec as unsigned, so this can work until year 2106 */
227 rtc_time64_to_tm(tod_data.tod_sec, tm);
228 return rtc_valid_tm(tm);
231 static int rtc_generic_set_time(struct device *dev, struct rtc_time *tm)
233 time64_t secs = rtc_tm_to_time64(tm);
235 if (pdc_tod_set(secs, 0) < 0)
241 static const struct rtc_class_ops rtc_generic_ops = {
242 .read_time = rtc_generic_get_time,
243 .set_time = rtc_generic_set_time,
246 static int __init rtc_init(void)
248 struct platform_device *pdev;
250 pdev = platform_device_register_data(NULL, "rtc-generic", -1,
252 sizeof(rtc_generic_ops));
254 return PTR_ERR_OR_ZERO(pdev);
256 device_initcall(rtc_init);
259 void read_persistent_clock(struct timespec *ts)
261 static struct pdc_tod tod_data;
262 if (pdc_tod_read(&tod_data) == 0) {
263 ts->tv_sec = tod_data.tod_sec;
264 ts->tv_nsec = tod_data.tod_usec * 1000;
266 printk(KERN_ERR "Error reading tod clock\n");
273 static u64 notrace read_cr16_sched_clock(void)
280 * timer interrupt and sched_clock() initialization
283 void __init time_init(void)
285 unsigned long cr16_hz;
287 clocktick = (100 * PAGE0->mem_10msec) / HZ;
288 start_cpu_itimer(); /* get CPU 0 started */
290 cr16_hz = 100 * PAGE0->mem_10msec; /* Hz */
292 /* register at clocksource framework */
293 clocksource_register_hz(&clocksource_cr16, cr16_hz);
295 /* register as sched_clock source */
296 sched_clock_register(read_cr16_sched_clock, BITS_PER_LONG, cr16_hz);