1 # SPDX-License-Identifier: GPL-2.0
3 # For a description of the syntax of this configuration file,
4 # see Documentation/kbuild/kconfig-language.txt.
9 select ARCH_32BIT_OFF_T
10 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
12 select OF_EARLY_FLATTREE
14 select HANDLE_DOMAIN_IRQ
16 select HAVE_ARCH_TRACEHOOK
18 select GENERIC_IRQ_CHIP
19 select GENERIC_IRQ_PROBE
20 select GENERIC_IRQ_SHOW
22 select GENERIC_CPU_DEVICES
24 select GENERIC_ATOMIC64
25 select GENERIC_CLOCKEVENTS
26 select GENERIC_CLOCKEVENTS_BROADCAST
27 select GENERIC_STRNCPY_FROM_USER
28 select GENERIC_STRNLEN_USER
29 select GENERIC_SMP_IDLE_THREAD
30 select MODULES_USE_ELF_RELA
31 select HAVE_DEBUG_STACKOVERFLOW
33 select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1
34 select ARCH_USE_QUEUED_SPINLOCKS
35 select ARCH_USE_QUEUED_RWLOCKS
37 select ARCH_WANT_FRAME_POINTERS
38 select GENERIC_IRQ_MULTI_HANDLER
46 config RWSEM_GENERIC_SPINLOCK
49 config RWSEM_XCHGADD_ALGORITHM
52 config GENERIC_HWEIGHT
58 config TRACE_IRQFLAGS_SUPPORT
61 # For now, use generic checksum functions
62 #These can be reimplemented in assembly later if so inclined
66 config STACKTRACE_SUPPORT
69 config LOCKDEP_SUPPORT
72 menu "Processor type and features"
75 prompt "Subarchitecture"
81 Generic OpenRISC 1200 architecture
85 config DCACHE_WRITETHROUGH
86 bool "Have write through data caches"
89 Select this if your implementation features write through data caches.
90 Selecting 'N' here will allow the kernel to force flushing of data
91 caches at relevant times. Most OpenRISC implementations support write-
96 config OPENRISC_BUILTIN_DTB
100 menu "Class II Instructions"
102 config OPENRISC_HAVE_INST_FF1
103 bool "Have instruction l.ff1"
106 Select this if your implementation has the Class II instruction l.ff1
108 config OPENRISC_HAVE_INST_FL1
109 bool "Have instruction l.fl1"
112 Select this if your implementation has the Class II instruction l.fl1
114 config OPENRISC_HAVE_INST_MUL
115 bool "Have instruction l.mul for hardware multiply"
118 Select this if your implementation has a hardware multiply instruction
120 config OPENRISC_HAVE_INST_DIV
121 bool "Have instruction l.div for hardware divide"
124 Select this if your implementation has a hardware divide instruction
128 int "Maximum number of CPUs (2-32)"
134 bool "Symmetric Multi-Processing support"
136 This enables support for systems with more than one CPU. If you have
137 a system with only one CPU, say N. If you have a system with more
140 If you don't know what to do here, say N.
142 source "kernel/Kconfig.hz"
144 config OPENRISC_NO_SPR_SR_DSX
145 bool "use SPR_SR_DSX software emulation" if OR1K_1200
148 SPR_SR_DSX bit is status register bit indicating whether
149 the last exception has happened in delay slot.
151 OpenRISC architecture makes it optional to have it implemented
152 in hardware and the OR1200 does not have it.
154 Say N here if you know that your OpenRISC processor has
155 SPR_SR_DSX bit implemented. Say Y if you are unsure.
157 config OPENRISC_HAVE_SHADOW_GPRS
158 bool "Support for shadow gpr files" if !SMP
161 Say Y here if your OpenRISC processor features shadowed
162 register files. They will in such case be used as a
163 scratch reg storage on exception entry.
165 On SMP systems, this feature is mandatory.
166 On a unicore system it's safe to say N here if you are unsure.
169 string "Default kernel command string"
172 On some architectures there is currently no way for the boot loader
173 to pass arguments to the kernel. For these architectures, you should
174 supply some command-line options at build time by entering them
177 menu "Debugging options"
179 config JUMP_UPON_UNHANDLED_EXCEPTION
180 bool "Try to die gracefully"
183 Now this puts kernel into infinite loop after first oops. Till
184 your kernel crashes this doesn't have any influence.
186 Say Y if you are unsure.
188 config OPENRISC_ESR_EXCEPTION_BUG_CHECK
189 bool "Check for possible ESR exception bug"
192 This option enables some checks that might expose some problems
195 Say N if you are unsure.