1 # SPDX-License-Identifier: GPL-2.0
3 # For a description of the syntax of this configuration file,
4 # see Documentation/kbuild/kconfig-language.txt.
9 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
11 select OF_EARLY_FLATTREE
13 select HANDLE_DOMAIN_IRQ
15 select HAVE_ARCH_TRACEHOOK
17 select GENERIC_IRQ_CHIP
18 select GENERIC_IRQ_PROBE
19 select GENERIC_IRQ_SHOW
21 select GENERIC_CPU_DEVICES
23 select GENERIC_ATOMIC64
24 select GENERIC_CLOCKEVENTS
25 select GENERIC_CLOCKEVENTS_BROADCAST
26 select GENERIC_STRNCPY_FROM_USER
27 select GENERIC_STRNLEN_USER
28 select GENERIC_SMP_IDLE_THREAD
29 select MODULES_USE_ELF_RELA
30 select HAVE_DEBUG_STACKOVERFLOW
32 select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1
33 select ARCH_USE_QUEUED_SPINLOCKS
34 select ARCH_USE_QUEUED_RWLOCKS
36 select ARCH_WANT_FRAME_POINTERS
37 select GENERIC_IRQ_MULTI_HANDLER
45 config RWSEM_GENERIC_SPINLOCK
48 config RWSEM_XCHGADD_ALGORITHM
51 config GENERIC_HWEIGHT
57 config TRACE_IRQFLAGS_SUPPORT
60 # For now, use generic checksum functions
61 #These can be reimplemented in assembly later if so inclined
65 config STACKTRACE_SUPPORT
68 config LOCKDEP_SUPPORT
71 menu "Processor type and features"
74 prompt "Subarchitecture"
80 Generic OpenRISC 1200 architecture
84 config DCACHE_WRITETHROUGH
85 bool "Have write through data caches"
88 Select this if your implementation features write through data caches.
89 Selecting 'N' here will allow the kernel to force flushing of data
90 caches at relevant times. Most OpenRISC implementations support write-
95 config OPENRISC_BUILTIN_DTB
99 menu "Class II Instructions"
101 config OPENRISC_HAVE_INST_FF1
102 bool "Have instruction l.ff1"
105 Select this if your implementation has the Class II instruction l.ff1
107 config OPENRISC_HAVE_INST_FL1
108 bool "Have instruction l.fl1"
111 Select this if your implementation has the Class II instruction l.fl1
113 config OPENRISC_HAVE_INST_MUL
114 bool "Have instruction l.mul for hardware multiply"
117 Select this if your implementation has a hardware multiply instruction
119 config OPENRISC_HAVE_INST_DIV
120 bool "Have instruction l.div for hardware divide"
123 Select this if your implementation has a hardware divide instruction
127 int "Maximum number of CPUs (2-32)"
133 bool "Symmetric Multi-Processing support"
135 This enables support for systems with more than one CPU. If you have
136 a system with only one CPU, say N. If you have a system with more
139 If you don't know what to do here, say N.
141 source "kernel/Kconfig.hz"
143 config OPENRISC_NO_SPR_SR_DSX
144 bool "use SPR_SR_DSX software emulation" if OR1K_1200
147 SPR_SR_DSX bit is status register bit indicating whether
148 the last exception has happened in delay slot.
150 OpenRISC architecture makes it optional to have it implemented
151 in hardware and the OR1200 does not have it.
153 Say N here if you know that your OpenRISC processor has
154 SPR_SR_DSX bit implemented. Say Y if you are unsure.
156 config OPENRISC_HAVE_SHADOW_GPRS
157 bool "Support for shadow gpr files" if !SMP
160 Say Y here if your OpenRISC processor features shadowed
161 register files. They will in such case be used as a
162 scratch reg storage on exception entry.
164 On SMP systems, this feature is mandatory.
165 On a unicore system it's safe to say N here if you are unsure.
168 string "Default kernel command string"
171 On some architectures there is currently no way for the boot loader
172 to pass arguments to the kernel. For these architectures, you should
173 supply some command-line options at build time by entering them
176 menu "Debugging options"
178 config JUMP_UPON_UNHANDLED_EXCEPTION
179 bool "Try to die gracefully"
182 Now this puts kernel into infinite loop after first oops. Till
183 your kernel crashes this doesn't have any influence.
185 Say Y if you are unsure.
187 config OPENRISC_ESR_EXCEPTION_BUG_CHECK
188 bool "Check for possible ESR exception bug"
191 This option enables some checks that might expose some problems
194 Say N if you are unsure.