arch/nds32/kernel/setup.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (C) 2005-2017 Andes Technology Corporation
   3
   4 #include <linux/cpu.h>
   5 #include <linux/memblock.h>
   6 #include <linux/seq_file.h>
   7 #include <linux/console.h>
   8 #include <linux/screen_info.h>
   9 #include <linux/delay.h>
  10 #include <linux/dma-mapping.h>
  11 #include <linux/of_fdt.h>
  12 #include <linux/of_platform.h>
  13 #include <asm/setup.h>
  14 #include <asm/sections.h>
  15 #include <asm/proc-fns.h>
  16 #include <asm/cache_info.h>
  17 #include <asm/elf.h>
  18 #include <nds32_intrinsic.h>
  19
  20 #define HWCAP_MFUSR_PC          0x000001
  21 #define HWCAP_EXT               0x000002
  22 #define HWCAP_EXT2              0x000004
  23 #define HWCAP_FPU               0x000008
  24 #define HWCAP_AUDIO             0x000010
  25 #define HWCAP_BASE16            0x000020
  26 #define HWCAP_STRING            0x000040
  27 #define HWCAP_REDUCED_REGS      0x000080
  28 #define HWCAP_VIDEO             0x000100
  29 #define HWCAP_ENCRYPT           0x000200
  30 #define HWCAP_EDM               0x000400
  31 #define HWCAP_LMDMA             0x000800
  32 #define HWCAP_PFM               0x001000
  33 #define HWCAP_HSMP              0x002000
  34 #define HWCAP_TRACE             0x004000
  35 #define HWCAP_DIV               0x008000
  36 #define HWCAP_MAC               0x010000
  37 #define HWCAP_L2C               0x020000
  38 #define HWCAP_FPU_DP            0x040000
  39 #define HWCAP_V2                0x080000
  40 #define HWCAP_DX_REGS           0x100000
  41
  42 unsigned long cpu_id, cpu_rev, cpu_cfgid;
  43 char cpu_series;
  44 char *endianness = NULL;
  45
  46 unsigned int __atags_pointer __initdata;
  47 unsigned int elf_hwcap;
  48 EXPORT_SYMBOL(elf_hwcap);
  49
  50 /*
  51  * The following string table, must sync with HWCAP_xx bitmask,
  52  * which is defined in <asm/procinfo.h>
  53  */
  54 static const char *hwcap_str[] = {
  55         "mfusr_pc",
  56         "perf1",
  57         "perf2",
  58         "fpu",
  59         "audio",
  60         "16b",
  61         "string",
  62         "reduced_regs",
  63         "video",
  64         "encrypt",
  65         "edm",
  66         "lmdma",
  67         "pfm",
  68         "hsmp",
  69         "trace",
  70         "div",
  71         "mac",
  72         "l2c",
  73         "dx_regs",
  74         "v2",
  75         NULL,
  76 };
  77
  78 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
  79 #define WRITE_METHOD "write through"
  80 #else
  81 #define WRITE_METHOD "write back"
  82 #endif
  83
  84 struct cache_info L1_cache_info[2];
  85 static void __init dump_cpu_info(int cpu)
  86 {
  87         int i, p = 0;
  88         char str[sizeof(hwcap_str) + 16];
  89
  90         for (i = 0; hwcap_str[i]; i++) {
  91                 if (elf_hwcap & (1 << i)) {
  92                         sprintf(str + p, "%s ", hwcap_str[i]);
  93                         p += strlen(hwcap_str[i]) + 1;
  94                 }
  95         }
  96
  97         pr_info("CPU%d Features: %s\n", cpu, str);
  98
  99         L1_cache_info[ICACHE].ways = CACHE_WAY(ICACHE);
 100         L1_cache_info[ICACHE].line_size = CACHE_LINE_SIZE(ICACHE);
 101         L1_cache_info[ICACHE].sets = CACHE_SET(ICACHE);
 102         L1_cache_info[ICACHE].size =
 103             L1_cache_info[ICACHE].ways * L1_cache_info[ICACHE].line_size *
 104             L1_cache_info[ICACHE].sets / 1024;
 105         pr_info("L1I:%dKB/%dS/%dW/%dB\n", L1_cache_info[ICACHE].size,
 106                 L1_cache_info[ICACHE].sets, L1_cache_info[ICACHE].ways,
 107                 L1_cache_info[ICACHE].line_size);
 108         L1_cache_info[DCACHE].ways = CACHE_WAY(DCACHE);
 109         L1_cache_info[DCACHE].line_size = CACHE_LINE_SIZE(DCACHE);
 110         L1_cache_info[DCACHE].sets = CACHE_SET(DCACHE);
 111         L1_cache_info[DCACHE].size =
 112             L1_cache_info[DCACHE].ways * L1_cache_info[DCACHE].line_size *
 113             L1_cache_info[DCACHE].sets / 1024;
 114         pr_info("L1D:%dKB/%dS/%dW/%dB\n", L1_cache_info[DCACHE].size,
 115                 L1_cache_info[DCACHE].sets, L1_cache_info[DCACHE].ways,
 116                 L1_cache_info[DCACHE].line_size);
 117         pr_info("L1 D-Cache is %s\n", WRITE_METHOD);
 118         if (L1_cache_info[DCACHE].size != L1_CACHE_BYTES)
 119                 pr_crit
 120                     ("The cache line size(%d) of this processor is not the same as L1_CACHE_BYTES(%d).\n",
 121                      L1_cache_info[DCACHE].size, L1_CACHE_BYTES);
 122 #ifdef CONFIG_CPU_CACHE_ALIASING
 123         {
 124                 int aliasing_num;
 125                 aliasing_num =
 126                     L1_cache_info[ICACHE].size * 1024 / PAGE_SIZE /
 127                     L1_cache_info[ICACHE].ways;
 128                 L1_cache_info[ICACHE].aliasing_num = aliasing_num;
 129                 L1_cache_info[ICACHE].aliasing_mask =
 130                     (aliasing_num - 1) << PAGE_SHIFT;
 131                 aliasing_num =
 132                     L1_cache_info[DCACHE].size * 1024 / PAGE_SIZE /
 133                     L1_cache_info[DCACHE].ways;
 134                 L1_cache_info[DCACHE].aliasing_num = aliasing_num;
 135                 L1_cache_info[DCACHE].aliasing_mask =
 136                     (aliasing_num - 1) << PAGE_SHIFT;
 137         }
 138 #endif
 139 }
 140
 141 static void __init setup_cpuinfo(void)
 142 {
 143         unsigned long tmp = 0, cpu_name;
 144
 145         cpu_dcache_inval_all();
 146         cpu_icache_inval_all();
 147         __nds32__isb();
 148
 149         cpu_id = (__nds32__mfsr(NDS32_SR_CPU_VER) & CPU_VER_mskCPUID) >> CPU_VER_offCPUID;
 150         cpu_name = ((cpu_id) & 0xf0) >> 4;
 151         cpu_series = cpu_name ? cpu_name - 10 + 'A' : 'N';
 152         cpu_id = cpu_id & 0xf;
 153         cpu_rev = (__nds32__mfsr(NDS32_SR_CPU_VER) & CPU_VER_mskREV) >> CPU_VER_offREV;
 154         cpu_cfgid = (__nds32__mfsr(NDS32_SR_CPU_VER) & CPU_VER_mskCFGID) >> CPU_VER_offCFGID;
 155
 156         pr_info("CPU:%c%ld, CPU_VER 0x%08x(id %lu, rev %lu, cfg %lu)\n",
 157                 cpu_series, cpu_id, __nds32__mfsr(NDS32_SR_CPU_VER), cpu_id, cpu_rev, cpu_cfgid);
 158
 159         elf_hwcap |= HWCAP_MFUSR_PC;
 160
 161         if (((__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskBASEV) >> MSC_CFG_offBASEV) == 0) {
 162                 if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskDIV)
 163                         elf_hwcap |= HWCAP_DIV;
 164
 165                 if ((__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskMAC)
 166                     || (cpu_id == 12 && cpu_rev < 4))
 167                         elf_hwcap |= HWCAP_MAC;
 168         } else {
 169                 elf_hwcap |= HWCAP_V2;
 170                 elf_hwcap |= HWCAP_DIV;
 171                 elf_hwcap |= HWCAP_MAC;
 172         }
 173
 174         if (cpu_cfgid & 0x0001)
 175                 elf_hwcap |= HWCAP_EXT;
 176
 177         if (cpu_cfgid & 0x0002)
 178                 elf_hwcap |= HWCAP_BASE16;
 179
 180         if (cpu_cfgid & 0x0004)
 181                 elf_hwcap |= HWCAP_EXT2;
 182
 183         if (cpu_cfgid & 0x0008)
 184                 elf_hwcap |= HWCAP_FPU;
 185
 186         if (cpu_cfgid & 0x0010)
 187                 elf_hwcap |= HWCAP_STRING;
 188
 189         if (__nds32__mfsr(NDS32_SR_MMU_CFG) & MMU_CFG_mskDE)
 190                 endianness = "MSB";
 191         else
 192                 endianness = "LSB";
 193
 194         if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskEDM)
 195                 elf_hwcap |= HWCAP_EDM;
 196
 197         if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskLMDMA)
 198                 elf_hwcap |= HWCAP_LMDMA;
 199
 200         if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskPFM)
 201                 elf_hwcap |= HWCAP_PFM;
 202
 203         if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskHSMP)
 204                 elf_hwcap |= HWCAP_HSMP;
 205
 206         if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskTRACE)
 207                 elf_hwcap |= HWCAP_TRACE;
 208
 209         if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskAUDIO)
 210                 elf_hwcap |= HWCAP_AUDIO;
 211
 212         if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskL2C)
 213                 elf_hwcap |= HWCAP_L2C;
 214
 215         tmp = __nds32__mfsr(NDS32_SR_CACHE_CTL);
 216         if (!IS_ENABLED(CONFIG_CPU_DCACHE_DISABLE))
 217                 tmp |= CACHE_CTL_mskDC_EN;
 218
 219         if (!IS_ENABLED(CONFIG_CPU_ICACHE_DISABLE))
 220                 tmp |= CACHE_CTL_mskIC_EN;
 221         __nds32__mtsr_isb(tmp, NDS32_SR_CACHE_CTL);
 222
 223         dump_cpu_info(smp_processor_id());
 224 }
 225
 226 static void __init setup_memory(void)
 227 {
 228         unsigned long ram_start_pfn;
 229         unsigned long free_ram_start_pfn;
 230         phys_addr_t memory_start, memory_end;
 231         struct memblock_region *region;
 232
 233         memory_end = memory_start = 0;
 234
 235         /* Find main memory where is the kernel */
 236         for_each_memblock(memory, region) {
 237                 memory_start = region->base;
 238                 memory_end = region->base + region->size;
 239                 pr_info("%s: Memory: 0x%x-0x%x\n", __func__,
 240                         memory_start, memory_end);
 241         }
 242
 243         if (!memory_end) {
 244                 panic("No memory!");
 245         }
 246
 247         ram_start_pfn = PFN_UP(memblock_start_of_DRAM());
 248         /* free_ram_start_pfn is first page after kernel */
 249         free_ram_start_pfn = PFN_UP(__pa(&_end));
 250         max_pfn = PFN_DOWN(memblock_end_of_DRAM());
 251         /* it could update max_pfn */
 252         if (max_pfn - ram_start_pfn <= MAXMEM_PFN)
 253                 max_low_pfn = max_pfn;
 254         else {
 255                 max_low_pfn = MAXMEM_PFN + ram_start_pfn;
 256                 if (!IS_ENABLED(CONFIG_HIGHMEM))
 257                         max_pfn = MAXMEM_PFN + ram_start_pfn;
 258         }
 259         /* high_memory is related with VMALLOC */
 260         high_memory = (void *)__va(max_low_pfn * PAGE_SIZE);
 261         min_low_pfn = free_ram_start_pfn;
 262
 263         /*
 264          * initialize the boot-time allocator (with low memory only).
 265          *
 266          * This makes the memory from the end of the kernel to the end of
 267          * RAM usable.
 268          */
 269         memblock_set_bottom_up(true);
 270         memblock_reserve(PFN_PHYS(ram_start_pfn), PFN_PHYS(free_ram_start_pfn - ram_start_pfn));
 271
 272         early_init_fdt_reserve_self();
 273         early_init_fdt_scan_reserved_mem();
 274
 275         memblock_dump_all();
 276 }
 277
 278 void __init setup_arch(char **cmdline_p)
 279 {
 280         early_init_devtree(__atags_pointer ? \
 281                 phys_to_virt(__atags_pointer) : __dtb_start);
 282
 283         setup_cpuinfo();
 284
 285         init_mm.start_code = (unsigned long)&_stext;
 286         init_mm.end_code = (unsigned long)&_etext;
 287         init_mm.end_data = (unsigned long)&_edata;
 288         init_mm.brk = (unsigned long)&_end;
 289
 290         /* setup bootmem allocator */
 291         setup_memory();
 292
 293         /* paging_init() sets up the MMU and marks all pages as reserved */
 294         paging_init();
 295
 296         /* invalidate all TLB entries because the new mapping is created */
 297         __nds32__tlbop_flua();
 298
 299         /* use generic way to parse */
 300         parse_early_param();
 301
 302         unflatten_and_copy_device_tree();
 303
 304         if(IS_ENABLED(CONFIG_VT)) {
 305                 if(IS_ENABLED(CONFIG_DUMMY_CONSOLE))
 306                         conswitchp = &dummy_con;
 307         }
 308
 309         *cmdline_p = boot_command_line;
 310         early_trap_init();
 311 }
 312
 313 static int c_show(struct seq_file *m, void *v)
 314 {
 315         int i;
 316
 317         seq_printf(m, "Processor\t: %c%ld (id %lu, rev %lu, cfg %lu)\n",
 318                    cpu_series, cpu_id, cpu_id, cpu_rev, cpu_cfgid);
 319
 320         seq_printf(m, "L1I\t\t: %luKB/%luS/%luW/%luB\n",
 321                    CACHE_SET(ICACHE) * CACHE_WAY(ICACHE) *
 322                    CACHE_LINE_SIZE(ICACHE) / 1024, CACHE_SET(ICACHE),
 323                    CACHE_WAY(ICACHE), CACHE_LINE_SIZE(ICACHE));
 324
 325         seq_printf(m, "L1D\t\t: %luKB/%luS/%luW/%luB\n",
 326                    CACHE_SET(DCACHE) * CACHE_WAY(DCACHE) *
 327                    CACHE_LINE_SIZE(DCACHE) / 1024, CACHE_SET(DCACHE),
 328                    CACHE_WAY(DCACHE), CACHE_LINE_SIZE(DCACHE));
 329
 330         seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
 331                    loops_per_jiffy / (500000 / HZ),
 332                    (loops_per_jiffy / (5000 / HZ)) % 100);
 333
 334         /* dump out the processor features */
 335         seq_puts(m, "Features\t: ");
 336
 337         for (i = 0; hwcap_str[i]; i++)
 338                 if (elf_hwcap & (1 << i))
 339                         seq_printf(m, "%s ", hwcap_str[i]);
 340
 341         seq_puts(m, "\n\n");
 342
 343         return 0;
 344 }
 345
 346 static void *c_start(struct seq_file *m, loff_t * pos)
 347 {
 348         return *pos < 1 ? (void *)1 : NULL;
 349 }
 350
 351 static void *c_next(struct seq_file *m, void *v, loff_t * pos)
 352 {
 353         ++*pos;
 354         return NULL;
 355 }
 356
 357 static void c_stop(struct seq_file *m, void *v)
 358 {
 359 }
 360
 361 struct seq_operations cpuinfo_op = {
 362         .start = c_start,
 363         .next = c_next,
 364         .stop = c_stop,
 365         .show = c_show
 366 };