arch/mips/rb532/devices.c

   1 /*
   2  *  RouterBoard 500 Platform devices
   3  *
   4  *  Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
   5  *  Copyright (C) 2007 Florian Fainelli <florian@openwrt.org>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License as published by
   9  *  the Free Software Foundation; either version 2 of the License, or
  10  *  (at your option) any later version.
  11  *
  12  *  This program is distributed in the hope that it will be useful,
  13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15  *  GNU General Public License for more details.
  16  */
  17 #include <linux/kernel.h>
  18 #include <linux/init.h>
  19 #include <linux/ctype.h>
  20 #include <linux/string.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/mtd/nand.h>
  23 #include <linux/mtd/mtd.h>
  24 #include <linux/mtd/partitions.h>
  25 #include <linux/gpio_keys.h>
  26 #include <linux/input.h>
  27 #include <linux/serial_8250.h>
  28
  29 #include <asm/bootinfo.h>
  30
  31 #include <asm/mach-rc32434/rc32434.h>
  32 #include <asm/mach-rc32434/dma.h>
  33 #include <asm/mach-rc32434/dma_v.h>
  34 #include <asm/mach-rc32434/eth.h>
  35 #include <asm/mach-rc32434/rb.h>
  36 #include <asm/mach-rc32434/integ.h>
  37 #include <asm/mach-rc32434/gpio.h>
  38 #include <asm/mach-rc32434/irq.h>
  39
  40 #define ETH0_RX_DMA_ADDR  (DMA0_BASE_ADDR + 0 * DMA_CHAN_OFFSET)
  41 #define ETH0_TX_DMA_ADDR  (DMA0_BASE_ADDR + 1 * DMA_CHAN_OFFSET)
  42
  43 extern unsigned int idt_cpu_freq;
  44
  45 static struct mpmc_device dev3;
  46
  47 void set_latch_u5(unsigned char or_mask, unsigned char nand_mask)
  48 {
  49         unsigned long flags;
  50
  51         spin_lock_irqsave(&dev3.lock, flags);
  52
  53         dev3.state = (dev3.state | or_mask) & ~nand_mask;
  54         writeb(dev3.state, dev3.base);
  55
  56         spin_unlock_irqrestore(&dev3.lock, flags);
  57 }
  58 EXPORT_SYMBOL(set_latch_u5);
  59
  60 unsigned char get_latch_u5(void)
  61 {
  62         return dev3.state;
  63 }
  64 EXPORT_SYMBOL(get_latch_u5);
  65
  66 static struct resource rb532_dev3_ctl_res[] = {
  67         {
  68                 .name   = "dev3_ctl",
  69                 .flags  = IORESOURCE_MEM,
  70         }
  71 };
  72
  73 static struct resource korina_dev0_res[] = {
  74         {
  75                 .name = "korina_regs",
  76                 .start = ETH0_BASE_ADDR,
  77                 .end = ETH0_BASE_ADDR + sizeof(struct eth_regs),
  78                 .flags = IORESOURCE_MEM,
  79          }, {
  80                 .name = "korina_rx",
  81                 .start = ETH0_DMA_RX_IRQ,
  82                 .end = ETH0_DMA_RX_IRQ,
  83                 .flags = IORESOURCE_IRQ
  84         }, {
  85                 .name = "korina_tx",
  86                 .start = ETH0_DMA_TX_IRQ,
  87                 .end = ETH0_DMA_TX_IRQ,
  88                 .flags = IORESOURCE_IRQ
  89         }, {
  90                 .name = "korina_ovr",
  91                 .start = ETH0_RX_OVR_IRQ,
  92                 .end = ETH0_RX_OVR_IRQ,
  93                 .flags = IORESOURCE_IRQ
  94         }, {
  95                 .name = "korina_und",
  96                 .start = ETH0_TX_UND_IRQ,
  97                 .end = ETH0_TX_UND_IRQ,
  98                 .flags = IORESOURCE_IRQ
  99         }, {
 100                 .name = "korina_dma_rx",
 101                 .start = ETH0_RX_DMA_ADDR,
 102                 .end = ETH0_RX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
 103                 .flags = IORESOURCE_MEM,
 104          }, {
 105                 .name = "korina_dma_tx",
 106                 .start = ETH0_TX_DMA_ADDR,
 107                 .end = ETH0_TX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
 108                 .flags = IORESOURCE_MEM,
 109          }
 110 };
 111
 112 static struct korina_device korina_dev0_data = {
 113         .name = "korina0",
 114         .mac = {0xde, 0xca, 0xff, 0xc0, 0xff, 0xee}
 115 };
 116
 117 static struct platform_device korina_dev0 = {
 118         .id = -1,
 119         .name = "korina",
 120         .dev.driver_data = &korina_dev0_data,
 121         .resource = korina_dev0_res,
 122         .num_resources = ARRAY_SIZE(korina_dev0_res),
 123 };
 124
 125 static struct resource cf_slot0_res[] = {
 126         {
 127                 .name = "cf_membase",
 128                 .flags = IORESOURCE_MEM
 129         }, {
 130                 .name = "cf_irq",
 131                 .start = (8 + 4 * 32 + CF_GPIO_NUM),    /* 149 */
 132                 .end = (8 + 4 * 32 + CF_GPIO_NUM),
 133                 .flags = IORESOURCE_IRQ
 134         }
 135 };
 136
 137 static struct cf_device cf_slot0_data = {
 138         .gpio_pin = CF_GPIO_NUM
 139 };
 140
 141 static struct platform_device cf_slot0 = {
 142         .id = -1,
 143         .name = "pata-rb532-cf",
 144         .dev.platform_data = &cf_slot0_data,
 145         .resource = cf_slot0_res,
 146         .num_resources = ARRAY_SIZE(cf_slot0_res),
 147 };
 148
 149 /* Resources and device for NAND */
 150 static int rb532_dev_ready(struct mtd_info *mtd)
 151 {
 152         return gpio_get_value(GPIO_RDY);
 153 }
 154
 155 static void rb532_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 156 {
 157         struct nand_chip *chip = mtd->priv;
 158         unsigned char orbits, nandbits;
 159
 160         if (ctrl & NAND_CTRL_CHANGE) {
 161                 orbits = (ctrl & NAND_CLE) << 1;
 162                 orbits |= (ctrl & NAND_ALE) >> 1;
 163
 164                 nandbits = (~ctrl & NAND_CLE) << 1;
 165                 nandbits |= (~ctrl & NAND_ALE) >> 1;
 166
 167                 set_latch_u5(orbits, nandbits);
 168         }
 169         if (cmd != NAND_CMD_NONE)
 170                 writeb(cmd, chip->IO_ADDR_W);
 171 }
 172
 173 static struct resource nand_slot0_res[] = {
 174         [0] = {
 175                 .name = "nand_membase",
 176                 .flags = IORESOURCE_MEM
 177         }
 178 };
 179
 180 static struct platform_nand_data rb532_nand_data = {
 181         .ctrl.dev_ready = rb532_dev_ready,
 182         .ctrl.cmd_ctrl  = rb532_cmd_ctrl,
 183 };
 184
 185 static struct platform_device nand_slot0 = {
 186         .name = "gen_nand",
 187         .id = -1,
 188         .resource = nand_slot0_res,
 189         .num_resources = ARRAY_SIZE(nand_slot0_res),
 190         .dev.platform_data = &rb532_nand_data,
 191 };
 192
 193 static struct mtd_partition rb532_partition_info[] = {
 194         {
 195                 .name = "Routerboard NAND boot",
 196                 .offset = 0,
 197                 .size = 4 * 1024 * 1024,
 198         }, {
 199                 .name = "rootfs",
 200                 .offset = MTDPART_OFS_NXTBLK,
 201                 .size = MTDPART_SIZ_FULL,
 202         }
 203 };
 204
 205 static struct platform_device rb532_led = {
 206         .name = "rb532-led",
 207         .id = -1,
 208 };
 209
 210 static struct gpio_keys_button rb532_gpio_btn[] = {
 211         {
 212                 .gpio = 1,
 213                 .code = BTN_0,
 214                 .desc = "S1",
 215                 .active_low = 1,
 216         }
 217 };
 218
 219 static struct gpio_keys_platform_data rb532_gpio_btn_data = {
 220         .buttons = rb532_gpio_btn,
 221         .nbuttons = ARRAY_SIZE(rb532_gpio_btn),
 222 };
 223
 224 static struct platform_device rb532_button = {
 225         .name   = "gpio-keys",
 226         .id     = -1,
 227         .dev    = {
 228                 .platform_data = &rb532_gpio_btn_data,
 229         }
 230 };
 231
 232 static struct resource rb532_wdt_res[] = {
 233         {
 234                 .name = "rb532_wdt_res",
 235                 .start = INTEG0_BASE_ADDR,
 236                 .end = INTEG0_BASE_ADDR + sizeof(struct integ),
 237                 .flags = IORESOURCE_MEM,
 238         }
 239 };
 240
 241 static struct platform_device rb532_wdt = {
 242         .name           = "rc32434_wdt",
 243         .id             = -1,
 244         .resource       = rb532_wdt_res,
 245         .num_resources  = ARRAY_SIZE(rb532_wdt_res),
 246 };
 247
 248 static struct plat_serial8250_port rb532_uart_res[] = {
 249         {
 250                 .membase        = (char *)KSEG1ADDR(REGBASE + UART0BASE),
 251                 .irq            = UART0_IRQ,
 252                 .regshift       = 2,
 253                 .iotype         = UPIO_MEM,
 254                 .flags          = UPF_BOOT_AUTOCONF,
 255         },
 256         {
 257                 .flags          = 0,
 258         }
 259 };
 260
 261 static struct platform_device rb532_uart = {
 262         .name              = "serial8250",
 263         .id                = PLAT8250_DEV_PLATFORM,
 264         .dev.platform_data = &rb532_uart_res,
 265 };
 266
 267 static struct platform_device *rb532_devs[] = {
 268         &korina_dev0,
 269         &nand_slot0,
 270         &cf_slot0,
 271         &rb532_led,
 272         &rb532_button,
 273         &rb532_uart,
 274         &rb532_wdt
 275 };
 276
 277 static void __init parse_mac_addr(char *macstr)
 278 {
 279         int i, j;
 280         unsigned char result, value;
 281
 282         for (i = 0; i < 6; i++) {
 283                 result = 0;
 284
 285                 if (i != 5 && *(macstr + 2) != ':')
 286                         return;
 287
 288                 for (j = 0; j < 2; j++) {
 289                         if (isxdigit(*macstr)
 290                             && (value =
 291                                 isdigit(*macstr) ? *macstr -
 292                                 '0' : toupper(*macstr) - 'A' + 10) < 16) {
 293                                 result = result * 16 + value;
 294                                 macstr++;
 295                         } else
 296                                 return;
 297                 }
 298
 299                 macstr++;
 300                 korina_dev0_data.mac[i] = result;
 301         }
 302 }
 303
 304
 305 /* NAND definitions */
 306 #define NAND_CHIP_DELAY 25
 307
 308 static void __init rb532_nand_setup(void)
 309 {
 310         switch (mips_machtype) {
 311         case MACH_MIKROTIK_RB532A:
 312                 set_latch_u5(LO_FOFF | LO_CEX,
 313                                 LO_ULED | LO_ALE | LO_CLE | LO_WPX);
 314                 break;
 315         default:
 316                 set_latch_u5(LO_WPX | LO_FOFF | LO_CEX,
 317                                 LO_ULED | LO_ALE | LO_CLE);
 318                 break;
 319         }
 320
 321         /* Setup NAND specific settings */
 322         rb532_nand_data.chip.nr_chips = 1;
 323         rb532_nand_data.chip.nr_partitions = ARRAY_SIZE(rb532_partition_info);
 324         rb532_nand_data.chip.partitions = rb532_partition_info;
 325         rb532_nand_data.chip.chip_delay = NAND_CHIP_DELAY;
 326         rb532_nand_data.chip.options = NAND_NO_AUTOINCR;
 327 }
 328
 329
 330 static int __init plat_setup_devices(void)
 331 {
 332         /* Look for the CF card reader */
 333         if (!readl(IDT434_REG_BASE + DEV1MASK))
 334                 rb532_devs[2] = NULL;   /* disable cf_slot0 at index 2 */
 335         else {
 336                 cf_slot0_res[0].start =
 337                     readl(IDT434_REG_BASE + DEV1BASE);
 338                 cf_slot0_res[0].end = cf_slot0_res[0].start + 0x1000;
 339         }
 340
 341         /* Read the NAND resources from the device controller */
 342         nand_slot0_res[0].start = readl(IDT434_REG_BASE + DEV2BASE);
 343         nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000;
 344
 345         /* Read the third (multi purpose) resources from the DC */
 346         rb532_dev3_ctl_res[0].start = readl(IDT434_REG_BASE + DEV3BASE);
 347         rb532_dev3_ctl_res[0].end = rb532_dev3_ctl_res[0].start + 0x1000;
 348
 349         dev3.base = ioremap_nocache(rb532_dev3_ctl_res[0].start, 0x1000);
 350
 351         if (!dev3.base) {
 352                 printk(KERN_ERR "rb532: cannot remap device controller 3\n");
 353                 return -ENXIO;
 354         }
 355
 356         /* Initialise the NAND device */
 357         rb532_nand_setup();
 358
 359         /* set the uart clock to the current cpu frequency */
 360         rb532_uart_res[0].uartclk = idt_cpu_freq;
 361
 362         return platform_add_devices(rb532_devs, ARRAY_SIZE(rb532_devs));
 363 }
 364
 365 static int __init setup_kmac(char *s)
 366 {
 367         printk(KERN_INFO "korina mac = %s\n", s);
 368         parse_mac_addr(s);
 369         return 0;
 370 }
 371
 372 __setup("kmac=", setup_kmac);
 373
 374 arch_initcall(plat_setup_devices);