2 * Pistachio platform setup
4 * Copyright (C) 2014 Google, Inc.
5 * Copyright (C) 2016 Imagination Technologies
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
12 #include <linux/init.h>
14 #include <linux/kernel.h>
15 #include <linux/of_address.h>
16 #include <linux/of_fdt.h>
17 #include <linux/of_platform.h>
19 #include <asm/cacheflush.h>
20 #include <asm/dma-coherence.h>
21 #include <asm/fw/fw.h>
22 #include <asm/mips-boards/generic.h>
23 #include <asm/mips-cm.h>
24 #include <asm/mips-cpc.h>
26 #include <asm/smp-ops.h>
27 #include <asm/traps.h>
30 * Core revision register decoding
31 * Bits 23 to 20: Major rev
32 * Bits 15 to 8: Minor rev
33 * Bits 7 to 0: Maintenance rev
35 #define PISTACHIO_CORE_REV_REG 0xB81483D0
36 #define PISTACHIO_CORE_REV_A1 0x00100006
37 #define PISTACHIO_CORE_REV_B0 0x00100106
39 const char *get_system_type(void)
44 core_rev = __raw_readl((const void *)PISTACHIO_CORE_REV_REG);
47 case PISTACHIO_CORE_REV_B0:
48 sys_type = "IMG Pistachio SoC (B0)";
51 case PISTACHIO_CORE_REV_A1:
52 sys_type = "IMG Pistachio SoC (A1)";
56 sys_type = "IMG Pistachio SoC";
63 static void __init plat_setup_iocoherency(void)
66 * Kernel has been configured with software coherency
67 * but we might choose to turn it off and use hardware
70 if (mips_cm_numiocu() != 0) {
71 /* Nothing special needs to be done to enable coherency */
72 pr_info("CMP IOCU detected\n");
75 pr_info("Hardware DMA cache coherency disabled\n");
77 pr_info("Hardware DMA cache coherency enabled\n");
80 pr_info("Hardware DMA cache coherency unsupported, but enabled from command line!\n");
82 pr_info("Software DMA cache coherency enabled\n");
86 void __init plat_mem_setup(void)
89 panic("Device-tree not present");
91 __dt_setup_arch((void *)fw_arg1);
93 plat_setup_iocoherency();
96 #define DEFAULT_CPC_BASE_ADDR 0x1bde0000
97 #define DEFAULT_CDMM_BASE_ADDR 0x1bdd0000
99 phys_addr_t mips_cpc_default_phys_base(void)
101 return DEFAULT_CPC_BASE_ADDR;
104 phys_addr_t mips_cdmm_phys_base(void)
106 return DEFAULT_CDMM_BASE_ADDR;
109 static void __init mips_nmi_setup(void)
112 extern char except_vec_nmi;
114 base = cpu_has_veic ?
115 (void *)(CAC_BASE + 0xa80) :
116 (void *)(CAC_BASE + 0x380);
117 memcpy(base, &except_vec_nmi, 0x80);
118 flush_icache_range((unsigned long)base,
119 (unsigned long)base + 0x80);
122 static void __init mips_ejtag_setup(void)
125 extern char except_vec_ejtag_debug;
127 base = cpu_has_veic ?
128 (void *)(CAC_BASE + 0xa00) :
129 (void *)(CAC_BASE + 0x300);
130 memcpy(base, &except_vec_ejtag_debug, 0x80);
131 flush_icache_range((unsigned long)base,
132 (unsigned long)base + 0x80);
135 void __init prom_init(void)
137 board_nmi_handler_setup = mips_nmi_setup;
138 board_ejtag_handler_setup = mips_ejtag_setup;
142 register_cps_smp_ops();
144 pr_info("SoC Type: %s\n", get_system_type());
147 void __init prom_free_prom_memory(void)
151 void __init device_tree_init(void)
153 if (!initial_boot_params)
156 unflatten_and_copy_device_tree();
159 static int __init plat_of_setup(void)
161 if (!of_have_populated_dt())
162 panic("Device tree not present");
164 if (of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL))
165 panic("Failed to populate DT");
169 arch_initcall(plat_of_setup);