2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2005-2009, 2010 Cavium Networks
8 #include <linux/kernel.h>
9 #include <linux/init.h>
10 #include <linux/msi.h>
11 #include <linux/spinlock.h>
12 #include <linux/interrupt.h>
14 #include <asm/octeon/octeon.h>
15 #include <asm/octeon/cvmx-npi-defs.h>
16 #include <asm/octeon/cvmx-pci-defs.h>
17 #include <asm/octeon/cvmx-npei-defs.h>
18 #include <asm/octeon/cvmx-sli-defs.h>
19 #include <asm/octeon/cvmx-pexp-defs.h>
20 #include <asm/octeon/pci-octeon.h>
23 * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is
26 static u64 msi_free_irq_bitmask[4];
29 * Each bit in msi_multiple_irq_bitmask tells that the device using
30 * this bit in msi_free_irq_bitmask is also using the next bit. This
31 * is used so we can disable all of the MSI interrupts when a device
34 static u64 msi_multiple_irq_bitmask[4];
37 * This lock controls updates to msi_free_irq_bitmask and
38 * msi_multiple_irq_bitmask.
40 static DEFINE_SPINLOCK(msi_free_irq_bitmask_lock);
43 * Number of MSI IRQs used. This variable is set up in
44 * the module init time.
46 static int msi_irq_size;
49 * Called when a driver request MSI interrupts instead of the
50 * legacy INT A-D. This routine will allocate multiple interrupts
51 * for MSI devices that support them. A device can override this by
52 * programming the MSI control bits [6:4] before calling
55 * @dev: Device requesting MSI interrupts
56 * @desc: MSI descriptor
58 * Returns 0 on success.
60 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
64 int configured_private_bits;
65 int request_private_bits;
72 * Read the MSI config to figure out how many IRQs this device
73 * wants. Most devices only want 1, which will give
74 * configured_private_bits and request_private_bits equal 0.
76 pci_read_config_word(dev, desc->msi_attrib.pos + PCI_MSI_FLAGS,
80 * If the number of private bits has been configured then use
81 * that value instead of the requested number. This gives the
82 * driver the chance to override the number of interrupts
83 * before calling pci_enable_msi().
85 configured_private_bits = (control & PCI_MSI_FLAGS_QSIZE) >> 4;
86 if (configured_private_bits == 0) {
87 /* Nothing is configured, so use the hardware requested size */
88 request_private_bits = (control & PCI_MSI_FLAGS_QMASK) >> 1;
91 * Use the number of configured bits, assuming the
92 * driver wanted to override the hardware request
95 request_private_bits = configured_private_bits;
99 * The PCI 2.3 spec mandates that there are at most 32
100 * interrupts. If this device asks for more, only give it one.
102 if (request_private_bits > 5)
103 request_private_bits = 0;
107 * The IRQs have to be aligned on a power of two based on the
108 * number being requested.
110 irq_step = 1 << request_private_bits;
112 /* Mask with one bit for each IRQ */
113 search_mask = (1 << irq_step) - 1;
116 * We're going to search msi_free_irq_bitmask_lock for zero
117 * bits. This represents an MSI interrupt number that isn't in
120 spin_lock(&msi_free_irq_bitmask_lock);
121 for (index = 0; index < msi_irq_size/64; index++) {
122 for (irq = 0; irq < 64; irq += irq_step) {
123 if ((msi_free_irq_bitmask[index] & (search_mask << irq)) == 0) {
124 msi_free_irq_bitmask[index] |= search_mask << irq;
125 msi_multiple_irq_bitmask[index] |= (search_mask >> 1) << irq;
126 goto msi_irq_allocated;
131 spin_unlock(&msi_free_irq_bitmask_lock);
133 /* Make sure the search for available interrupts didn't fail */
135 if (request_private_bits) {
136 pr_err("arch_setup_msi_irq: Unable to find %d free interrupts, trying just one",
137 1 << request_private_bits);
138 request_private_bits = 0;
141 panic("arch_setup_msi_irq: Unable to find a free MSI interrupt");
144 /* MSI interrupts start at logical IRQ OCTEON_IRQ_MSI_BIT0 */
146 irq += OCTEON_IRQ_MSI_BIT0;
148 switch (octeon_dma_bar_type) {
149 case OCTEON_DMA_BAR_TYPE_SMALL:
150 /* When not using big bar, Bar 0 is based at 128MB */
152 ((128ul << 20) + CVMX_PCI_MSI_RCV) & 0xffffffff;
153 msg.address_hi = ((128ul << 20) + CVMX_PCI_MSI_RCV) >> 32;
155 case OCTEON_DMA_BAR_TYPE_BIG:
156 /* When using big bar, Bar 0 is based at 0 */
157 msg.address_lo = (0 + CVMX_PCI_MSI_RCV) & 0xffffffff;
158 msg.address_hi = (0 + CVMX_PCI_MSI_RCV) >> 32;
160 case OCTEON_DMA_BAR_TYPE_PCIE:
161 /* When using PCIe, Bar 0 is based at 0 */
162 /* FIXME CVMX_NPEI_MSI_RCV* other than 0? */
163 msg.address_lo = (0 + CVMX_NPEI_PCIE_MSI_RCV) & 0xffffffff;
164 msg.address_hi = (0 + CVMX_NPEI_PCIE_MSI_RCV) >> 32;
166 case OCTEON_DMA_BAR_TYPE_PCIE2:
167 /* When using PCIe2, Bar 0 is based at 0 */
168 msg.address_lo = (0 + CVMX_SLI_PCIE_MSI_RCV) & 0xffffffff;
169 msg.address_hi = (0 + CVMX_SLI_PCIE_MSI_RCV) >> 32;
172 panic("arch_setup_msi_irq: Invalid octeon_dma_bar_type");
174 msg.data = irq - OCTEON_IRQ_MSI_BIT0;
176 /* Update the number of IRQs the device has available to it */
177 control &= ~PCI_MSI_FLAGS_QSIZE;
178 control |= request_private_bits << 4;
179 pci_write_config_word(dev, desc->msi_attrib.pos + PCI_MSI_FLAGS,
182 irq_set_msi_desc(irq, desc);
183 write_msi_msg(irq, &msg);
187 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
189 struct msi_desc *entry;
193 * MSI-X is not supported.
195 if (type == PCI_CAP_ID_MSIX)
199 * If an architecture wants to support multiple MSI, it needs to
200 * override arch_setup_msi_irqs()
202 if (type == PCI_CAP_ID_MSI && nvec > 1)
205 list_for_each_entry(entry, &dev->msi_list, list) {
206 ret = arch_setup_msi_irq(dev, entry);
217 * Called when a device no longer needs its MSI interrupts. All
218 * MSI interrupts for the device are freed.
220 * @irq: The devices first irq number. There may be multple in sequence.
222 void arch_teardown_msi_irq(unsigned int irq)
229 if ((irq < OCTEON_IRQ_MSI_BIT0)
230 || (irq > msi_irq_size + OCTEON_IRQ_MSI_BIT0))
231 panic("arch_teardown_msi_irq: Attempted to teardown illegal "
232 "MSI interrupt (%d)", irq);
234 irq -= OCTEON_IRQ_MSI_BIT0;
239 * Count the number of IRQs we need to free by looking at the
240 * msi_multiple_irq_bitmask. Each bit set means that the next
241 * IRQ is also owned by this device.
244 while ((irq0 + number_irqs < 64) &&
245 (msi_multiple_irq_bitmask[index]
246 & (1ull << (irq0 + number_irqs))))
249 /* Mask with one bit for each IRQ */
250 bitmask = (1 << number_irqs) - 1;
251 /* Shift the mask to the correct bit location */
253 if ((msi_free_irq_bitmask[index] & bitmask) != bitmask)
254 panic("arch_teardown_msi_irq: Attempted to teardown MSI "
255 "interrupt (%d) not in use", irq);
257 /* Checks are done, update the in use bitmask */
258 spin_lock(&msi_free_irq_bitmask_lock);
259 msi_free_irq_bitmask[index] &= ~bitmask;
260 msi_multiple_irq_bitmask[index] &= ~bitmask;
261 spin_unlock(&msi_free_irq_bitmask_lock);
264 static DEFINE_RAW_SPINLOCK(octeon_irq_msi_lock);
266 static u64 msi_rcv_reg[4];
267 static u64 mis_ena_reg[4];
269 static void octeon_irq_msi_enable_pcie(struct irq_data *data)
273 int msi_number = data->irq - OCTEON_IRQ_MSI_BIT0;
274 int irq_index = msi_number >> 6;
275 int irq_bit = msi_number & 0x3f;
277 raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags);
278 en = cvmx_read_csr(mis_ena_reg[irq_index]);
279 en |= 1ull << irq_bit;
280 cvmx_write_csr(mis_ena_reg[irq_index], en);
281 cvmx_read_csr(mis_ena_reg[irq_index]);
282 raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
285 static void octeon_irq_msi_disable_pcie(struct irq_data *data)
289 int msi_number = data->irq - OCTEON_IRQ_MSI_BIT0;
290 int irq_index = msi_number >> 6;
291 int irq_bit = msi_number & 0x3f;
293 raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags);
294 en = cvmx_read_csr(mis_ena_reg[irq_index]);
295 en &= ~(1ull << irq_bit);
296 cvmx_write_csr(mis_ena_reg[irq_index], en);
297 cvmx_read_csr(mis_ena_reg[irq_index]);
298 raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
301 static struct irq_chip octeon_irq_chip_msi_pcie = {
303 .irq_enable = octeon_irq_msi_enable_pcie,
304 .irq_disable = octeon_irq_msi_disable_pcie,
307 static void octeon_irq_msi_enable_pci(struct irq_data *data)
310 * Octeon PCI doesn't have the ability to mask/unmask MSI
311 * interrupts individually. Instead of masking/unmasking them
312 * in groups of 16, we simple assume MSI devices are well
313 * behaved. MSI interrupts are always enable and the ACK is
314 * assumed to be enough
318 static void octeon_irq_msi_disable_pci(struct irq_data *data)
320 /* See comment in enable */
323 static struct irq_chip octeon_irq_chip_msi_pci = {
325 .irq_enable = octeon_irq_msi_enable_pci,
326 .irq_disable = octeon_irq_msi_disable_pci,
330 * Called by the interrupt handling code when an MSI interrupt
333 static irqreturn_t __octeon_msi_do_interrupt(int index, u64 msi_bits)
338 bit = fls64(msi_bits);
341 /* Acknowledge it first. */
342 cvmx_write_csr(msi_rcv_reg[index], 1ull << bit);
344 irq = bit + OCTEON_IRQ_MSI_BIT0 + 64 * index;
351 #define OCTEON_MSI_INT_HANDLER_X(x) \
352 static irqreturn_t octeon_msi_interrupt##x(int cpl, void *dev_id) \
354 u64 msi_bits = cvmx_read_csr(msi_rcv_reg[(x)]); \
355 return __octeon_msi_do_interrupt((x), msi_bits); \
359 * Create octeon_msi_interrupt{0-3} function body
361 OCTEON_MSI_INT_HANDLER_X(0);
362 OCTEON_MSI_INT_HANDLER_X(1);
363 OCTEON_MSI_INT_HANDLER_X(2);
364 OCTEON_MSI_INT_HANDLER_X(3);
367 * Initializes the MSI interrupt handling code
369 int __init octeon_msi_initialize(void)
372 struct irq_chip *msi;
374 if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_PCIE) {
375 msi_rcv_reg[0] = CVMX_PEXP_NPEI_MSI_RCV0;
376 msi_rcv_reg[1] = CVMX_PEXP_NPEI_MSI_RCV1;
377 msi_rcv_reg[2] = CVMX_PEXP_NPEI_MSI_RCV2;
378 msi_rcv_reg[3] = CVMX_PEXP_NPEI_MSI_RCV3;
379 mis_ena_reg[0] = CVMX_PEXP_NPEI_MSI_ENB0;
380 mis_ena_reg[1] = CVMX_PEXP_NPEI_MSI_ENB1;
381 mis_ena_reg[2] = CVMX_PEXP_NPEI_MSI_ENB2;
382 mis_ena_reg[3] = CVMX_PEXP_NPEI_MSI_ENB3;
383 msi = &octeon_irq_chip_msi_pcie;
385 msi_rcv_reg[0] = CVMX_NPI_NPI_MSI_RCV;
386 #define INVALID_GENERATE_ADE 0x8700000000000000ULL;
387 msi_rcv_reg[1] = INVALID_GENERATE_ADE;
388 msi_rcv_reg[2] = INVALID_GENERATE_ADE;
389 msi_rcv_reg[3] = INVALID_GENERATE_ADE;
390 mis_ena_reg[0] = INVALID_GENERATE_ADE;
391 mis_ena_reg[1] = INVALID_GENERATE_ADE;
392 mis_ena_reg[2] = INVALID_GENERATE_ADE;
393 mis_ena_reg[3] = INVALID_GENERATE_ADE;
394 msi = &octeon_irq_chip_msi_pci;
397 for (irq = OCTEON_IRQ_MSI_BIT0; irq <= OCTEON_IRQ_MSI_LAST; irq++)
398 irq_set_chip_and_handler(irq, msi, handle_simple_irq);
400 if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
401 if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt0,
402 0, "MSI[0:63]", octeon_msi_interrupt0))
403 panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed");
405 if (request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt1,
406 0, "MSI[64:127]", octeon_msi_interrupt1))
407 panic("request_irq(OCTEON_IRQ_PCI_MSI1) failed");
409 if (request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt2,
410 0, "MSI[127:191]", octeon_msi_interrupt2))
411 panic("request_irq(OCTEON_IRQ_PCI_MSI2) failed");
413 if (request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt3,
414 0, "MSI[192:255]", octeon_msi_interrupt3))
415 panic("request_irq(OCTEON_IRQ_PCI_MSI3) failed");
418 } else if (octeon_is_pci_host()) {
419 if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt0,
420 0, "MSI[0:15]", octeon_msi_interrupt0))
421 panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed");
423 if (request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt0,
424 0, "MSI[16:31]", octeon_msi_interrupt0))
425 panic("request_irq(OCTEON_IRQ_PCI_MSI1) failed");
427 if (request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt0,
428 0, "MSI[32:47]", octeon_msi_interrupt0))
429 panic("request_irq(OCTEON_IRQ_PCI_MSI2) failed");
431 if (request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt0,
432 0, "MSI[48:63]", octeon_msi_interrupt0))
433 panic("request_irq(OCTEON_IRQ_PCI_MSI3) failed");
438 subsys_initcall(octeon_msi_initialize);