2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
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35 #include <linux/init.h>
36 #include <linux/kernel.h>
37 #include <linux/threads.h>
40 #include <asm/asm-offsets.h>
41 #include <asm/mipsregs.h>
42 #include <asm/addrspace.h>
43 #include <asm/string.h>
45 #include <asm/netlogic/haldefs.h>
46 #include <asm/netlogic/common.h>
47 #include <asm/netlogic/mips-extns.h>
49 #include <asm/netlogic/xlp-hal/iomap.h>
50 #include <asm/netlogic/xlp-hal/pic.h>
51 #include <asm/netlogic/xlp-hal/xlp.h>
52 #include <asm/netlogic/xlp-hal/sys.h>
54 static int xlp_wakeup_core(uint64_t sysbase, int core)
56 uint32_t coremask, value;
59 coremask = (1 << core);
61 /* Enable CPU clock */
62 value = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL);
64 nlm_write_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL, value);
66 /* Remove CPU Reset */
67 value = nlm_read_sys_reg(sysbase, SYS_CPU_RESET);
69 nlm_write_sys_reg(sysbase, SYS_CPU_RESET, value);
71 /* Poll for CPU to mark itself coherent */
74 value = nlm_read_sys_reg(sysbase, SYS_CPU_NONCOHERENT_MODE);
75 } while ((value & coremask) != 0 && --count > 0);
80 static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask)
82 uint64_t syspcibase, sysbase;
86 for (n = 0; n < 4; n++) {
87 syspcibase = nlm_get_sys_pcibase(n);
88 if (nlm_read_reg(syspcibase, 0) == 0xffffffff)
91 /* read cores in reset from SYS and account for boot cpu */
92 sysbase = nlm_get_sys_regbase(n);
93 syscoremask = nlm_read_sys_reg(sysbase, SYS_CPU_RESET);
97 for (core = 0; core < 8; core++) {
98 /* see if the core exists */
99 if ((syscoremask & (1 << core)) == 0)
102 /* see if at least the first thread is enabled */
103 if (!cpumask_test_cpu((n * 8 + core) * 4, wakeup_mask))
106 /* wake up the core */
107 if (!xlp_wakeup_core(sysbase, core))
108 pr_err("Failed to enable core %d\n", core);
113 void xlp_wakeup_secondary_cpus()
116 * In case of u-boot, the secondaries are in reset
117 * first wakeup core 0 threads
119 xlp_boot_core0_siblings();
121 /* now get other cores out of reset */
122 xlp_enable_secondary_cores(&nlm_cpumask);