2 * Just-In-Time compiler for BPF filters on MIPS
4 * Copyright (c) 2014 Imagination Technologies Ltd.
5 * Author: Markos Chandras <markos.chandras@imgtec.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; version 2 of the License.
12 #include <linux/bitops.h>
13 #include <linux/compiler.h>
14 #include <linux/errno.h>
15 #include <linux/filter.h>
16 #include <linux/if_vlan.h>
17 #include <linux/kconfig.h>
18 #include <linux/moduleloader.h>
19 #include <linux/netdevice.h>
20 #include <linux/string.h>
21 #include <linux/slab.h>
22 #include <linux/types.h>
23 #include <asm/bitops.h>
24 #include <asm/cacheflush.h>
25 #include <asm/cpu-features.h>
32 * s0 1st scratch register
33 * s1 2nd scratch register
40 * On entry (*bpf_func)(*skb, *filter)
41 * a0 = MIPS_R_A0 = skb;
42 * a1 = MIPS_R_A1 = filter;
54 * saved reg 0 <-- r_sp
59 * <--------------------- len ------------------------>
60 * <--skb-len(r_skb_hl)-->< ----- skb->data_len ------>
61 * ----------------------------------------------------
63 * ----------------------------------------------------
66 #define RSIZE (sizeof(unsigned long))
67 #define ptr typeof(unsigned long)
69 /* ABI specific return values */
70 #ifdef CONFIG_32BIT /* O32 */
71 #ifdef CONFIG_CPU_LITTLE_ENDIAN
72 #define r_err MIPS_R_V1
73 #define r_val MIPS_R_V0
74 #else /* CONFIG_CPU_LITTLE_ENDIAN */
75 #define r_err MIPS_R_V0
76 #define r_val MIPS_R_V1
79 #define r_err MIPS_R_V0
80 #define r_val MIPS_R_V0
83 #define r_ret MIPS_R_V0
86 * Use 2 scratch registers to avoid pipeline interlocks.
87 * There is no overhead during epilogue and prologue since
88 * any of the $s0-$s6 registers will only be preserved if
89 * they are going to actually be used.
91 #define r_s0 MIPS_R_S0 /* scratch reg 1 */
92 #define r_s1 MIPS_R_S1 /* scratch reg 2 */
93 #define r_off MIPS_R_S2
96 #define r_skb MIPS_R_S5
98 #define r_tmp_imm MIPS_R_T6 /* No need to preserve this */
99 #define r_tmp MIPS_R_T7 /* No need to preserve this */
100 #define r_zero MIPS_R_ZERO
101 #define r_sp MIPS_R_SP
102 #define r_ra MIPS_R_RA
104 #define SCRATCH_OFF(k) (4 * (k))
107 #define SEEN_CALL (1 << BPF_MEMWORDS)
108 #define SEEN_SREG_SFT (BPF_MEMWORDS + 1)
109 #define SEEN_SREG_BASE (1 << SEEN_SREG_SFT)
110 #define SEEN_SREG(x) (SEEN_SREG_BASE << (x))
111 #define SEEN_S0 SEEN_SREG(0)
112 #define SEEN_S1 SEEN_SREG(1)
113 #define SEEN_OFF SEEN_SREG(2)
114 #define SEEN_A SEEN_SREG(3)
115 #define SEEN_X SEEN_SREG(4)
116 #define SEEN_SKB SEEN_SREG(5)
117 #define SEEN_MEM SEEN_SREG(6)
119 /* Arguments used by JIT */
120 #define ARGS_USED_BY_JIT 2 /* only applicable to 64-bit */
122 #define SBIT(x) (1 << (x)) /* Signed version of BIT() */
125 * struct jit_ctx - JIT context
126 * @skf: The sk_filter
127 * @prologue_bytes: Number of bytes for prologue
128 * @idx: Instruction index
130 * @offsets: Instruction offsets
131 * @target: Memory location for the compiled filter
134 const struct bpf_prog *skf;
135 unsigned int prologue_bytes;
143 static inline int optimize_div(u32 *k)
145 /* power of 2 divides can be implemented with right shift */
146 if (!(*k & (*k-1))) {
154 static inline void emit_jit_reg_move(ptr dst, ptr src, struct jit_ctx *ctx);
156 /* Simply emit the instruction if the JIT memory space has been allocated */
157 #define emit_instr(ctx, func, ...) \
159 if ((ctx)->target != NULL) { \
160 u32 *p = &(ctx)->target[ctx->idx]; \
161 uasm_i_##func(&p, ##__VA_ARGS__); \
166 /* Determine if immediate is within the 16-bit signed range */
167 static inline bool is_range16(s32 imm)
169 return !(imm >= SBIT(15) || imm < -SBIT(15));
172 static inline void emit_addu(unsigned int dst, unsigned int src1,
173 unsigned int src2, struct jit_ctx *ctx)
175 emit_instr(ctx, addu, dst, src1, src2);
178 static inline void emit_nop(struct jit_ctx *ctx)
180 emit_instr(ctx, nop);
183 /* Load a u32 immediate to a register */
184 static inline void emit_load_imm(unsigned int dst, u32 imm, struct jit_ctx *ctx)
186 if (ctx->target != NULL) {
187 /* addiu can only handle s16 */
188 if (!is_range16(imm)) {
189 u32 *p = &ctx->target[ctx->idx];
190 uasm_i_lui(&p, r_tmp_imm, (s32)imm >> 16);
191 p = &ctx->target[ctx->idx + 1];
192 uasm_i_ori(&p, dst, r_tmp_imm, imm & 0xffff);
194 u32 *p = &ctx->target[ctx->idx];
195 uasm_i_addiu(&p, dst, r_zero, imm);
200 if (!is_range16(imm))
204 static inline void emit_or(unsigned int dst, unsigned int src1,
205 unsigned int src2, struct jit_ctx *ctx)
207 emit_instr(ctx, or, dst, src1, src2);
210 static inline void emit_ori(unsigned int dst, unsigned src, u32 imm,
213 if (imm >= BIT(16)) {
214 emit_load_imm(r_tmp, imm, ctx);
215 emit_or(dst, src, r_tmp, ctx);
217 emit_instr(ctx, ori, dst, src, imm);
222 static inline void emit_daddu(unsigned int dst, unsigned int src1,
223 unsigned int src2, struct jit_ctx *ctx)
225 emit_instr(ctx, daddu, dst, src1, src2);
228 static inline void emit_daddiu(unsigned int dst, unsigned int src,
229 int imm, struct jit_ctx *ctx)
232 * Only used for stack, so the imm is relatively small
233 * and it fits in 15-bits
235 emit_instr(ctx, daddiu, dst, src, imm);
238 static inline void emit_addiu(unsigned int dst, unsigned int src,
239 u32 imm, struct jit_ctx *ctx)
241 if (!is_range16(imm)) {
242 emit_load_imm(r_tmp, imm, ctx);
243 emit_addu(dst, r_tmp, src, ctx);
245 emit_instr(ctx, addiu, dst, src, imm);
249 static inline void emit_and(unsigned int dst, unsigned int src1,
250 unsigned int src2, struct jit_ctx *ctx)
252 emit_instr(ctx, and, dst, src1, src2);
255 static inline void emit_andi(unsigned int dst, unsigned int src,
256 u32 imm, struct jit_ctx *ctx)
258 /* If imm does not fit in u16 then load it to register */
259 if (imm >= BIT(16)) {
260 emit_load_imm(r_tmp, imm, ctx);
261 emit_and(dst, src, r_tmp, ctx);
263 emit_instr(ctx, andi, dst, src, imm);
267 static inline void emit_xor(unsigned int dst, unsigned int src1,
268 unsigned int src2, struct jit_ctx *ctx)
270 emit_instr(ctx, xor, dst, src1, src2);
273 static inline void emit_xori(ptr dst, ptr src, u32 imm, struct jit_ctx *ctx)
275 /* If imm does not fit in u16 then load it to register */
276 if (imm >= BIT(16)) {
277 emit_load_imm(r_tmp, imm, ctx);
278 emit_xor(dst, src, r_tmp, ctx);
280 emit_instr(ctx, xori, dst, src, imm);
284 static inline void emit_stack_offset(int offset, struct jit_ctx *ctx)
286 if (config_enabled(CONFIG_64BIT))
287 emit_instr(ctx, daddiu, r_sp, r_sp, offset);
289 emit_instr(ctx, addiu, r_sp, r_sp, offset);
293 static inline void emit_subu(unsigned int dst, unsigned int src1,
294 unsigned int src2, struct jit_ctx *ctx)
296 emit_instr(ctx, subu, dst, src1, src2);
299 static inline void emit_neg(unsigned int reg, struct jit_ctx *ctx)
301 emit_subu(reg, r_zero, reg, ctx);
304 static inline void emit_sllv(unsigned int dst, unsigned int src,
305 unsigned int sa, struct jit_ctx *ctx)
307 emit_instr(ctx, sllv, dst, src, sa);
310 static inline void emit_sll(unsigned int dst, unsigned int src,
311 unsigned int sa, struct jit_ctx *ctx)
313 /* sa is 5-bits long */
315 /* Shifting >= 32 results in zero */
316 emit_jit_reg_move(dst, r_zero, ctx);
318 emit_instr(ctx, sll, dst, src, sa);
321 static inline void emit_srlv(unsigned int dst, unsigned int src,
322 unsigned int sa, struct jit_ctx *ctx)
324 emit_instr(ctx, srlv, dst, src, sa);
327 static inline void emit_srl(unsigned int dst, unsigned int src,
328 unsigned int sa, struct jit_ctx *ctx)
330 /* sa is 5-bits long */
332 /* Shifting >= 32 results in zero */
333 emit_jit_reg_move(dst, r_zero, ctx);
335 emit_instr(ctx, srl, dst, src, sa);
338 static inline void emit_slt(unsigned int dst, unsigned int src1,
339 unsigned int src2, struct jit_ctx *ctx)
341 emit_instr(ctx, slt, dst, src1, src2);
344 static inline void emit_sltu(unsigned int dst, unsigned int src1,
345 unsigned int src2, struct jit_ctx *ctx)
347 emit_instr(ctx, sltu, dst, src1, src2);
350 static inline void emit_sltiu(unsigned dst, unsigned int src,
351 unsigned int imm, struct jit_ctx *ctx)
353 /* 16 bit immediate */
354 if (!is_range16((s32)imm)) {
355 emit_load_imm(r_tmp, imm, ctx);
356 emit_sltu(dst, src, r_tmp, ctx);
358 emit_instr(ctx, sltiu, dst, src, imm);
363 /* Store register on the stack */
364 static inline void emit_store_stack_reg(ptr reg, ptr base,
368 if (config_enabled(CONFIG_64BIT))
369 emit_instr(ctx, sd, reg, offset, base);
371 emit_instr(ctx, sw, reg, offset, base);
374 static inline void emit_store(ptr reg, ptr base, unsigned int offset,
377 emit_instr(ctx, sw, reg, offset, base);
380 static inline void emit_load_stack_reg(ptr reg, ptr base,
384 if (config_enabled(CONFIG_64BIT))
385 emit_instr(ctx, ld, reg, offset, base);
387 emit_instr(ctx, lw, reg, offset, base);
390 static inline void emit_load(unsigned int reg, unsigned int base,
391 unsigned int offset, struct jit_ctx *ctx)
393 emit_instr(ctx, lw, reg, offset, base);
396 static inline void emit_load_byte(unsigned int reg, unsigned int base,
397 unsigned int offset, struct jit_ctx *ctx)
399 emit_instr(ctx, lb, reg, offset, base);
402 static inline void emit_half_load(unsigned int reg, unsigned int base,
403 unsigned int offset, struct jit_ctx *ctx)
405 emit_instr(ctx, lh, reg, offset, base);
408 static inline void emit_mul(unsigned int dst, unsigned int src1,
409 unsigned int src2, struct jit_ctx *ctx)
411 emit_instr(ctx, mul, dst, src1, src2);
414 static inline void emit_div(unsigned int dst, unsigned int src,
417 if (ctx->target != NULL) {
418 u32 *p = &ctx->target[ctx->idx];
419 uasm_i_divu(&p, dst, src);
420 p = &ctx->target[ctx->idx + 1];
421 uasm_i_mflo(&p, dst);
423 ctx->idx += 2; /* 2 insts */
426 static inline void emit_mod(unsigned int dst, unsigned int src,
429 if (ctx->target != NULL) {
430 u32 *p = &ctx->target[ctx->idx];
431 uasm_i_divu(&p, dst, src);
432 p = &ctx->target[ctx->idx + 1];
433 uasm_i_mflo(&p, dst);
435 ctx->idx += 2; /* 2 insts */
438 static inline void emit_dsll(unsigned int dst, unsigned int src,
439 unsigned int sa, struct jit_ctx *ctx)
441 emit_instr(ctx, dsll, dst, src, sa);
444 static inline void emit_dsrl32(unsigned int dst, unsigned int src,
445 unsigned int sa, struct jit_ctx *ctx)
447 emit_instr(ctx, dsrl32, dst, src, sa);
450 static inline void emit_wsbh(unsigned int dst, unsigned int src,
453 emit_instr(ctx, wsbh, dst, src);
456 /* load pointer to register */
457 static inline void emit_load_ptr(unsigned int dst, unsigned int src,
458 int imm, struct jit_ctx *ctx)
460 /* src contains the base addr of the 32/64-pointer */
461 if (config_enabled(CONFIG_64BIT))
462 emit_instr(ctx, ld, dst, imm, src);
464 emit_instr(ctx, lw, dst, imm, src);
467 /* load a function pointer to register */
468 static inline void emit_load_func(unsigned int reg, ptr imm,
471 if (config_enabled(CONFIG_64BIT)) {
472 /* At this point imm is always 64-bit */
473 emit_load_imm(r_tmp, (u64)imm >> 32, ctx);
474 emit_dsll(r_tmp_imm, r_tmp, 16, ctx); /* left shift by 16 */
475 emit_ori(r_tmp, r_tmp_imm, (imm >> 16) & 0xffff, ctx);
476 emit_dsll(r_tmp_imm, r_tmp, 16, ctx); /* left shift by 16 */
477 emit_ori(reg, r_tmp_imm, imm & 0xffff, ctx);
479 emit_load_imm(reg, imm, ctx);
483 /* Move to real MIPS register */
484 static inline void emit_reg_move(ptr dst, ptr src, struct jit_ctx *ctx)
486 if (config_enabled(CONFIG_64BIT))
487 emit_daddu(dst, src, r_zero, ctx);
489 emit_addu(dst, src, r_zero, ctx);
492 /* Move to JIT (32-bit) register */
493 static inline void emit_jit_reg_move(ptr dst, ptr src, struct jit_ctx *ctx)
495 emit_addu(dst, src, r_zero, ctx);
498 /* Compute the immediate value for PC-relative branches. */
499 static inline u32 b_imm(unsigned int tgt, struct jit_ctx *ctx)
501 if (ctx->target == NULL)
505 * We want a pc-relative branch. We only do forward branches
506 * so tgt is always after pc. tgt is the instruction offset
507 * we want to jump to.
510 * I: target_offset <- sign_extend(offset)
511 * I+1: PC += target_offset (delay slot)
513 * ctx->idx currently points to the branch instruction
514 * but the offset is added to the delay slot so we need
517 return ctx->offsets[tgt] -
518 (ctx->idx * 4 - ctx->prologue_bytes) - 4;
521 static inline void emit_bcond(int cond, unsigned int reg1, unsigned int reg2,
522 unsigned int imm, struct jit_ctx *ctx)
524 if (ctx->target != NULL) {
525 u32 *p = &ctx->target[ctx->idx];
529 uasm_i_beq(&p, reg1, reg2, imm);
532 uasm_i_bne(&p, reg1, reg2, imm);
538 pr_warn("%s: Unhandled branch conditional: %d\n",
545 static inline void emit_b(unsigned int imm, struct jit_ctx *ctx)
547 emit_bcond(MIPS_COND_ALL, r_zero, r_zero, imm, ctx);
550 static inline void emit_jalr(unsigned int link, unsigned int reg,
553 emit_instr(ctx, jalr, link, reg);
556 static inline void emit_jr(unsigned int reg, struct jit_ctx *ctx)
558 emit_instr(ctx, jr, reg);
561 static inline u16 align_sp(unsigned int num)
563 /* Double word alignment for 32-bit, quadword for 64-bit */
564 unsigned int align = config_enabled(CONFIG_64BIT) ? 16 : 8;
565 num = (num + (align - 1)) & -align;
569 static bool is_load_to_a(u16 inst)
572 case BPF_LD | BPF_W | BPF_LEN:
573 case BPF_LD | BPF_W | BPF_ABS:
574 case BPF_LD | BPF_H | BPF_ABS:
575 case BPF_LD | BPF_B | BPF_ABS:
582 static void save_bpf_jit_regs(struct jit_ctx *ctx, unsigned offset)
584 int i = 0, real_off = 0;
585 u32 sflags, tmp_flags;
587 /* Adjust the stack pointer */
588 emit_stack_offset(-align_sp(offset), ctx);
590 if (ctx->flags & SEEN_CALL) {
591 /* Argument save area */
592 if (config_enabled(CONFIG_64BIT))
593 /* Bottom of current frame */
594 real_off = align_sp(offset) - RSIZE;
596 /* Top of previous frame */
597 real_off = align_sp(offset) + RSIZE;
598 emit_store_stack_reg(MIPS_R_A0, r_sp, real_off, ctx);
599 emit_store_stack_reg(MIPS_R_A1, r_sp, real_off + RSIZE, ctx);
604 tmp_flags = sflags = ctx->flags >> SEEN_SREG_SFT;
605 /* sflags is essentially a bitmap */
607 if ((sflags >> i) & 0x1) {
608 emit_store_stack_reg(MIPS_R_S0 + i, r_sp, real_off,
616 /* save return address */
617 if (ctx->flags & SEEN_CALL) {
618 emit_store_stack_reg(r_ra, r_sp, real_off, ctx);
622 /* Setup r_M leaving the alignment gap if necessary */
623 if (ctx->flags & SEEN_MEM) {
624 if (real_off % (RSIZE * 2))
626 if (config_enabled(CONFIG_64BIT))
627 emit_daddiu(r_M, r_sp, real_off, ctx);
629 emit_addiu(r_M, r_sp, real_off, ctx);
633 static void restore_bpf_jit_regs(struct jit_ctx *ctx,
637 u32 sflags, tmp_flags;
639 if (ctx->flags & SEEN_CALL) {
640 if (config_enabled(CONFIG_64BIT))
641 /* Bottom of current frame */
642 real_off = align_sp(offset) - RSIZE;
644 /* Top of previous frame */
645 real_off = align_sp(offset) + RSIZE;
646 emit_load_stack_reg(MIPS_R_A0, r_sp, real_off, ctx);
647 emit_load_stack_reg(MIPS_R_A1, r_sp, real_off + RSIZE, ctx);
652 tmp_flags = sflags = ctx->flags >> SEEN_SREG_SFT;
653 /* sflags is a bitmap */
656 if ((sflags >> i) & 0x1) {
657 emit_load_stack_reg(MIPS_R_S0 + i, r_sp, real_off,
665 /* restore return address */
666 if (ctx->flags & SEEN_CALL)
667 emit_load_stack_reg(r_ra, r_sp, real_off, ctx);
669 /* Restore the sp and discard the scrach memory */
670 emit_stack_offset(align_sp(offset), ctx);
673 static unsigned int get_stack_depth(struct jit_ctx *ctx)
678 /* How may s* regs do we need to preserved? */
679 sp_off += hweight32(ctx->flags >> SEEN_SREG_SFT) * RSIZE;
681 if (ctx->flags & SEEN_MEM)
682 sp_off += 4 * BPF_MEMWORDS; /* BPF_MEMWORDS are 32-bit */
684 if (ctx->flags & SEEN_CALL)
686 * The JIT code make calls to external functions using 2
687 * arguments. Therefore, for o32 we don't need to allocate
688 * space because we don't care if the argumetns are lost
689 * across calls. We do need however to preserve incoming
690 * arguments but the space is already allocated for us by
691 * the caller. On the other hand, for n64, we need to allocate
692 * this space ourselves. We need to preserve $ra as well.
694 sp_off += config_enabled(CONFIG_64BIT) ?
695 (ARGS_USED_BY_JIT + 1) * RSIZE : RSIZE;
698 * Subtract the bytes for the last registers since we only care about
699 * the location on the stack pointer.
701 return sp_off - RSIZE;
704 static void build_prologue(struct jit_ctx *ctx)
706 u16 first_inst = ctx->skf->insns[0].code;
709 /* Calculate the total offset for the stack pointer */
710 sp_off = get_stack_depth(ctx);
711 save_bpf_jit_regs(ctx, sp_off);
713 if (ctx->flags & SEEN_SKB)
714 emit_reg_move(r_skb, MIPS_R_A0, ctx);
716 if (ctx->flags & SEEN_X)
717 emit_jit_reg_move(r_X, r_zero, ctx);
719 /* Do not leak kernel data to userspace */
720 if ((first_inst != (BPF_RET | BPF_K)) && !(is_load_to_a(first_inst)))
721 emit_jit_reg_move(r_A, r_zero, ctx);
724 static void build_epilogue(struct jit_ctx *ctx)
728 /* Calculate the total offset for the stack pointer */
730 sp_off = get_stack_depth(ctx);
731 restore_bpf_jit_regs(ctx, sp_off);
738 static u64 jit_get_skb_b(struct sk_buff *skb, unsigned offset)
743 err = skb_copy_bits(skb, offset, &ret, 1);
745 return (u64)err << 32 | ret;
748 static u64 jit_get_skb_h(struct sk_buff *skb, unsigned offset)
753 err = skb_copy_bits(skb, offset, &ret, 2);
755 return (u64)err << 32 | ntohs(ret);
758 static u64 jit_get_skb_w(struct sk_buff *skb, unsigned offset)
763 err = skb_copy_bits(skb, offset, &ret, 4);
765 return (u64)err << 32 | ntohl(ret);
768 static int build_body(struct jit_ctx *ctx)
770 void *load_func[] = {jit_get_skb_b, jit_get_skb_h, jit_get_skb_w};
771 const struct bpf_prog *prog = ctx->skf;
772 const struct sock_filter *inst;
773 unsigned int i, off, load_order, condt;
774 u32 k, b_off __maybe_unused;
777 for (i = 0; i < prog->len; i++) {
780 inst = &(prog->insns[i]);
781 pr_debug("%s: code->0x%02x, jt->0x%x, jf->0x%x, k->0x%x\n",
782 __func__, inst->code, inst->jt, inst->jf, inst->k);
784 code = bpf_anc_helper(inst);
786 if (ctx->target == NULL)
787 ctx->offsets[i] = ctx->idx * 4;
790 case BPF_LD | BPF_IMM:
791 /* A <- k ==> li r_A, k */
792 ctx->flags |= SEEN_A;
793 emit_load_imm(r_A, k, ctx);
795 case BPF_LD | BPF_W | BPF_LEN:
796 BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, len) != 4);
797 /* A <- len ==> lw r_A, offset(skb) */
798 ctx->flags |= SEEN_SKB | SEEN_A;
799 off = offsetof(struct sk_buff, len);
800 emit_load(r_A, r_skb, off, ctx);
802 case BPF_LD | BPF_MEM:
803 /* A <- M[k] ==> lw r_A, offset(M) */
804 ctx->flags |= SEEN_MEM | SEEN_A;
805 emit_load(r_A, r_M, SCRATCH_OFF(k), ctx);
807 case BPF_LD | BPF_W | BPF_ABS:
811 case BPF_LD | BPF_H | BPF_ABS:
815 case BPF_LD | BPF_B | BPF_ABS:
819 /* the interpreter will deal with the negative K */
823 emit_load_imm(r_off, k, ctx);
826 * We may got here from the indirect loads so
827 * return if offset is negative.
829 emit_slt(r_s0, r_off, r_zero, ctx);
830 emit_bcond(MIPS_COND_NE, r_s0, r_zero,
831 b_imm(prog->len, ctx), ctx);
832 emit_reg_move(r_ret, r_zero, ctx);
834 ctx->flags |= SEEN_CALL | SEEN_OFF | SEEN_S0 |
837 emit_load_func(r_s0, (ptr)load_func[load_order],
839 emit_reg_move(MIPS_R_A0, r_skb, ctx);
840 emit_jalr(MIPS_R_RA, r_s0, ctx);
841 /* Load second argument to delay slot */
842 emit_reg_move(MIPS_R_A1, r_off, ctx);
843 /* Check the error value */
844 if (config_enabled(CONFIG_64BIT)) {
845 /* Get error code from the top 32-bits */
846 emit_dsrl32(r_s0, r_val, 0, ctx);
847 /* Branch to 3 instructions ahead */
848 emit_bcond(MIPS_COND_NE, r_s0, r_zero, 3 << 2,
851 /* Branch to 3 instructions ahead */
852 emit_bcond(MIPS_COND_NE, r_err, r_zero, 3 << 2,
857 emit_b(b_imm(i + 1, ctx), ctx);
858 emit_jit_reg_move(r_A, r_val, ctx);
859 /* Return with error */
860 emit_b(b_imm(prog->len, ctx), ctx);
861 emit_reg_move(r_ret, r_zero, ctx);
863 case BPF_LD | BPF_W | BPF_IND:
864 /* A <- P[X + k:4] */
867 case BPF_LD | BPF_H | BPF_IND:
868 /* A <- P[X + k:2] */
871 case BPF_LD | BPF_B | BPF_IND:
872 /* A <- P[X + k:1] */
875 ctx->flags |= SEEN_OFF | SEEN_X;
876 emit_addiu(r_off, r_X, k, ctx);
878 case BPF_LDX | BPF_IMM:
880 ctx->flags |= SEEN_X;
881 emit_load_imm(r_X, k, ctx);
883 case BPF_LDX | BPF_MEM:
885 ctx->flags |= SEEN_X | SEEN_MEM;
886 emit_load(r_X, r_M, SCRATCH_OFF(k), ctx);
888 case BPF_LDX | BPF_W | BPF_LEN:
890 ctx->flags |= SEEN_X | SEEN_SKB;
891 off = offsetof(struct sk_buff, len);
892 emit_load(r_X, r_skb, off, ctx);
894 case BPF_LDX | BPF_B | BPF_MSH:
895 /* the interpreter will deal with the negative K */
899 /* X <- 4 * (P[k:1] & 0xf) */
900 ctx->flags |= SEEN_X | SEEN_CALL | SEEN_S0 | SEEN_SKB;
901 /* Load offset to a1 */
902 emit_load_func(r_s0, (ptr)jit_get_skb_b, ctx);
904 * This may emit two instructions so it may not fit
905 * in the delay slot. So use a0 in the delay slot.
907 emit_load_imm(MIPS_R_A1, k, ctx);
908 emit_jalr(MIPS_R_RA, r_s0, ctx);
909 emit_reg_move(MIPS_R_A0, r_skb, ctx); /* delay slot */
910 /* Check the error value */
911 if (config_enabled(CONFIG_64BIT)) {
912 /* Top 32-bits of $v0 on 64-bit */
913 emit_dsrl32(r_s0, r_val, 0, ctx);
914 emit_bcond(MIPS_COND_NE, r_s0, r_zero,
917 emit_bcond(MIPS_COND_NE, r_err, r_zero,
920 /* No need for delay slot */
922 /* X <- P[1:K] & 0xf */
923 emit_andi(r_X, r_val, 0xf, ctx);
925 emit_b(b_imm(i + 1, ctx), ctx);
926 emit_sll(r_X, r_X, 2, ctx); /* delay slot */
927 /* Return with error */
928 emit_b(b_imm(prog->len, ctx), ctx);
929 emit_load_imm(r_ret, 0, ctx); /* delay slot */
933 ctx->flags |= SEEN_MEM | SEEN_A;
934 emit_store(r_A, r_M, SCRATCH_OFF(k), ctx);
938 ctx->flags |= SEEN_MEM | SEEN_X;
939 emit_store(r_X, r_M, SCRATCH_OFF(k), ctx);
941 case BPF_ALU | BPF_ADD | BPF_K:
943 ctx->flags |= SEEN_A;
944 emit_addiu(r_A, r_A, k, ctx);
946 case BPF_ALU | BPF_ADD | BPF_X:
948 ctx->flags |= SEEN_A | SEEN_X;
949 emit_addu(r_A, r_A, r_X, ctx);
951 case BPF_ALU | BPF_SUB | BPF_K:
953 ctx->flags |= SEEN_A;
954 emit_addiu(r_A, r_A, -k, ctx);
956 case BPF_ALU | BPF_SUB | BPF_X:
958 ctx->flags |= SEEN_A | SEEN_X;
959 emit_subu(r_A, r_A, r_X, ctx);
961 case BPF_ALU | BPF_MUL | BPF_K:
963 /* Load K to scratch register before MUL */
964 ctx->flags |= SEEN_A | SEEN_S0;
965 emit_load_imm(r_s0, k, ctx);
966 emit_mul(r_A, r_A, r_s0, ctx);
968 case BPF_ALU | BPF_MUL | BPF_X:
970 ctx->flags |= SEEN_A | SEEN_X;
971 emit_mul(r_A, r_A, r_X, ctx);
973 case BPF_ALU | BPF_DIV | BPF_K:
977 if (optimize_div(&k)) {
978 ctx->flags |= SEEN_A;
979 emit_srl(r_A, r_A, k, ctx);
982 ctx->flags |= SEEN_A | SEEN_S0;
983 emit_load_imm(r_s0, k, ctx);
984 emit_div(r_A, r_s0, ctx);
986 case BPF_ALU | BPF_MOD | BPF_K:
988 if (k == 1 || optimize_div(&k)) {
989 ctx->flags |= SEEN_A;
990 emit_jit_reg_move(r_A, r_zero, ctx);
992 ctx->flags |= SEEN_A | SEEN_S0;
993 emit_load_imm(r_s0, k, ctx);
994 emit_mod(r_A, r_s0, ctx);
997 case BPF_ALU | BPF_DIV | BPF_X:
999 ctx->flags |= SEEN_X | SEEN_A;
1000 /* Check if r_X is zero */
1001 emit_bcond(MIPS_COND_EQ, r_X, r_zero,
1002 b_imm(prog->len, ctx), ctx);
1003 emit_load_imm(r_val, 0, ctx); /* delay slot */
1004 emit_div(r_A, r_X, ctx);
1006 case BPF_ALU | BPF_MOD | BPF_X:
1008 ctx->flags |= SEEN_X | SEEN_A;
1009 /* Check if r_X is zero */
1010 emit_bcond(MIPS_COND_EQ, r_X, r_zero,
1011 b_imm(prog->len, ctx), ctx);
1012 emit_load_imm(r_val, 0, ctx); /* delay slot */
1013 emit_mod(r_A, r_X, ctx);
1015 case BPF_ALU | BPF_OR | BPF_K:
1017 ctx->flags |= SEEN_A;
1018 emit_ori(r_A, r_A, k, ctx);
1020 case BPF_ALU | BPF_OR | BPF_X:
1022 ctx->flags |= SEEN_A;
1023 emit_ori(r_A, r_A, r_X, ctx);
1025 case BPF_ALU | BPF_XOR | BPF_K:
1027 ctx->flags |= SEEN_A;
1028 emit_xori(r_A, r_A, k, ctx);
1030 case BPF_ANC | SKF_AD_ALU_XOR_X:
1031 case BPF_ALU | BPF_XOR | BPF_X:
1033 ctx->flags |= SEEN_A;
1034 emit_xor(r_A, r_A, r_X, ctx);
1036 case BPF_ALU | BPF_AND | BPF_K:
1038 ctx->flags |= SEEN_A;
1039 emit_andi(r_A, r_A, k, ctx);
1041 case BPF_ALU | BPF_AND | BPF_X:
1043 ctx->flags |= SEEN_A | SEEN_X;
1044 emit_and(r_A, r_A, r_X, ctx);
1046 case BPF_ALU | BPF_LSH | BPF_K:
1048 ctx->flags |= SEEN_A;
1049 emit_sll(r_A, r_A, k, ctx);
1051 case BPF_ALU | BPF_LSH | BPF_X:
1053 ctx->flags |= SEEN_A | SEEN_X;
1054 emit_sllv(r_A, r_A, r_X, ctx);
1056 case BPF_ALU | BPF_RSH | BPF_K:
1058 ctx->flags |= SEEN_A;
1059 emit_srl(r_A, r_A, k, ctx);
1061 case BPF_ALU | BPF_RSH | BPF_X:
1062 ctx->flags |= SEEN_A | SEEN_X;
1063 emit_srlv(r_A, r_A, r_X, ctx);
1065 case BPF_ALU | BPF_NEG:
1067 ctx->flags |= SEEN_A;
1070 case BPF_JMP | BPF_JA:
1072 emit_b(b_imm(i + k + 1, ctx), ctx);
1075 case BPF_JMP | BPF_JEQ | BPF_K:
1076 /* pc += ( A == K ) ? pc->jt : pc->jf */
1077 condt = MIPS_COND_EQ | MIPS_COND_K;
1079 case BPF_JMP | BPF_JEQ | BPF_X:
1080 ctx->flags |= SEEN_X;
1081 /* pc += ( A == X ) ? pc->jt : pc->jf */
1082 condt = MIPS_COND_EQ | MIPS_COND_X;
1084 case BPF_JMP | BPF_JGE | BPF_K:
1085 /* pc += ( A >= K ) ? pc->jt : pc->jf */
1086 condt = MIPS_COND_GE | MIPS_COND_K;
1088 case BPF_JMP | BPF_JGE | BPF_X:
1089 ctx->flags |= SEEN_X;
1090 /* pc += ( A >= X ) ? pc->jt : pc->jf */
1091 condt = MIPS_COND_GE | MIPS_COND_X;
1093 case BPF_JMP | BPF_JGT | BPF_K:
1094 /* pc += ( A > K ) ? pc->jt : pc->jf */
1095 condt = MIPS_COND_GT | MIPS_COND_K;
1097 case BPF_JMP | BPF_JGT | BPF_X:
1098 ctx->flags |= SEEN_X;
1099 /* pc += ( A > X ) ? pc->jt : pc->jf */
1100 condt = MIPS_COND_GT | MIPS_COND_X;
1102 /* Greater or Equal */
1103 if ((condt & MIPS_COND_GE) ||
1104 (condt & MIPS_COND_GT)) {
1105 if (condt & MIPS_COND_K) { /* K */
1106 ctx->flags |= SEEN_S0 | SEEN_A;
1107 emit_sltiu(r_s0, r_A, k, ctx);
1109 ctx->flags |= SEEN_S0 | SEEN_A |
1111 emit_sltu(r_s0, r_A, r_X, ctx);
1113 /* A < (K|X) ? r_scrach = 1 */
1114 b_off = b_imm(i + inst->jf + 1, ctx);
1115 emit_bcond(MIPS_COND_NE, r_s0, r_zero, b_off,
1118 /* A > (K|X) ? scratch = 0 */
1119 if (condt & MIPS_COND_GT) {
1120 /* Checking for equality */
1121 ctx->flags |= SEEN_S0 | SEEN_A | SEEN_X;
1122 if (condt & MIPS_COND_K)
1123 emit_load_imm(r_s0, k, ctx);
1125 emit_jit_reg_move(r_s0, r_X,
1127 b_off = b_imm(i + inst->jf + 1, ctx);
1128 emit_bcond(MIPS_COND_EQ, r_A, r_s0,
1131 /* Finally, A > K|X */
1132 b_off = b_imm(i + inst->jt + 1, ctx);
1136 /* A >= (K|X) so jump */
1137 b_off = b_imm(i + inst->jt + 1, ctx);
1143 if (condt & MIPS_COND_K) { /* K */
1144 ctx->flags |= SEEN_S0 | SEEN_A;
1145 emit_load_imm(r_s0, k, ctx);
1147 b_off = b_imm(i + inst->jt + 1, ctx);
1148 emit_bcond(MIPS_COND_EQ, r_A, r_s0,
1152 b_off = b_imm(i + inst->jf + 1,
1154 emit_bcond(MIPS_COND_NE, r_A, r_s0,
1159 ctx->flags |= SEEN_A | SEEN_X;
1160 b_off = b_imm(i + inst->jt + 1,
1162 emit_bcond(MIPS_COND_EQ, r_A, r_X,
1166 b_off = b_imm(i + inst->jf + 1, ctx);
1167 emit_bcond(MIPS_COND_NE, r_A, r_X,
1173 case BPF_JMP | BPF_JSET | BPF_K:
1174 ctx->flags |= SEEN_S0 | SEEN_S1 | SEEN_A;
1175 /* pc += (A & K) ? pc -> jt : pc -> jf */
1176 emit_load_imm(r_s1, k, ctx);
1177 emit_and(r_s0, r_A, r_s1, ctx);
1179 b_off = b_imm(i + inst->jt + 1, ctx);
1180 emit_bcond(MIPS_COND_NE, r_s0, r_zero, b_off, ctx);
1183 b_off = b_imm(i + inst->jf + 1, ctx);
1187 case BPF_JMP | BPF_JSET | BPF_X:
1188 ctx->flags |= SEEN_S0 | SEEN_X | SEEN_A;
1189 /* pc += (A & X) ? pc -> jt : pc -> jf */
1190 emit_and(r_s0, r_A, r_X, ctx);
1192 b_off = b_imm(i + inst->jt + 1, ctx);
1193 emit_bcond(MIPS_COND_NE, r_s0, r_zero, b_off, ctx);
1196 b_off = b_imm(i + inst->jf + 1, ctx);
1200 case BPF_RET | BPF_A:
1201 ctx->flags |= SEEN_A;
1202 if (i != prog->len - 1)
1204 * If this is not the last instruction
1205 * then jump to the epilogue
1207 emit_b(b_imm(prog->len, ctx), ctx);
1208 emit_reg_move(r_ret, r_A, ctx); /* delay slot */
1210 case BPF_RET | BPF_K:
1212 * It can emit two instructions so it does not fit on
1215 emit_load_imm(r_ret, k, ctx);
1216 if (i != prog->len - 1) {
1218 * If this is not the last instruction
1219 * then jump to the epilogue
1221 emit_b(b_imm(prog->len, ctx), ctx);
1225 case BPF_MISC | BPF_TAX:
1227 ctx->flags |= SEEN_X | SEEN_A;
1228 emit_jit_reg_move(r_X, r_A, ctx);
1230 case BPF_MISC | BPF_TXA:
1232 ctx->flags |= SEEN_A | SEEN_X;
1233 emit_jit_reg_move(r_A, r_X, ctx);
1236 case BPF_ANC | SKF_AD_PROTOCOL:
1237 /* A = ntohs(skb->protocol */
1238 ctx->flags |= SEEN_SKB | SEEN_OFF | SEEN_A;
1239 BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff,
1241 off = offsetof(struct sk_buff, protocol);
1242 emit_half_load(r_A, r_skb, off, ctx);
1243 #ifdef CONFIG_CPU_LITTLE_ENDIAN
1244 /* This needs little endian fixup */
1245 if (cpu_has_mips_r2) {
1246 /* R2 and later have the wsbh instruction */
1247 emit_wsbh(r_A, r_A, ctx);
1249 /* Get first byte */
1250 emit_andi(r_tmp_imm, r_A, 0xff, ctx);
1252 emit_sll(r_tmp, r_tmp_imm, 8, ctx);
1253 /* Get second byte */
1254 emit_srl(r_tmp_imm, r_A, 8, ctx);
1255 emit_andi(r_tmp_imm, r_tmp_imm, 0xff, ctx);
1256 /* Put everyting together in r_A */
1257 emit_or(r_A, r_tmp, r_tmp_imm, ctx);
1261 case BPF_ANC | SKF_AD_CPU:
1262 ctx->flags |= SEEN_A | SEEN_OFF;
1263 /* A = current_thread_info()->cpu */
1264 BUILD_BUG_ON(FIELD_SIZEOF(struct thread_info,
1266 off = offsetof(struct thread_info, cpu);
1267 /* $28/gp points to the thread_info struct */
1268 emit_load(r_A, 28, off, ctx);
1270 case BPF_ANC | SKF_AD_IFINDEX:
1271 /* A = skb->dev->ifindex */
1272 ctx->flags |= SEEN_SKB | SEEN_A | SEEN_S0;
1273 off = offsetof(struct sk_buff, dev);
1274 /* Load *dev pointer */
1275 emit_load_ptr(r_s0, r_skb, off, ctx);
1276 /* error (0) in the delay slot */
1277 emit_bcond(MIPS_COND_EQ, r_s0, r_zero,
1278 b_imm(prog->len, ctx), ctx);
1279 emit_reg_move(r_ret, r_zero, ctx);
1280 BUILD_BUG_ON(FIELD_SIZEOF(struct net_device,
1282 off = offsetof(struct net_device, ifindex);
1283 emit_load(r_A, r_s0, off, ctx);
1285 case BPF_ANC | SKF_AD_MARK:
1286 ctx->flags |= SEEN_SKB | SEEN_A;
1287 BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, mark) != 4);
1288 off = offsetof(struct sk_buff, mark);
1289 emit_load(r_A, r_skb, off, ctx);
1291 case BPF_ANC | SKF_AD_RXHASH:
1292 ctx->flags |= SEEN_SKB | SEEN_A;
1293 BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, hash) != 4);
1294 off = offsetof(struct sk_buff, hash);
1295 emit_load(r_A, r_skb, off, ctx);
1297 case BPF_ANC | SKF_AD_VLAN_TAG:
1298 case BPF_ANC | SKF_AD_VLAN_TAG_PRESENT:
1299 ctx->flags |= SEEN_SKB | SEEN_S0 | SEEN_A;
1300 BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff,
1302 off = offsetof(struct sk_buff, vlan_tci);
1303 emit_half_load(r_s0, r_skb, off, ctx);
1304 if (code == (BPF_ANC | SKF_AD_VLAN_TAG)) {
1305 emit_andi(r_A, r_s0, (u16)~VLAN_TAG_PRESENT, ctx);
1307 emit_andi(r_A, r_s0, VLAN_TAG_PRESENT, ctx);
1308 /* return 1 if present */
1309 emit_sltu(r_A, r_zero, r_A, ctx);
1312 case BPF_ANC | SKF_AD_PKTTYPE:
1313 ctx->flags |= SEEN_SKB;
1315 emit_load_byte(r_tmp, r_skb, PKT_TYPE_OFFSET(), ctx);
1316 /* Keep only the last 3 bits */
1317 emit_andi(r_A, r_tmp, PKT_TYPE_MAX, ctx);
1318 #ifdef __BIG_ENDIAN_BITFIELD
1319 /* Get the actual packet type to the lower 3 bits */
1320 emit_srl(r_A, r_A, 5, ctx);
1323 case BPF_ANC | SKF_AD_QUEUE:
1324 ctx->flags |= SEEN_SKB | SEEN_A;
1325 BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff,
1326 queue_mapping) != 2);
1327 BUILD_BUG_ON(offsetof(struct sk_buff,
1328 queue_mapping) > 0xff);
1329 off = offsetof(struct sk_buff, queue_mapping);
1330 emit_half_load(r_A, r_skb, off, ctx);
1333 pr_debug("%s: Unhandled opcode: 0x%02x\n", __FILE__,
1339 /* compute offsets only during the first pass */
1340 if (ctx->target == NULL)
1341 ctx->offsets[i] = ctx->idx * 4;
1346 int bpf_jit_enable __read_mostly;
1348 void bpf_jit_compile(struct bpf_prog *fp)
1351 unsigned int alloc_size, tmp_idx;
1353 if (!bpf_jit_enable)
1356 memset(&ctx, 0, sizeof(ctx));
1358 ctx.offsets = kcalloc(fp->len, sizeof(*ctx.offsets), GFP_KERNEL);
1359 if (ctx.offsets == NULL)
1364 if (build_body(&ctx))
1368 build_prologue(&ctx);
1369 ctx.prologue_bytes = (ctx.idx - tmp_idx) * 4;
1370 /* just to complete the ctx.idx count */
1371 build_epilogue(&ctx);
1373 alloc_size = 4 * ctx.idx;
1374 ctx.target = module_alloc(alloc_size);
1375 if (ctx.target == NULL)
1379 memset(ctx.target, 0, alloc_size);
1383 /* Generate the actual JIT code */
1384 build_prologue(&ctx);
1386 build_epilogue(&ctx);
1388 /* Update the icache */
1389 flush_icache_range((ptr)ctx.target, (ptr)(ctx.target + ctx.idx));
1391 if (bpf_jit_enable > 1)
1393 bpf_jit_dump(fp->len, alloc_size, 2, ctx.target);
1395 fp->bpf_func = (void *)ctx.target;
1402 void bpf_jit_free(struct bpf_prog *fp)
1405 module_free(NULL, fp->bpf_func);
1407 bpf_prog_unlock_free(fp);