2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Synthesize TLB refill handlers at runtime.
8 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
9 * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki
10 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
11 * Copyright (C) 2008, 2009 Cavium Networks, Inc.
13 * ... and the days got worse and worse and now you see
14 * I've gone completly out of my mind.
16 * They're coming to take me a away haha
17 * they're coming to take me a away hoho hihi haha
18 * to the funny farm where code is beautiful all the time ...
20 * (Condolences to Napoleon XIV)
23 #include <linux/bug.h>
24 #include <linux/kernel.h>
25 #include <linux/types.h>
26 #include <linux/smp.h>
27 #include <linux/string.h>
28 #include <linux/init.h>
30 #include <asm/mmu_context.h>
35 static inline int r45k_bvahwbug(void)
37 /* XXX: We should probe for the presence of this bug, but we don't. */
41 static inline int r4k_250MHZhwbug(void)
43 /* XXX: We should probe for the presence of this bug, but we don't. */
47 static inline int __maybe_unused bcm1250_m3_war(void)
49 return BCM1250_M3_WAR;
52 static inline int __maybe_unused r10000_llsc_war(void)
54 return R10000_LLSC_WAR;
58 * Found by experiment: At least some revisions of the 4kc throw under
59 * some circumstances a machine check exception, triggered by invalid
60 * values in the index register. Delaying the tlbp instruction until
61 * after the next branch, plus adding an additional nop in front of
62 * tlbwi/tlbwr avoids the invalid index register values. Nobody knows
63 * why; it's not an issue caused by the core RTL.
66 static int __cpuinit m4kc_tlbp_war(void)
68 return (current_cpu_data.processor_id & 0xffff00) ==
69 (PRID_COMP_MIPS | PRID_IMP_4KC);
72 /* Handle labels (which must be positive integers). */
74 label_second_part = 1,
86 label_smp_pgtable_change,
87 label_r3000_write_probe_fail,
88 #ifdef CONFIG_HUGETLB_PAGE
89 label_tlb_huge_update,
93 UASM_L_LA(_second_part)
96 UASM_L_LA(_module_alloc)
99 UASM_L_LA(_vmalloc_done)
100 UASM_L_LA(_tlbw_hazard)
102 UASM_L_LA(_nopage_tlbl)
103 UASM_L_LA(_nopage_tlbs)
104 UASM_L_LA(_nopage_tlbm)
105 UASM_L_LA(_smp_pgtable_change)
106 UASM_L_LA(_r3000_write_probe_fail)
107 #ifdef CONFIG_HUGETLB_PAGE
108 UASM_L_LA(_tlb_huge_update)
112 * For debug purposes.
114 static inline void dump_handler(const u32 *handler, int count)
118 pr_debug("\t.set push\n");
119 pr_debug("\t.set noreorder\n");
121 for (i = 0; i < count; i++)
122 pr_debug("\t%p\t.word 0x%08x\n", &handler[i], handler[i]);
124 pr_debug("\t.set pop\n");
127 /* The only general purpose registers allowed in TLB handlers. */
131 /* Some CP0 registers */
132 #define C0_INDEX 0, 0
133 #define C0_ENTRYLO0 2, 0
134 #define C0_TCBIND 2, 2
135 #define C0_ENTRYLO1 3, 0
136 #define C0_CONTEXT 4, 0
137 #define C0_PAGEMASK 5, 0
138 #define C0_BADVADDR 8, 0
139 #define C0_ENTRYHI 10, 0
141 #define C0_XCONTEXT 20, 0
144 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT)
146 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT)
149 /* The worst case length of the handler is around 18 instructions for
150 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs.
151 * Maximum space available is 32 instructions for R3000 and 64
152 * instructions for R4000.
154 * We deliberately chose a buffer size of 128, so we won't scribble
155 * over anything important on overflow before we panic.
157 static u32 tlb_handler[128] __cpuinitdata;
159 /* simply assume worst case size for labels and relocs */
160 static struct uasm_label labels[128] __cpuinitdata;
161 static struct uasm_reloc relocs[128] __cpuinitdata;
163 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
165 * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current,
166 * we cannot do r3000 under these circumstances.
170 * The R3000 TLB handler is simple.
172 static void __cpuinit build_r3000_tlb_refill_handler(void)
174 long pgdc = (long)pgd_current;
177 memset(tlb_handler, 0, sizeof(tlb_handler));
180 uasm_i_mfc0(&p, K0, C0_BADVADDR);
181 uasm_i_lui(&p, K1, uasm_rel_hi(pgdc)); /* cp0 delay */
182 uasm_i_lw(&p, K1, uasm_rel_lo(pgdc), K1);
183 uasm_i_srl(&p, K0, K0, 22); /* load delay */
184 uasm_i_sll(&p, K0, K0, 2);
185 uasm_i_addu(&p, K1, K1, K0);
186 uasm_i_mfc0(&p, K0, C0_CONTEXT);
187 uasm_i_lw(&p, K1, 0, K1); /* cp0 delay */
188 uasm_i_andi(&p, K0, K0, 0xffc); /* load delay */
189 uasm_i_addu(&p, K1, K1, K0);
190 uasm_i_lw(&p, K0, 0, K1);
191 uasm_i_nop(&p); /* load delay */
192 uasm_i_mtc0(&p, K0, C0_ENTRYLO0);
193 uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */
194 uasm_i_tlbwr(&p); /* cp0 delay */
196 uasm_i_rfe(&p); /* branch delay */
198 if (p > tlb_handler + 32)
199 panic("TLB refill handler space exceeded");
201 pr_debug("Wrote TLB refill handler (%u instructions).\n",
202 (unsigned int)(p - tlb_handler));
204 memcpy((void *)ebase, tlb_handler, 0x80);
206 dump_handler((u32 *)ebase, 32);
208 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
211 * The R4000 TLB handler is much more complicated. We have two
212 * consecutive handler areas with 32 instructions space each.
213 * Since they aren't used at the same time, we can overflow in the
214 * other one.To keep things simple, we first assume linear space,
215 * then we relocate it to the final handler layout as needed.
217 static u32 final_handler[64] __cpuinitdata;
222 * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0:
223 * 2. A timing hazard exists for the TLBP instruction.
225 * stalling_instruction
228 * The JTLB is being read for the TLBP throughout the stall generated by the
229 * previous instruction. This is not really correct as the stalling instruction
230 * can modify the address used to access the JTLB. The failure symptom is that
231 * the TLBP instruction will use an address created for the stalling instruction
232 * and not the address held in C0_ENHI and thus report the wrong results.
234 * The software work-around is to not allow the instruction preceding the TLBP
235 * to stall - make it an NOP or some other instruction guaranteed not to stall.
237 * Errata 2 will not be fixed. This errata is also on the R5000.
239 * As if we MIPS hackers wouldn't know how to nop pipelines happy ...
241 static void __cpuinit __maybe_unused build_tlb_probe_entry(u32 **p)
243 switch (current_cpu_type()) {
244 /* Found by experiment: R4600 v2.0/R4700 needs this, too. */
261 * Write random or indexed TLB entry, and care about the hazards from
262 * the preceeding mtc0 and for the following eret.
264 enum tlb_write_entry { tlb_random, tlb_indexed };
266 static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
267 struct uasm_reloc **r,
268 enum tlb_write_entry wmode)
270 void(*tlbw)(u32 **) = NULL;
273 case tlb_random: tlbw = uasm_i_tlbwr; break;
274 case tlb_indexed: tlbw = uasm_i_tlbwi; break;
277 if (cpu_has_mips_r2) {
278 if (cpu_has_mips_r2_exec_hazard)
284 switch (current_cpu_type()) {
292 * This branch uses up a mtc0 hazard nop slot and saves
293 * two nops after the tlbw instruction.
295 uasm_il_bgezl(p, r, 0, label_tlbw_hazard);
297 uasm_l_tlbw_hazard(l, *p);
343 uasm_i_nop(p); /* QED specifies 2 nops hazard */
345 * This branch uses up a mtc0 hazard nop slot and saves
346 * a nop after the tlbw instruction.
348 uasm_il_bgezl(p, r, 0, label_tlbw_hazard);
350 uasm_l_tlbw_hazard(l, *p);
363 * When the JTLB is updated by tlbwi or tlbwr, a subsequent
364 * use of the JTLB for instructions should not occur for 4
365 * cpu cycles and use for data translations should not occur
400 panic("No TLB refill handler yet (CPU type: %d)",
401 current_cpu_data.cputype);
406 #ifdef CONFIG_HUGETLB_PAGE
407 static __cpuinit void build_huge_tlb_write_entry(u32 **p,
408 struct uasm_label **l,
409 struct uasm_reloc **r,
411 enum tlb_write_entry wmode)
413 /* Set huge page tlb entry size */
414 uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16);
415 uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff);
416 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
418 build_tlb_write_entry(p, l, r, wmode);
420 /* Reset default page size */
421 if (PM_DEFAULT_MASK >> 16) {
422 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16);
423 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff);
424 uasm_il_b(p, r, label_leave);
425 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
426 } else if (PM_DEFAULT_MASK) {
427 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK);
428 uasm_il_b(p, r, label_leave);
429 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
431 uasm_il_b(p, r, label_leave);
432 uasm_i_mtc0(p, 0, C0_PAGEMASK);
437 * Check if Huge PTE is present, if so then jump to LABEL.
439 static void __cpuinit
440 build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp,
441 unsigned int pmd, int lid)
443 UASM_i_LW(p, tmp, 0, pmd);
444 uasm_i_andi(p, tmp, tmp, _PAGE_HUGE);
445 uasm_il_bnez(p, r, tmp, lid);
448 static __cpuinit void build_huge_update_entries(u32 **p,
455 * A huge PTE describes an area the size of the
456 * configured huge page size. This is twice the
457 * of the large TLB entry size we intend to use.
458 * A TLB entry half the size of the configured
459 * huge page size is configured into entrylo0
460 * and entrylo1 to cover the contiguous huge PTE
463 small_sequence = (HPAGE_SIZE >> 7) < 0x10000;
465 /* We can clobber tmp. It isn't used after this.*/
467 uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16));
469 UASM_i_SRL(p, pte, pte, 6); /* convert to entrylo */
470 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* load it */
471 /* convert to entrylo1 */
473 UASM_i_ADDIU(p, pte, pte, HPAGE_SIZE >> 7);
475 UASM_i_ADDU(p, pte, pte, tmp);
477 uasm_i_mtc0(p, pte, C0_ENTRYLO1); /* load it */
480 static __cpuinit void build_huge_handler_tail(u32 **p,
481 struct uasm_reloc **r,
482 struct uasm_label **l,
487 UASM_i_SC(p, pte, 0, ptr);
488 uasm_il_beqz(p, r, pte, label_tlb_huge_update);
489 UASM_i_LW(p, pte, 0, ptr); /* Needed because SC killed our PTE */
491 UASM_i_SW(p, pte, 0, ptr);
493 build_huge_update_entries(p, pte, ptr);
494 build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed);
496 #endif /* CONFIG_HUGETLB_PAGE */
500 * TMP and PTR are scratch.
501 * TMP will be clobbered, PTR will hold the pmd entry.
503 static void __cpuinit
504 build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
505 unsigned int tmp, unsigned int ptr)
507 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
508 long pgdc = (long)pgd_current;
511 * The vmalloc handling is not in the hotpath.
513 uasm_i_dmfc0(p, tmp, C0_BADVADDR);
514 uasm_il_bltz(p, r, tmp, label_vmalloc);
515 /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */
517 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
519 * &pgd << 11 stored in CONTEXT [23..63].
521 UASM_i_MFC0(p, ptr, C0_CONTEXT);
522 uasm_i_dins(p, ptr, 0, 0, 23); /* Clear lower 23 bits of context. */
523 uasm_i_ori(p, ptr, ptr, 0x540); /* 1 0 1 0 1 << 6 xkphys cached */
524 uasm_i_drotr(p, ptr, ptr, 11);
525 #elif defined(CONFIG_SMP)
526 # ifdef CONFIG_MIPS_MT_SMTC
528 * SMTC uses TCBind value as "CPU" index
530 uasm_i_mfc0(p, ptr, C0_TCBIND);
531 uasm_i_dsrl(p, ptr, ptr, 19);
534 * 64 bit SMP running in XKPHYS has smp_processor_id() << 3
537 uasm_i_dmfc0(p, ptr, C0_CONTEXT);
538 uasm_i_dsrl(p, ptr, ptr, 23);
540 UASM_i_LA_mostly(p, tmp, pgdc);
541 uasm_i_daddu(p, ptr, ptr, tmp);
542 uasm_i_dmfc0(p, tmp, C0_BADVADDR);
543 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
545 UASM_i_LA_mostly(p, ptr, pgdc);
546 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
549 uasm_l_vmalloc_done(l, *p);
551 if (PGDIR_SHIFT - 3 < 32) /* get pgd offset in bytes */
552 uasm_i_dsrl(p, tmp, tmp, PGDIR_SHIFT-3);
554 uasm_i_dsrl32(p, tmp, tmp, PGDIR_SHIFT - 3 - 32);
556 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3);
557 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */
558 uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */
559 uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */
560 uasm_i_dsrl(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */
561 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3);
562 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */
566 * BVADDR is the faulting address, PTR is scratch.
567 * PTR will hold the pgd for vmalloc.
569 static void __cpuinit
570 build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
571 unsigned int bvaddr, unsigned int ptr)
573 long swpd = (long)swapper_pg_dir;
575 uasm_l_vmalloc(l, *p);
577 if (uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd)) {
578 uasm_il_b(p, r, label_vmalloc_done);
579 uasm_i_lui(p, ptr, uasm_rel_hi(swpd));
581 UASM_i_LA_mostly(p, ptr, swpd);
582 uasm_il_b(p, r, label_vmalloc_done);
583 if (uasm_in_compat_space_p(swpd))
584 uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd));
586 uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd));
590 #else /* !CONFIG_64BIT */
593 * TMP and PTR are scratch.
594 * TMP will be clobbered, PTR will hold the pgd entry.
596 static void __cpuinit __maybe_unused
597 build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
599 long pgdc = (long)pgd_current;
601 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */
603 #ifdef CONFIG_MIPS_MT_SMTC
605 * SMTC uses TCBind value as "CPU" index
607 uasm_i_mfc0(p, ptr, C0_TCBIND);
608 UASM_i_LA_mostly(p, tmp, pgdc);
609 uasm_i_srl(p, ptr, ptr, 19);
612 * smp_processor_id() << 3 is stored in CONTEXT.
614 uasm_i_mfc0(p, ptr, C0_CONTEXT);
615 UASM_i_LA_mostly(p, tmp, pgdc);
616 uasm_i_srl(p, ptr, ptr, 23);
618 uasm_i_addu(p, ptr, tmp, ptr);
620 UASM_i_LA_mostly(p, ptr, pgdc);
622 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
623 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
624 uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */
625 uasm_i_sll(p, tmp, tmp, PGD_T_LOG2);
626 uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */
629 #endif /* !CONFIG_64BIT */
631 static void __cpuinit build_adjust_context(u32 **p, unsigned int ctx)
633 unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12;
634 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1);
636 switch (current_cpu_type()) {
653 UASM_i_SRL(p, ctx, ctx, shift);
654 uasm_i_andi(p, ctx, ctx, mask);
657 static void __cpuinit build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)
660 * Bug workaround for the Nevada. It seems as if under certain
661 * circumstances the move from cp0_context might produce a
662 * bogus result when the mfc0 instruction and its consumer are
663 * in a different cacheline or a load instruction, probably any
664 * memory reference, is between them.
666 switch (current_cpu_type()) {
668 UASM_i_LW(p, ptr, 0, ptr);
669 GET_CONTEXT(p, tmp); /* get context reg */
673 GET_CONTEXT(p, tmp); /* get context reg */
674 UASM_i_LW(p, ptr, 0, ptr);
678 build_adjust_context(p, tmp);
679 UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */
682 static void __cpuinit build_update_entries(u32 **p, unsigned int tmp,
686 * 64bit address support (36bit on a 32bit CPU) in a 32bit
687 * Kernel is a special case. Only a few CPUs use it.
689 #ifdef CONFIG_64BIT_PHYS_ADDR
690 if (cpu_has_64bits) {
691 uasm_i_ld(p, tmp, 0, ptep); /* get even pte */
692 uasm_i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */
693 uasm_i_dsrl(p, tmp, tmp, 6); /* convert to entrylo0 */
694 uasm_i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */
695 uasm_i_dsrl(p, ptep, ptep, 6); /* convert to entrylo1 */
696 uasm_i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */
698 int pte_off_even = sizeof(pte_t) / 2;
699 int pte_off_odd = pte_off_even + sizeof(pte_t);
701 /* The pte entries are pre-shifted */
702 uasm_i_lw(p, tmp, pte_off_even, ptep); /* get even pte */
703 uasm_i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */
704 uasm_i_lw(p, ptep, pte_off_odd, ptep); /* get odd pte */
705 uasm_i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */
708 UASM_i_LW(p, tmp, 0, ptep); /* get even pte */
709 UASM_i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */
711 build_tlb_probe_entry(p);
712 UASM_i_SRL(p, tmp, tmp, 6); /* convert to entrylo0 */
713 if (r4k_250MHZhwbug())
714 uasm_i_mtc0(p, 0, C0_ENTRYLO0);
715 uasm_i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */
716 UASM_i_SRL(p, ptep, ptep, 6); /* convert to entrylo1 */
718 uasm_i_mfc0(p, tmp, C0_INDEX);
719 if (r4k_250MHZhwbug())
720 uasm_i_mtc0(p, 0, C0_ENTRYLO1);
721 uasm_i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */
726 * For a 64-bit kernel, we are using the 64-bit XTLB refill exception
727 * because EXL == 0. If we wrap, we can also use the 32 instruction
728 * slots before the XTLB refill exception handler which belong to the
729 * unused TLB refill exception.
731 #define MIPS64_REFILL_INSNS 32
733 static void __cpuinit build_r4000_tlb_refill_handler(void)
735 u32 *p = tlb_handler;
736 struct uasm_label *l = labels;
737 struct uasm_reloc *r = relocs;
739 unsigned int final_len;
741 memset(tlb_handler, 0, sizeof(tlb_handler));
742 memset(labels, 0, sizeof(labels));
743 memset(relocs, 0, sizeof(relocs));
744 memset(final_handler, 0, sizeof(final_handler));
747 * create the plain linear handler
749 if (bcm1250_m3_war()) {
750 UASM_i_MFC0(&p, K0, C0_BADVADDR);
751 UASM_i_MFC0(&p, K1, C0_ENTRYHI);
752 uasm_i_xor(&p, K0, K0, K1);
753 UASM_i_SRL(&p, K0, K0, PAGE_SHIFT + 1);
754 uasm_il_bnez(&p, &r, K0, label_leave);
755 /* No need for uasm_i_nop */
759 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
761 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
764 #ifdef CONFIG_HUGETLB_PAGE
765 build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update);
768 build_get_ptep(&p, K0, K1);
769 build_update_entries(&p, K0, K1);
770 build_tlb_write_entry(&p, &l, &r, tlb_random);
772 uasm_i_eret(&p); /* return from trap */
774 #ifdef CONFIG_HUGETLB_PAGE
775 uasm_l_tlb_huge_update(&l, p);
776 UASM_i_LW(&p, K0, 0, K1);
777 build_huge_update_entries(&p, K0, K1);
778 build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random);
782 build_get_pgd_vmalloc64(&p, &l, &r, K0, K1);
786 * Overflow check: For the 64bit handler, we need at least one
787 * free instruction slot for the wrap-around branch. In worst
788 * case, if the intended insertion point is a delay slot, we
789 * need three, with the second nop'ed and the third being
792 /* Loongson2 ebase is different than r4k, we have more space */
793 #if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2)
794 if ((p - tlb_handler) > 64)
795 panic("TLB refill handler space exceeded");
797 if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1)
798 || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3)
799 && uasm_insn_has_bdelay(relocs,
800 tlb_handler + MIPS64_REFILL_INSNS - 3)))
801 panic("TLB refill handler space exceeded");
805 * Now fold the handler in the TLB refill handler space.
807 #if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2)
809 /* Simplest case, just copy the handler. */
810 uasm_copy_handler(relocs, labels, tlb_handler, p, f);
811 final_len = p - tlb_handler;
812 #else /* CONFIG_64BIT */
813 f = final_handler + MIPS64_REFILL_INSNS;
814 if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) {
815 /* Just copy the handler. */
816 uasm_copy_handler(relocs, labels, tlb_handler, p, f);
817 final_len = p - tlb_handler;
819 #if defined(CONFIG_HUGETLB_PAGE)
820 const enum label_id ls = label_tlb_huge_update;
821 #elif defined(MODULE_START)
822 const enum label_id ls = label_module_alloc;
824 const enum label_id ls = label_vmalloc;
830 for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++)
832 BUG_ON(i == ARRAY_SIZE(labels));
833 split = labels[i].addr;
836 * See if we have overflown one way or the other.
838 if (split > tlb_handler + MIPS64_REFILL_INSNS ||
839 split < p - MIPS64_REFILL_INSNS)
844 * Split two instructions before the end. One
845 * for the branch and one for the instruction
848 split = tlb_handler + MIPS64_REFILL_INSNS - 2;
851 * If the branch would fall in a delay slot,
852 * we must back up an additional instruction
853 * so that it is no longer in a delay slot.
855 if (uasm_insn_has_bdelay(relocs, split - 1))
858 /* Copy first part of the handler. */
859 uasm_copy_handler(relocs, labels, tlb_handler, split, f);
860 f += split - tlb_handler;
864 uasm_l_split(&l, final_handler);
865 uasm_il_b(&f, &r, label_split);
866 if (uasm_insn_has_bdelay(relocs, split))
869 uasm_copy_handler(relocs, labels,
870 split, split + 1, f);
871 uasm_move_labels(labels, f, f + 1, -1);
877 /* Copy the rest of the handler. */
878 uasm_copy_handler(relocs, labels, split, p, final_handler);
879 final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) +
882 #endif /* CONFIG_64BIT */
884 uasm_resolve_relocs(relocs, labels);
885 pr_debug("Wrote TLB refill handler (%u instructions).\n",
888 memcpy((void *)ebase, final_handler, 0x100);
890 dump_handler((u32 *)ebase, 64);
894 * TLB load/store/modify handlers.
896 * Only the fastpath gets synthesized at runtime, the slowpath for
897 * do_page_fault remains normal asm.
899 extern void tlb_do_page_fault_0(void);
900 extern void tlb_do_page_fault_1(void);
903 * 128 instructions for the fastpath handler is generous and should
906 #define FASTPATH_SIZE 128
908 u32 handle_tlbl[FASTPATH_SIZE] __cacheline_aligned;
909 u32 handle_tlbs[FASTPATH_SIZE] __cacheline_aligned;
910 u32 handle_tlbm[FASTPATH_SIZE] __cacheline_aligned;
912 static void __cpuinit
913 iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr)
916 # ifdef CONFIG_64BIT_PHYS_ADDR
918 uasm_i_lld(p, pte, 0, ptr);
921 UASM_i_LL(p, pte, 0, ptr);
923 # ifdef CONFIG_64BIT_PHYS_ADDR
925 uasm_i_ld(p, pte, 0, ptr);
928 UASM_i_LW(p, pte, 0, ptr);
932 static void __cpuinit
933 iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr,
936 #ifdef CONFIG_64BIT_PHYS_ADDR
937 unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY);
940 uasm_i_ori(p, pte, pte, mode);
942 # ifdef CONFIG_64BIT_PHYS_ADDR
944 uasm_i_scd(p, pte, 0, ptr);
947 UASM_i_SC(p, pte, 0, ptr);
949 if (r10000_llsc_war())
950 uasm_il_beqzl(p, r, pte, label_smp_pgtable_change);
952 uasm_il_beqz(p, r, pte, label_smp_pgtable_change);
954 # ifdef CONFIG_64BIT_PHYS_ADDR
955 if (!cpu_has_64bits) {
956 /* no uasm_i_nop needed */
957 uasm_i_ll(p, pte, sizeof(pte_t) / 2, ptr);
958 uasm_i_ori(p, pte, pte, hwmode);
959 uasm_i_sc(p, pte, sizeof(pte_t) / 2, ptr);
960 uasm_il_beqz(p, r, pte, label_smp_pgtable_change);
961 /* no uasm_i_nop needed */
962 uasm_i_lw(p, pte, 0, ptr);
969 # ifdef CONFIG_64BIT_PHYS_ADDR
971 uasm_i_sd(p, pte, 0, ptr);
974 UASM_i_SW(p, pte, 0, ptr);
976 # ifdef CONFIG_64BIT_PHYS_ADDR
977 if (!cpu_has_64bits) {
978 uasm_i_lw(p, pte, sizeof(pte_t) / 2, ptr);
979 uasm_i_ori(p, pte, pte, hwmode);
980 uasm_i_sw(p, pte, sizeof(pte_t) / 2, ptr);
981 uasm_i_lw(p, pte, 0, ptr);
988 * Check if PTE is present, if not then jump to LABEL. PTR points to
989 * the page table where this PTE is located, PTE will be re-loaded
990 * with it's original value.
992 static void __cpuinit
993 build_pte_present(u32 **p, struct uasm_reloc **r,
994 unsigned int pte, unsigned int ptr, enum label_id lid)
996 uasm_i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_READ);
997 uasm_i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_READ);
998 uasm_il_bnez(p, r, pte, lid);
999 iPTE_LW(p, pte, ptr);
1002 /* Make PTE valid, store result in PTR. */
1003 static void __cpuinit
1004 build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte,
1007 unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED;
1009 iPTE_SW(p, r, pte, ptr, mode);
1013 * Check if PTE can be written to, if not branch to LABEL. Regardless
1014 * restore PTE with value from PTR when done.
1016 static void __cpuinit
1017 build_pte_writable(u32 **p, struct uasm_reloc **r,
1018 unsigned int pte, unsigned int ptr, enum label_id lid)
1020 uasm_i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE);
1021 uasm_i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE);
1022 uasm_il_bnez(p, r, pte, lid);
1023 iPTE_LW(p, pte, ptr);
1026 /* Make PTE writable, update software status bits as well, then store
1029 static void __cpuinit
1030 build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte,
1033 unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID
1036 iPTE_SW(p, r, pte, ptr, mode);
1040 * Check if PTE can be modified, if not branch to LABEL. Regardless
1041 * restore PTE with value from PTR when done.
1043 static void __cpuinit
1044 build_pte_modifiable(u32 **p, struct uasm_reloc **r,
1045 unsigned int pte, unsigned int ptr, enum label_id lid)
1047 uasm_i_andi(p, pte, pte, _PAGE_WRITE);
1048 uasm_il_beqz(p, r, pte, lid);
1049 iPTE_LW(p, pte, ptr);
1052 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
1054 * R3000 style TLB load/store/modify handlers.
1058 * This places the pte into ENTRYLO0 and writes it with tlbwi.
1061 static void __cpuinit
1062 build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp)
1064 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
1065 uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */
1068 uasm_i_rfe(p); /* branch delay */
1072 * This places the pte into ENTRYLO0 and writes it with tlbwi
1073 * or tlbwr as appropriate. This is because the index register
1074 * may have the probe fail bit set as a result of a trap on a
1075 * kseg2 access, i.e. without refill. Then it returns.
1077 static void __cpuinit
1078 build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l,
1079 struct uasm_reloc **r, unsigned int pte,
1082 uasm_i_mfc0(p, tmp, C0_INDEX);
1083 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
1084 uasm_il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */
1085 uasm_i_mfc0(p, tmp, C0_EPC); /* branch delay */
1086 uasm_i_tlbwi(p); /* cp0 delay */
1088 uasm_i_rfe(p); /* branch delay */
1089 uasm_l_r3000_write_probe_fail(l, *p);
1090 uasm_i_tlbwr(p); /* cp0 delay */
1092 uasm_i_rfe(p); /* branch delay */
1095 static void __cpuinit
1096 build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte,
1099 long pgdc = (long)pgd_current;
1101 uasm_i_mfc0(p, pte, C0_BADVADDR);
1102 uasm_i_lui(p, ptr, uasm_rel_hi(pgdc)); /* cp0 delay */
1103 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
1104 uasm_i_srl(p, pte, pte, 22); /* load delay */
1105 uasm_i_sll(p, pte, pte, 2);
1106 uasm_i_addu(p, ptr, ptr, pte);
1107 uasm_i_mfc0(p, pte, C0_CONTEXT);
1108 uasm_i_lw(p, ptr, 0, ptr); /* cp0 delay */
1109 uasm_i_andi(p, pte, pte, 0xffc); /* load delay */
1110 uasm_i_addu(p, ptr, ptr, pte);
1111 uasm_i_lw(p, pte, 0, ptr);
1112 uasm_i_tlbp(p); /* load delay */
1115 static void __cpuinit build_r3000_tlb_load_handler(void)
1117 u32 *p = handle_tlbl;
1118 struct uasm_label *l = labels;
1119 struct uasm_reloc *r = relocs;
1121 memset(handle_tlbl, 0, sizeof(handle_tlbl));
1122 memset(labels, 0, sizeof(labels));
1123 memset(relocs, 0, sizeof(relocs));
1125 build_r3000_tlbchange_handler_head(&p, K0, K1);
1126 build_pte_present(&p, &r, K0, K1, label_nopage_tlbl);
1127 uasm_i_nop(&p); /* load delay */
1128 build_make_valid(&p, &r, K0, K1);
1129 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
1131 uasm_l_nopage_tlbl(&l, p);
1132 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
1135 if ((p - handle_tlbl) > FASTPATH_SIZE)
1136 panic("TLB load handler fastpath space exceeded");
1138 uasm_resolve_relocs(relocs, labels);
1139 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
1140 (unsigned int)(p - handle_tlbl));
1142 dump_handler(handle_tlbl, ARRAY_SIZE(handle_tlbl));
1145 static void __cpuinit build_r3000_tlb_store_handler(void)
1147 u32 *p = handle_tlbs;
1148 struct uasm_label *l = labels;
1149 struct uasm_reloc *r = relocs;
1151 memset(handle_tlbs, 0, sizeof(handle_tlbs));
1152 memset(labels, 0, sizeof(labels));
1153 memset(relocs, 0, sizeof(relocs));
1155 build_r3000_tlbchange_handler_head(&p, K0, K1);
1156 build_pte_writable(&p, &r, K0, K1, label_nopage_tlbs);
1157 uasm_i_nop(&p); /* load delay */
1158 build_make_write(&p, &r, K0, K1);
1159 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
1161 uasm_l_nopage_tlbs(&l, p);
1162 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1165 if ((p - handle_tlbs) > FASTPATH_SIZE)
1166 panic("TLB store handler fastpath space exceeded");
1168 uasm_resolve_relocs(relocs, labels);
1169 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
1170 (unsigned int)(p - handle_tlbs));
1172 dump_handler(handle_tlbs, ARRAY_SIZE(handle_tlbs));
1175 static void __cpuinit build_r3000_tlb_modify_handler(void)
1177 u32 *p = handle_tlbm;
1178 struct uasm_label *l = labels;
1179 struct uasm_reloc *r = relocs;
1181 memset(handle_tlbm, 0, sizeof(handle_tlbm));
1182 memset(labels, 0, sizeof(labels));
1183 memset(relocs, 0, sizeof(relocs));
1185 build_r3000_tlbchange_handler_head(&p, K0, K1);
1186 build_pte_modifiable(&p, &r, K0, K1, label_nopage_tlbm);
1187 uasm_i_nop(&p); /* load delay */
1188 build_make_write(&p, &r, K0, K1);
1189 build_r3000_pte_reload_tlbwi(&p, K0, K1);
1191 uasm_l_nopage_tlbm(&l, p);
1192 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1195 if ((p - handle_tlbm) > FASTPATH_SIZE)
1196 panic("TLB modify handler fastpath space exceeded");
1198 uasm_resolve_relocs(relocs, labels);
1199 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
1200 (unsigned int)(p - handle_tlbm));
1202 dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm));
1204 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
1207 * R4000 style TLB load/store/modify handlers.
1209 static void __cpuinit
1210 build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l,
1211 struct uasm_reloc **r, unsigned int pte,
1215 build_get_pmde64(p, l, r, pte, ptr); /* get pmd in ptr */
1217 build_get_pgde32(p, pte, ptr); /* get pgd in ptr */
1220 #ifdef CONFIG_HUGETLB_PAGE
1222 * For huge tlb entries, pmd doesn't contain an address but
1223 * instead contains the tlb pte. Check the PAGE_HUGE bit and
1224 * see if we need to jump to huge tlb processing.
1226 build_is_huge_pte(p, r, pte, ptr, label_tlb_huge_update);
1229 UASM_i_MFC0(p, pte, C0_BADVADDR);
1230 UASM_i_LW(p, ptr, 0, ptr);
1231 UASM_i_SRL(p, pte, pte, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2);
1232 uasm_i_andi(p, pte, pte, (PTRS_PER_PTE - 1) << PTE_T_LOG2);
1233 UASM_i_ADDU(p, ptr, ptr, pte);
1236 uasm_l_smp_pgtable_change(l, *p);
1238 iPTE_LW(p, pte, ptr); /* get even pte */
1239 if (!m4kc_tlbp_war())
1240 build_tlb_probe_entry(p);
1243 static void __cpuinit
1244 build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l,
1245 struct uasm_reloc **r, unsigned int tmp,
1248 uasm_i_ori(p, ptr, ptr, sizeof(pte_t));
1249 uasm_i_xori(p, ptr, ptr, sizeof(pte_t));
1250 build_update_entries(p, tmp, ptr);
1251 build_tlb_write_entry(p, l, r, tlb_indexed);
1252 uasm_l_leave(l, *p);
1253 uasm_i_eret(p); /* return from trap */
1256 build_get_pgd_vmalloc64(p, l, r, tmp, ptr);
1260 static void __cpuinit build_r4000_tlb_load_handler(void)
1262 u32 *p = handle_tlbl;
1263 struct uasm_label *l = labels;
1264 struct uasm_reloc *r = relocs;
1266 memset(handle_tlbl, 0, sizeof(handle_tlbl));
1267 memset(labels, 0, sizeof(labels));
1268 memset(relocs, 0, sizeof(relocs));
1270 if (bcm1250_m3_war()) {
1271 UASM_i_MFC0(&p, K0, C0_BADVADDR);
1272 UASM_i_MFC0(&p, K1, C0_ENTRYHI);
1273 uasm_i_xor(&p, K0, K0, K1);
1274 UASM_i_SRL(&p, K0, K0, PAGE_SHIFT + 1);
1275 uasm_il_bnez(&p, &r, K0, label_leave);
1276 /* No need for uasm_i_nop */
1279 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1);
1280 build_pte_present(&p, &r, K0, K1, label_nopage_tlbl);
1281 if (m4kc_tlbp_war())
1282 build_tlb_probe_entry(&p);
1283 build_make_valid(&p, &r, K0, K1);
1284 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1);
1286 #ifdef CONFIG_HUGETLB_PAGE
1288 * This is the entry point when build_r4000_tlbchange_handler_head
1289 * spots a huge page.
1291 uasm_l_tlb_huge_update(&l, p);
1292 iPTE_LW(&p, K0, K1);
1293 build_pte_present(&p, &r, K0, K1, label_nopage_tlbl);
1294 build_tlb_probe_entry(&p);
1295 uasm_i_ori(&p, K0, K0, (_PAGE_ACCESSED | _PAGE_VALID));
1296 build_huge_handler_tail(&p, &r, &l, K0, K1);
1299 uasm_l_nopage_tlbl(&l, p);
1300 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
1303 if ((p - handle_tlbl) > FASTPATH_SIZE)
1304 panic("TLB load handler fastpath space exceeded");
1306 uasm_resolve_relocs(relocs, labels);
1307 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
1308 (unsigned int)(p - handle_tlbl));
1310 dump_handler(handle_tlbl, ARRAY_SIZE(handle_tlbl));
1313 static void __cpuinit build_r4000_tlb_store_handler(void)
1315 u32 *p = handle_tlbs;
1316 struct uasm_label *l = labels;
1317 struct uasm_reloc *r = relocs;
1319 memset(handle_tlbs, 0, sizeof(handle_tlbs));
1320 memset(labels, 0, sizeof(labels));
1321 memset(relocs, 0, sizeof(relocs));
1323 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1);
1324 build_pte_writable(&p, &r, K0, K1, label_nopage_tlbs);
1325 if (m4kc_tlbp_war())
1326 build_tlb_probe_entry(&p);
1327 build_make_write(&p, &r, K0, K1);
1328 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1);
1330 #ifdef CONFIG_HUGETLB_PAGE
1332 * This is the entry point when
1333 * build_r4000_tlbchange_handler_head spots a huge page.
1335 uasm_l_tlb_huge_update(&l, p);
1336 iPTE_LW(&p, K0, K1);
1337 build_pte_writable(&p, &r, K0, K1, label_nopage_tlbs);
1338 build_tlb_probe_entry(&p);
1339 uasm_i_ori(&p, K0, K0,
1340 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY);
1341 build_huge_handler_tail(&p, &r, &l, K0, K1);
1344 uasm_l_nopage_tlbs(&l, p);
1345 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1348 if ((p - handle_tlbs) > FASTPATH_SIZE)
1349 panic("TLB store handler fastpath space exceeded");
1351 uasm_resolve_relocs(relocs, labels);
1352 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
1353 (unsigned int)(p - handle_tlbs));
1355 dump_handler(handle_tlbs, ARRAY_SIZE(handle_tlbs));
1358 static void __cpuinit build_r4000_tlb_modify_handler(void)
1360 u32 *p = handle_tlbm;
1361 struct uasm_label *l = labels;
1362 struct uasm_reloc *r = relocs;
1364 memset(handle_tlbm, 0, sizeof(handle_tlbm));
1365 memset(labels, 0, sizeof(labels));
1366 memset(relocs, 0, sizeof(relocs));
1368 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1);
1369 build_pte_modifiable(&p, &r, K0, K1, label_nopage_tlbm);
1370 if (m4kc_tlbp_war())
1371 build_tlb_probe_entry(&p);
1372 /* Present and writable bits set, set accessed and dirty bits. */
1373 build_make_write(&p, &r, K0, K1);
1374 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1);
1376 #ifdef CONFIG_HUGETLB_PAGE
1378 * This is the entry point when
1379 * build_r4000_tlbchange_handler_head spots a huge page.
1381 uasm_l_tlb_huge_update(&l, p);
1382 iPTE_LW(&p, K0, K1);
1383 build_pte_modifiable(&p, &r, K0, K1, label_nopage_tlbm);
1384 build_tlb_probe_entry(&p);
1385 uasm_i_ori(&p, K0, K0,
1386 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY);
1387 build_huge_handler_tail(&p, &r, &l, K0, K1);
1390 uasm_l_nopage_tlbm(&l, p);
1391 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1394 if ((p - handle_tlbm) > FASTPATH_SIZE)
1395 panic("TLB modify handler fastpath space exceeded");
1397 uasm_resolve_relocs(relocs, labels);
1398 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
1399 (unsigned int)(p - handle_tlbm));
1401 dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm));
1404 void __cpuinit build_tlb_refill_handler(void)
1407 * The refill handler is generated per-CPU, multi-node systems
1408 * may have local storage for it. The other handlers are only
1411 static int run_once = 0;
1413 switch (current_cpu_type()) {
1421 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
1422 build_r3000_tlb_refill_handler();
1424 build_r3000_tlb_load_handler();
1425 build_r3000_tlb_store_handler();
1426 build_r3000_tlb_modify_handler();
1430 panic("No R3000 TLB refill handler");
1436 panic("No R6000 TLB refill handler yet");
1440 panic("No R8000 TLB refill handler yet");
1444 build_r4000_tlb_refill_handler();
1446 build_r4000_tlb_load_handler();
1447 build_r4000_tlb_store_handler();
1448 build_r4000_tlb_modify_handler();
1454 void __cpuinit flush_tlb_handlers(void)
1456 local_flush_icache_range((unsigned long)handle_tlbl,
1457 (unsigned long)handle_tlbl + sizeof(handle_tlbl));
1458 local_flush_icache_range((unsigned long)handle_tlbs,
1459 (unsigned long)handle_tlbs + sizeof(handle_tlbs));
1460 local_flush_icache_range((unsigned long)handle_tlbm,
1461 (unsigned long)handle_tlbm + sizeof(handle_tlbm));