2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
7 * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
10 #include <linux/hardirq.h>
11 #include <linux/init.h>
12 #include <linux/highmem.h>
13 #include <linux/kernel.h>
14 #include <linux/linkage.h>
15 #include <linux/sched.h>
16 #include <linux/smp.h>
18 #include <linux/module.h>
19 #include <linux/bitops.h>
21 #include <asm/bcache.h>
22 #include <asm/bootinfo.h>
23 #include <asm/cache.h>
24 #include <asm/cacheops.h>
26 #include <asm/cpu-features.h>
29 #include <asm/pgtable.h>
30 #include <asm/r4kcache.h>
31 #include <asm/sections.h>
32 #include <asm/mmu_context.h>
34 #include <asm/cacheflush.h> /* for run_uncached() */
35 #include <asm/traps.h>
38 * Special Variant of smp_call_function for use by cache functions:
41 * o collapses to normal function call on UP kernels
42 * o collapses to normal function call on systems with a single shared
44 * o doesn't disable interrupts on the local CPU
46 static inline void r4k_on_each_cpu(void (*func) (void *info), void *info)
50 #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
51 smp_call_function(func, info, 1);
57 #if defined(CONFIG_MIPS_CMP)
58 #define cpu_has_safe_index_cacheops 0
60 #define cpu_has_safe_index_cacheops 1
66 static unsigned long icache_size __read_mostly;
67 static unsigned long dcache_size __read_mostly;
68 static unsigned long scache_size __read_mostly;
71 * Dummy cache handling routines for machines without boardcaches
73 static void cache_noop(void) {}
75 static struct bcache_ops no_sc_ops = {
76 .bc_enable = (void *)cache_noop,
77 .bc_disable = (void *)cache_noop,
78 .bc_wback_inv = (void *)cache_noop,
79 .bc_inv = (void *)cache_noop
82 struct bcache_ops *bcops = &no_sc_ops;
84 #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010)
85 #define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020)
87 #define R4600_HIT_CACHEOP_WAR_IMPL \
89 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \
90 *(volatile unsigned long *)CKSEG1; \
91 if (R4600_V1_HIT_CACHEOP_WAR) \
92 __asm__ __volatile__("nop;nop;nop;nop"); \
95 static void (*r4k_blast_dcache_page)(unsigned long addr);
97 static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
99 R4600_HIT_CACHEOP_WAR_IMPL;
100 blast_dcache32_page(addr);
103 static inline void r4k_blast_dcache_page_dc64(unsigned long addr)
105 R4600_HIT_CACHEOP_WAR_IMPL;
106 blast_dcache64_page(addr);
109 static void __cpuinit r4k_blast_dcache_page_setup(void)
111 unsigned long dc_lsize = cpu_dcache_line_size();
114 r4k_blast_dcache_page = (void *)cache_noop;
115 else if (dc_lsize == 16)
116 r4k_blast_dcache_page = blast_dcache16_page;
117 else if (dc_lsize == 32)
118 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
119 else if (dc_lsize == 64)
120 r4k_blast_dcache_page = r4k_blast_dcache_page_dc64;
123 static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
125 static void __cpuinit r4k_blast_dcache_page_indexed_setup(void)
127 unsigned long dc_lsize = cpu_dcache_line_size();
130 r4k_blast_dcache_page_indexed = (void *)cache_noop;
131 else if (dc_lsize == 16)
132 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
133 else if (dc_lsize == 32)
134 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
135 else if (dc_lsize == 64)
136 r4k_blast_dcache_page_indexed = blast_dcache64_page_indexed;
139 void (* r4k_blast_dcache)(void);
140 EXPORT_SYMBOL(r4k_blast_dcache);
142 static void __cpuinit r4k_blast_dcache_setup(void)
144 unsigned long dc_lsize = cpu_dcache_line_size();
147 r4k_blast_dcache = (void *)cache_noop;
148 else if (dc_lsize == 16)
149 r4k_blast_dcache = blast_dcache16;
150 else if (dc_lsize == 32)
151 r4k_blast_dcache = blast_dcache32;
152 else if (dc_lsize == 64)
153 r4k_blast_dcache = blast_dcache64;
156 /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
157 #define JUMP_TO_ALIGN(order) \
158 __asm__ __volatile__( \
160 ".align\t" #order "\n\t" \
163 #define CACHE32_UNROLL32_ALIGN JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */
164 #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11)
166 static inline void blast_r4600_v1_icache32(void)
170 local_irq_save(flags);
172 local_irq_restore(flags);
175 static inline void tx49_blast_icache32(void)
177 unsigned long start = INDEX_BASE;
178 unsigned long end = start + current_cpu_data.icache.waysize;
179 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
180 unsigned long ws_end = current_cpu_data.icache.ways <<
181 current_cpu_data.icache.waybit;
182 unsigned long ws, addr;
184 CACHE32_UNROLL32_ALIGN2;
185 /* I'm in even chunk. blast odd chunks */
186 for (ws = 0; ws < ws_end; ws += ws_inc)
187 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
188 cache32_unroll32(addr|ws, Index_Invalidate_I);
189 CACHE32_UNROLL32_ALIGN;
190 /* I'm in odd chunk. blast even chunks */
191 for (ws = 0; ws < ws_end; ws += ws_inc)
192 for (addr = start; addr < end; addr += 0x400 * 2)
193 cache32_unroll32(addr|ws, Index_Invalidate_I);
196 static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page)
200 local_irq_save(flags);
201 blast_icache32_page_indexed(page);
202 local_irq_restore(flags);
205 static inline void tx49_blast_icache32_page_indexed(unsigned long page)
207 unsigned long indexmask = current_cpu_data.icache.waysize - 1;
208 unsigned long start = INDEX_BASE + (page & indexmask);
209 unsigned long end = start + PAGE_SIZE;
210 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
211 unsigned long ws_end = current_cpu_data.icache.ways <<
212 current_cpu_data.icache.waybit;
213 unsigned long ws, addr;
215 CACHE32_UNROLL32_ALIGN2;
216 /* I'm in even chunk. blast odd chunks */
217 for (ws = 0; ws < ws_end; ws += ws_inc)
218 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
219 cache32_unroll32(addr|ws, Index_Invalidate_I);
220 CACHE32_UNROLL32_ALIGN;
221 /* I'm in odd chunk. blast even chunks */
222 for (ws = 0; ws < ws_end; ws += ws_inc)
223 for (addr = start; addr < end; addr += 0x400 * 2)
224 cache32_unroll32(addr|ws, Index_Invalidate_I);
227 static void (* r4k_blast_icache_page)(unsigned long addr);
229 static void __cpuinit r4k_blast_icache_page_setup(void)
231 unsigned long ic_lsize = cpu_icache_line_size();
234 r4k_blast_icache_page = (void *)cache_noop;
235 else if (ic_lsize == 16)
236 r4k_blast_icache_page = blast_icache16_page;
237 else if (ic_lsize == 32)
238 r4k_blast_icache_page = blast_icache32_page;
239 else if (ic_lsize == 64)
240 r4k_blast_icache_page = blast_icache64_page;
244 static void (* r4k_blast_icache_page_indexed)(unsigned long addr);
246 static void __cpuinit r4k_blast_icache_page_indexed_setup(void)
248 unsigned long ic_lsize = cpu_icache_line_size();
251 r4k_blast_icache_page_indexed = (void *)cache_noop;
252 else if (ic_lsize == 16)
253 r4k_blast_icache_page_indexed = blast_icache16_page_indexed;
254 else if (ic_lsize == 32) {
255 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
256 r4k_blast_icache_page_indexed =
257 blast_icache32_r4600_v1_page_indexed;
258 else if (TX49XX_ICACHE_INDEX_INV_WAR)
259 r4k_blast_icache_page_indexed =
260 tx49_blast_icache32_page_indexed;
262 r4k_blast_icache_page_indexed =
263 blast_icache32_page_indexed;
264 } else if (ic_lsize == 64)
265 r4k_blast_icache_page_indexed = blast_icache64_page_indexed;
268 void (* r4k_blast_icache)(void);
269 EXPORT_SYMBOL(r4k_blast_icache);
271 static void __cpuinit r4k_blast_icache_setup(void)
273 unsigned long ic_lsize = cpu_icache_line_size();
276 r4k_blast_icache = (void *)cache_noop;
277 else if (ic_lsize == 16)
278 r4k_blast_icache = blast_icache16;
279 else if (ic_lsize == 32) {
280 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
281 r4k_blast_icache = blast_r4600_v1_icache32;
282 else if (TX49XX_ICACHE_INDEX_INV_WAR)
283 r4k_blast_icache = tx49_blast_icache32;
285 r4k_blast_icache = blast_icache32;
286 } else if (ic_lsize == 64)
287 r4k_blast_icache = blast_icache64;
290 static void (* r4k_blast_scache_page)(unsigned long addr);
292 static void __cpuinit r4k_blast_scache_page_setup(void)
294 unsigned long sc_lsize = cpu_scache_line_size();
296 if (scache_size == 0)
297 r4k_blast_scache_page = (void *)cache_noop;
298 else if (sc_lsize == 16)
299 r4k_blast_scache_page = blast_scache16_page;
300 else if (sc_lsize == 32)
301 r4k_blast_scache_page = blast_scache32_page;
302 else if (sc_lsize == 64)
303 r4k_blast_scache_page = blast_scache64_page;
304 else if (sc_lsize == 128)
305 r4k_blast_scache_page = blast_scache128_page;
308 static void (* r4k_blast_scache_page_indexed)(unsigned long addr);
310 static void __cpuinit r4k_blast_scache_page_indexed_setup(void)
312 unsigned long sc_lsize = cpu_scache_line_size();
314 if (scache_size == 0)
315 r4k_blast_scache_page_indexed = (void *)cache_noop;
316 else if (sc_lsize == 16)
317 r4k_blast_scache_page_indexed = blast_scache16_page_indexed;
318 else if (sc_lsize == 32)
319 r4k_blast_scache_page_indexed = blast_scache32_page_indexed;
320 else if (sc_lsize == 64)
321 r4k_blast_scache_page_indexed = blast_scache64_page_indexed;
322 else if (sc_lsize == 128)
323 r4k_blast_scache_page_indexed = blast_scache128_page_indexed;
326 static void (* r4k_blast_scache)(void);
328 static void __cpuinit r4k_blast_scache_setup(void)
330 unsigned long sc_lsize = cpu_scache_line_size();
332 if (scache_size == 0)
333 r4k_blast_scache = (void *)cache_noop;
334 else if (sc_lsize == 16)
335 r4k_blast_scache = blast_scache16;
336 else if (sc_lsize == 32)
337 r4k_blast_scache = blast_scache32;
338 else if (sc_lsize == 64)
339 r4k_blast_scache = blast_scache64;
340 else if (sc_lsize == 128)
341 r4k_blast_scache = blast_scache128;
344 static inline void local_r4k___flush_cache_all(void * args)
346 #if defined(CONFIG_CPU_LOONGSON2)
353 switch (current_cpu_type()) {
365 static void r4k___flush_cache_all(void)
367 r4k_on_each_cpu(local_r4k___flush_cache_all, NULL);
370 static inline int has_valid_asid(const struct mm_struct *mm)
372 #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
375 for_each_online_cpu(i)
376 if (cpu_context(i, mm))
381 return cpu_context(smp_processor_id(), mm);
385 static void r4k__flush_cache_vmap(void)
390 static void r4k__flush_cache_vunmap(void)
395 static inline void local_r4k_flush_cache_range(void * args)
397 struct vm_area_struct *vma = args;
398 int exec = vma->vm_flags & VM_EXEC;
400 if (!(has_valid_asid(vma->vm_mm)))
408 static void r4k_flush_cache_range(struct vm_area_struct *vma,
409 unsigned long start, unsigned long end)
411 int exec = vma->vm_flags & VM_EXEC;
413 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc))
414 r4k_on_each_cpu(local_r4k_flush_cache_range, vma);
417 static inline void local_r4k_flush_cache_mm(void * args)
419 struct mm_struct *mm = args;
421 if (!has_valid_asid(mm))
425 * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we
426 * only flush the primary caches but R10000 and R12000 behave sane ...
427 * R4000SC and R4400SC indexed S-cache ops also invalidate primary
428 * caches, so we can bail out early.
430 if (current_cpu_type() == CPU_R4000SC ||
431 current_cpu_type() == CPU_R4000MC ||
432 current_cpu_type() == CPU_R4400SC ||
433 current_cpu_type() == CPU_R4400MC) {
441 static void r4k_flush_cache_mm(struct mm_struct *mm)
443 if (!cpu_has_dc_aliases)
446 r4k_on_each_cpu(local_r4k_flush_cache_mm, mm);
449 struct flush_cache_page_args {
450 struct vm_area_struct *vma;
455 static inline void local_r4k_flush_cache_page(void *args)
457 struct flush_cache_page_args *fcp_args = args;
458 struct vm_area_struct *vma = fcp_args->vma;
459 unsigned long addr = fcp_args->addr;
460 struct page *page = pfn_to_page(fcp_args->pfn);
461 int exec = vma->vm_flags & VM_EXEC;
462 struct mm_struct *mm = vma->vm_mm;
463 int map_coherent = 0;
471 * If ownes no valid ASID yet, cannot possibly have gotten
472 * this page into the cache.
474 if (!has_valid_asid(mm))
478 pgdp = pgd_offset(mm, addr);
479 pudp = pud_offset(pgdp, addr);
480 pmdp = pmd_offset(pudp, addr);
481 ptep = pte_offset(pmdp, addr);
484 * If the page isn't marked valid, the page cannot possibly be
487 if (!(pte_present(*ptep)))
490 if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID))
494 * Use kmap_coherent or kmap_atomic to do flushes for
495 * another ASID than the current one.
497 map_coherent = (cpu_has_dc_aliases &&
498 page_mapped(page) && !Page_dcache_dirty(page));
500 vaddr = kmap_coherent(page, addr);
502 vaddr = kmap_atomic(page);
503 addr = (unsigned long)vaddr;
506 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
507 r4k_blast_dcache_page(addr);
508 if (exec && !cpu_icache_snoops_remote_store)
509 r4k_blast_scache_page(addr);
512 if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) {
513 int cpu = smp_processor_id();
515 if (cpu_context(cpu, mm) != 0)
516 drop_mmu_context(mm, cpu);
518 r4k_blast_icache_page(addr);
525 kunmap_atomic(vaddr);
529 static void r4k_flush_cache_page(struct vm_area_struct *vma,
530 unsigned long addr, unsigned long pfn)
532 struct flush_cache_page_args args;
538 r4k_on_each_cpu(local_r4k_flush_cache_page, &args);
541 static inline void local_r4k_flush_data_cache_page(void * addr)
543 r4k_blast_dcache_page((unsigned long) addr);
546 static void r4k_flush_data_cache_page(unsigned long addr)
549 local_r4k_flush_data_cache_page((void *)addr);
551 r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr);
554 struct flush_icache_range_args {
559 static inline void local_r4k_flush_icache_range(unsigned long start, unsigned long end)
561 if (!cpu_has_ic_fills_f_dc) {
562 if (end - start >= dcache_size) {
565 R4600_HIT_CACHEOP_WAR_IMPL;
566 protected_blast_dcache_range(start, end);
570 if (end - start > icache_size)
573 protected_blast_icache_range(start, end);
576 static inline void local_r4k_flush_icache_range_ipi(void *args)
578 struct flush_icache_range_args *fir_args = args;
579 unsigned long start = fir_args->start;
580 unsigned long end = fir_args->end;
582 local_r4k_flush_icache_range(start, end);
585 static void r4k_flush_icache_range(unsigned long start, unsigned long end)
587 struct flush_icache_range_args args;
592 r4k_on_each_cpu(local_r4k_flush_icache_range_ipi, &args);
593 instruction_hazard();
596 #ifdef CONFIG_DMA_NONCOHERENT
598 static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
600 /* Catch bad driver code */
603 if (cpu_has_inclusive_pcaches) {
604 if (size >= scache_size)
607 blast_scache_range(addr, addr + size);
613 * Either no secondary cache or the available caches don't have the
614 * subset property so we have to flush the primary caches
617 if (cpu_has_safe_index_cacheops && size >= dcache_size) {
620 R4600_HIT_CACHEOP_WAR_IMPL;
621 blast_dcache_range(addr, addr + size);
624 bc_wback_inv(addr, size);
628 static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
630 /* Catch bad driver code */
633 if (cpu_has_inclusive_pcaches) {
634 if (size >= scache_size)
638 * There is no clearly documented alignment requirement
639 * for the cache instruction on MIPS processors and
640 * some processors, among them the RM5200 and RM7000
641 * QED processors will throw an address error for cache
642 * hit ops with insufficient alignment. Solved by
643 * aligning the address to cache line size.
645 blast_inv_scache_range(addr, addr + size);
651 if (cpu_has_safe_index_cacheops && size >= dcache_size) {
654 R4600_HIT_CACHEOP_WAR_IMPL;
655 blast_inv_dcache_range(addr, addr + size);
661 #endif /* CONFIG_DMA_NONCOHERENT */
664 * While we're protected against bad userland addresses we don't care
665 * very much about what happens in that case. Usually a segmentation
666 * fault will dump the process later on anyway ...
668 static void local_r4k_flush_cache_sigtramp(void * arg)
670 unsigned long ic_lsize = cpu_icache_line_size();
671 unsigned long dc_lsize = cpu_dcache_line_size();
672 unsigned long sc_lsize = cpu_scache_line_size();
673 unsigned long addr = (unsigned long) arg;
675 R4600_HIT_CACHEOP_WAR_IMPL;
677 protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
678 if (!cpu_icache_snoops_remote_store && scache_size)
679 protected_writeback_scache_line(addr & ~(sc_lsize - 1));
681 protected_flush_icache_line(addr & ~(ic_lsize - 1));
682 if (MIPS4K_ICACHE_REFILL_WAR) {
683 __asm__ __volatile__ (
698 : "i" (Hit_Invalidate_I));
700 if (MIPS_CACHE_SYNC_WAR)
701 __asm__ __volatile__ ("sync");
704 static void r4k_flush_cache_sigtramp(unsigned long addr)
706 r4k_on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr);
709 static void r4k_flush_icache_all(void)
711 if (cpu_has_vtag_icache)
715 struct flush_kernel_vmap_range_args {
720 static inline void local_r4k_flush_kernel_vmap_range(void *args)
722 struct flush_kernel_vmap_range_args *vmra = args;
723 unsigned long vaddr = vmra->vaddr;
724 int size = vmra->size;
727 * Aliases only affect the primary caches so don't bother with
728 * S-caches or T-caches.
730 if (cpu_has_safe_index_cacheops && size >= dcache_size)
733 R4600_HIT_CACHEOP_WAR_IMPL;
734 blast_dcache_range(vaddr, vaddr + size);
738 static void r4k_flush_kernel_vmap_range(unsigned long vaddr, int size)
740 struct flush_kernel_vmap_range_args args;
742 args.vaddr = (unsigned long) vaddr;
745 r4k_on_each_cpu(local_r4k_flush_kernel_vmap_range, &args);
748 static inline void rm7k_erratum31(void)
750 const unsigned long ic_lsize = 32;
753 /* RM7000 erratum #31. The icache is screwed at startup. */
757 for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) {
758 __asm__ __volatile__ (
762 "cache\t%1, 0(%0)\n\t"
763 "cache\t%1, 0x1000(%0)\n\t"
764 "cache\t%1, 0x2000(%0)\n\t"
765 "cache\t%1, 0x3000(%0)\n\t"
766 "cache\t%2, 0(%0)\n\t"
767 "cache\t%2, 0x1000(%0)\n\t"
768 "cache\t%2, 0x2000(%0)\n\t"
769 "cache\t%2, 0x3000(%0)\n\t"
770 "cache\t%1, 0(%0)\n\t"
771 "cache\t%1, 0x1000(%0)\n\t"
772 "cache\t%1, 0x2000(%0)\n\t"
773 "cache\t%1, 0x3000(%0)\n\t"
776 : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill));
780 static inline void alias_74k_erratum(struct cpuinfo_mips *c)
783 * Early versions of the 74K do not update the cache tags on a
784 * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG
785 * aliases. In this case it is better to treat the cache as always
788 if ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(2, 4, 0))
789 c->dcache.flags |= MIPS_CACHE_VTAG;
790 if ((c->processor_id & 0xff) == PRID_REV_ENCODE_332(2, 4, 0))
791 write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
792 if (((c->processor_id & 0xff00) == PRID_IMP_1074K) &&
793 ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(1, 1, 0))) {
794 c->dcache.flags |= MIPS_CACHE_VTAG;
795 write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
799 static char *way_string[] __cpuinitdata = { NULL, "direct mapped", "2-way",
800 "3-way", "4-way", "5-way", "6-way", "7-way", "8-way"
803 static void __cpuinit probe_pcache(void)
805 struct cpuinfo_mips *c = ¤t_cpu_data;
806 unsigned int config = read_c0_config();
807 unsigned int prid = read_c0_prid();
808 unsigned long config1;
811 switch (c->cputype) {
812 case CPU_R4600: /* QED style two way caches? */
816 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
817 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
819 c->icache.waybit = __ffs(icache_size/2);
821 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
822 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
824 c->dcache.waybit= __ffs(dcache_size/2);
826 c->options |= MIPS_CPU_CACHE_CDEX_P;
831 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
832 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
836 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
837 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
839 c->dcache.waybit = 0;
841 c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH;
845 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
846 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
850 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
851 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
853 c->dcache.waybit = 0;
855 c->options |= MIPS_CPU_CACHE_CDEX_P;
856 c->options |= MIPS_CPU_PREFETCH;
866 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
867 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
869 c->icache.waybit = 0; /* doesn't matter */
871 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
872 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
874 c->dcache.waybit = 0; /* does not matter */
876 c->options |= MIPS_CPU_CACHE_CDEX_P;
882 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29));
883 c->icache.linesz = 64;
885 c->icache.waybit = 0;
887 dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26));
888 c->dcache.linesz = 32;
890 c->dcache.waybit = 0;
892 c->options |= MIPS_CPU_PREFETCH;
896 write_c0_config(config & ~VR41_CONF_P4K);
898 /* Workaround for cache instruction bug of VR4131 */
899 if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U ||
900 c->processor_id == 0x0c82U) {
901 config |= 0x00400000U;
902 if (c->processor_id == 0x0c80U)
903 config |= VR41_CONF_BP;
904 write_c0_config(config);
906 c->options |= MIPS_CPU_CACHE_CDEX_P;
908 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
909 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
911 c->icache.waybit = __ffs(icache_size/2);
913 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
914 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
916 c->dcache.waybit = __ffs(dcache_size/2);
925 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
926 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
928 c->icache.waybit = 0; /* doesn't matter */
930 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
931 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
933 c->dcache.waybit = 0; /* does not matter */
935 c->options |= MIPS_CPU_CACHE_CDEX_P;
941 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
942 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
944 c->icache.waybit = __ffs(icache_size / c->icache.ways);
946 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
947 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
949 c->dcache.waybit = __ffs(dcache_size / c->dcache.ways);
951 c->options |= MIPS_CPU_CACHE_CDEX_P;
952 c->options |= MIPS_CPU_PREFETCH;
956 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
957 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
962 c->icache.waybit = 0;
964 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
965 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
970 c->dcache.waybit = 0;
974 if (!(config & MIPS_CONF_M))
975 panic("Don't know how to probe P-caches on this cpu.");
978 * So we seem to be a MIPS32 or MIPS64 CPU
979 * So let's probe the I-cache ...
981 config1 = read_c0_config1();
983 if ((lsize = ((config1 >> 19) & 7)))
984 c->icache.linesz = 2 << lsize;
986 c->icache.linesz = lsize;
987 c->icache.sets = 32 << (((config1 >> 22) + 1) & 7);
988 c->icache.ways = 1 + ((config1 >> 16) & 7);
990 icache_size = c->icache.sets *
993 c->icache.waybit = __ffs(icache_size/c->icache.ways);
995 if (config & 0x8) /* VI bit */
996 c->icache.flags |= MIPS_CACHE_VTAG;
999 * Now probe the MIPS32 / MIPS64 data cache.
1001 c->dcache.flags = 0;
1003 if ((lsize = ((config1 >> 10) & 7)))
1004 c->dcache.linesz = 2 << lsize;
1006 c->dcache.linesz= lsize;
1007 c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7);
1008 c->dcache.ways = 1 + ((config1 >> 7) & 7);
1010 dcache_size = c->dcache.sets *
1013 c->dcache.waybit = __ffs(dcache_size/c->dcache.ways);
1015 c->options |= MIPS_CPU_PREFETCH;
1020 * Processor configuration sanity check for the R4000SC erratum
1021 * #5. With page sizes larger than 32kB there is no possibility
1022 * to get a VCE exception anymore so we don't care about this
1023 * misconfiguration. The case is rather theoretical anyway;
1024 * presumably no vendor is shipping his hardware in the "bad"
1027 if ((prid & 0xff00) == PRID_IMP_R4000 && (prid & 0xff) < 0x40 &&
1028 !(config & CONF_SC) && c->icache.linesz != 16 &&
1029 PAGE_SIZE <= 0x8000)
1030 panic("Improper R4000SC processor configuration detected");
1032 /* compute a couple of other cache variables */
1033 c->icache.waysize = icache_size / c->icache.ways;
1034 c->dcache.waysize = dcache_size / c->dcache.ways;
1036 c->icache.sets = c->icache.linesz ?
1037 icache_size / (c->icache.linesz * c->icache.ways) : 0;
1038 c->dcache.sets = c->dcache.linesz ?
1039 dcache_size / (c->dcache.linesz * c->dcache.ways) : 0;
1042 * R10000 and R12000 P-caches are odd in a positive way. They're 32kB
1043 * 2-way virtually indexed so normally would suffer from aliases. So
1044 * normally they'd suffer from aliases but magic in the hardware deals
1045 * with that for us so we don't need to take care ourselves.
1047 switch (c->cputype) {
1053 c->dcache.flags |= MIPS_CACHE_PINDEX;
1067 if (c->cputype == CPU_74K)
1068 alias_74k_erratum(c);
1069 if ((read_c0_config7() & (1 << 16))) {
1070 /* effectively physically indexed dcache,
1071 thus no virtual aliases. */
1072 c->dcache.flags |= MIPS_CACHE_PINDEX;
1076 if (c->dcache.waysize > PAGE_SIZE)
1077 c->dcache.flags |= MIPS_CACHE_ALIASES;
1080 switch (c->cputype) {
1083 * Some older 20Kc chips doesn't have the 'VI' bit in
1084 * the config register.
1086 c->icache.flags |= MIPS_CACHE_VTAG;
1090 c->icache.flags |= MIPS_CACHE_IC_F_DC;
1094 #ifdef CONFIG_CPU_LOONGSON2
1096 * LOONGSON2 has 4 way icache, but when using indexed cache op,
1097 * one op will act on all 4 ways
1102 printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
1104 c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT",
1105 way_string[c->icache.ways], c->icache.linesz);
1107 printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",
1108 dcache_size >> 10, way_string[c->dcache.ways],
1109 (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT",
1110 (c->dcache.flags & MIPS_CACHE_ALIASES) ?
1111 "cache aliases" : "no aliases",
1116 * If you even _breathe_ on this function, look at the gcc output and make sure
1117 * it does not pop things on and off the stack for the cache sizing loop that
1118 * executes in KSEG1 space or else you will crash and burn badly. You have
1121 static int __cpuinit probe_scache(void)
1123 unsigned long flags, addr, begin, end, pow2;
1124 unsigned int config = read_c0_config();
1125 struct cpuinfo_mips *c = ¤t_cpu_data;
1127 if (config & CONF_SC)
1130 begin = (unsigned long) &_stext;
1131 begin &= ~((4 * 1024 * 1024) - 1);
1132 end = begin + (4 * 1024 * 1024);
1135 * This is such a bitch, you'd think they would make it easy to do
1136 * this. Away you daemons of stupidity!
1138 local_irq_save(flags);
1140 /* Fill each size-multiple cache line with a valid tag. */
1142 for (addr = begin; addr < end; addr = (begin + pow2)) {
1143 unsigned long *p = (unsigned long *) addr;
1144 __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */
1148 /* Load first line with zero (therefore invalid) tag. */
1151 __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
1152 cache_op(Index_Store_Tag_I, begin);
1153 cache_op(Index_Store_Tag_D, begin);
1154 cache_op(Index_Store_Tag_SD, begin);
1156 /* Now search for the wrap around point. */
1157 pow2 = (128 * 1024);
1158 for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) {
1159 cache_op(Index_Load_Tag_SD, addr);
1160 __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */
1161 if (!read_c0_taglo())
1165 local_irq_restore(flags);
1169 c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22);
1171 c->dcache.waybit = 0; /* does not matter */
1176 #if defined(CONFIG_CPU_LOONGSON2)
1177 static void __init loongson2_sc_init(void)
1179 struct cpuinfo_mips *c = ¤t_cpu_data;
1181 scache_size = 512*1024;
1182 c->scache.linesz = 32;
1184 c->scache.waybit = 0;
1185 c->scache.waysize = scache_size / (c->scache.ways);
1186 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1187 pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1188 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1190 c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1194 extern int r5k_sc_init(void);
1195 extern int rm7k_sc_init(void);
1196 extern int mips_sc_init(void);
1198 static void __cpuinit setup_scache(void)
1200 struct cpuinfo_mips *c = ¤t_cpu_data;
1201 unsigned int config = read_c0_config();
1205 * Do the probing thing on R4000SC and R4400SC processors. Other
1206 * processors don't have a S-cache that would be relevant to the
1207 * Linux memory management.
1209 switch (c->cputype) {
1214 sc_present = run_uncached(probe_scache);
1216 c->options |= MIPS_CPU_CACHE_CDEX_S;
1222 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16);
1223 c->scache.linesz = 64 << ((config >> 13) & 1);
1225 c->scache.waybit= 0;
1231 #ifdef CONFIG_R5000_CPU_SCACHE
1237 #ifdef CONFIG_RM7000_CPU_SCACHE
1242 #if defined(CONFIG_CPU_LOONGSON2)
1244 loongson2_sc_init();
1248 /* don't need to worry about L2, fully coherent */
1252 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
1253 MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
1254 #ifdef CONFIG_MIPS_CPU_SCACHE
1255 if (mips_sc_init ()) {
1256 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
1257 printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
1259 way_string[c->scache.ways], c->scache.linesz);
1262 if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
1263 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
1273 /* compute a couple of other cache variables */
1274 c->scache.waysize = scache_size / c->scache.ways;
1276 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1278 printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1279 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1281 c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1284 void au1x00_fixup_config_od(void)
1287 * c0_config.od (bit 19) was write only (and read as 0)
1288 * on the early revisions of Alchemy SOCs. It disables the bus
1289 * transaction overlapping and needs to be set to fix various errata.
1291 switch (read_c0_prid()) {
1292 case 0x00030100: /* Au1000 DA */
1293 case 0x00030201: /* Au1000 HA */
1294 case 0x00030202: /* Au1000 HB */
1295 case 0x01030200: /* Au1500 AB */
1297 * Au1100 errata actually keeps silence about this bit, so we set it
1298 * just in case for those revisions that require it to be set according
1299 * to the (now gone) cpu table.
1301 case 0x02030200: /* Au1100 AB */
1302 case 0x02030201: /* Au1100 BA */
1303 case 0x02030202: /* Au1100 BC */
1304 set_c0_config(1 << 19);
1309 /* CP0 hazard avoidance. */
1310 #define NXP_BARRIER() \
1311 __asm__ __volatile__( \
1312 ".set noreorder\n\t" \
1313 "nop; nop; nop; nop; nop; nop;\n\t" \
1316 static void nxp_pr4450_fixup_config(void)
1318 unsigned long config0;
1320 config0 = read_c0_config();
1322 /* clear all three cache coherency fields */
1323 config0 &= ~(0x7 | (7 << 25) | (7 << 28));
1324 config0 |= (((_page_cachable_default >> _CACHE_SHIFT) << 0) |
1325 ((_page_cachable_default >> _CACHE_SHIFT) << 25) |
1326 ((_page_cachable_default >> _CACHE_SHIFT) << 28));
1327 write_c0_config(config0);
1331 static int __cpuinitdata cca = -1;
1333 static int __init cca_setup(char *str)
1335 get_option(&str, &cca);
1340 early_param("cca", cca_setup);
1342 static void __cpuinit coherency_setup(void)
1344 if (cca < 0 || cca > 7)
1345 cca = read_c0_config() & CONF_CM_CMASK;
1346 _page_cachable_default = cca << _CACHE_SHIFT;
1348 pr_debug("Using cache attribute %d\n", cca);
1349 change_c0_config(CONF_CM_CMASK, cca);
1352 * c0_status.cu=0 specifies that updates by the sc instruction use
1353 * the coherency mode specified by the TLB; 1 means cachable
1354 * coherent update on write will be used. Not all processors have
1355 * this bit and; some wire it to zero, others like Toshiba had the
1356 * silly idea of putting something else there ...
1358 switch (current_cpu_type()) {
1365 clear_c0_config(CONF_CU);
1368 * We need to catch the early Alchemy SOCs with
1369 * the write-only co_config.od bit and set it back to one on:
1370 * Au1000 rev DA, HA, HB; Au1100 AB, BA, BC, Au1500 AB
1373 au1x00_fixup_config_od();
1376 case PRID_IMP_PR4450:
1377 nxp_pr4450_fixup_config();
1382 #if defined(CONFIG_DMA_NONCOHERENT)
1384 static int __cpuinitdata coherentio;
1386 static int __init setcoherentio(char *str)
1393 early_param("coherentio", setcoherentio);
1396 static void __cpuinit r4k_cache_error_setup(void)
1398 extern char __weak except_vec2_generic;
1399 extern char __weak except_vec2_sb1;
1400 struct cpuinfo_mips *c = ¤t_cpu_data;
1402 switch (c->cputype) {
1405 set_uncached_handler(0x100, &except_vec2_sb1, 0x80);
1409 set_uncached_handler(0x100, &except_vec2_generic, 0x80);
1414 void __cpuinit r4k_cache_init(void)
1416 extern void build_clear_page(void);
1417 extern void build_copy_page(void);
1418 struct cpuinfo_mips *c = ¤t_cpu_data;
1423 r4k_blast_dcache_page_setup();
1424 r4k_blast_dcache_page_indexed_setup();
1425 r4k_blast_dcache_setup();
1426 r4k_blast_icache_page_setup();
1427 r4k_blast_icache_page_indexed_setup();
1428 r4k_blast_icache_setup();
1429 r4k_blast_scache_page_setup();
1430 r4k_blast_scache_page_indexed_setup();
1431 r4k_blast_scache_setup();
1434 * Some MIPS32 and MIPS64 processors have physically indexed caches.
1435 * This code supports virtually indexed processors and will be
1436 * unnecessarily inefficient on physically indexed processors.
1438 if (c->dcache.linesz)
1439 shm_align_mask = max_t( unsigned long,
1440 c->dcache.sets * c->dcache.linesz - 1,
1443 shm_align_mask = PAGE_SIZE-1;
1445 __flush_cache_vmap = r4k__flush_cache_vmap;
1446 __flush_cache_vunmap = r4k__flush_cache_vunmap;
1448 flush_cache_all = cache_noop;
1449 __flush_cache_all = r4k___flush_cache_all;
1450 flush_cache_mm = r4k_flush_cache_mm;
1451 flush_cache_page = r4k_flush_cache_page;
1452 flush_cache_range = r4k_flush_cache_range;
1454 __flush_kernel_vmap_range = r4k_flush_kernel_vmap_range;
1456 flush_cache_sigtramp = r4k_flush_cache_sigtramp;
1457 flush_icache_all = r4k_flush_icache_all;
1458 local_flush_data_cache_page = local_r4k_flush_data_cache_page;
1459 flush_data_cache_page = r4k_flush_data_cache_page;
1460 flush_icache_range = r4k_flush_icache_range;
1461 local_flush_icache_range = local_r4k_flush_icache_range;
1463 #if defined(CONFIG_DMA_NONCOHERENT)
1465 _dma_cache_wback_inv = (void *)cache_noop;
1466 _dma_cache_wback = (void *)cache_noop;
1467 _dma_cache_inv = (void *)cache_noop;
1469 _dma_cache_wback_inv = r4k_dma_cache_wback_inv;
1470 _dma_cache_wback = r4k_dma_cache_wback_inv;
1471 _dma_cache_inv = r4k_dma_cache_inv;
1477 #if !defined(CONFIG_MIPS_CMP)
1478 local_r4k___flush_cache_all(NULL);
1481 board_cache_error_setup = r4k_cache_error_setup;