2 * IEEE754 floating point arithmetic
3 * double precision: MADDF.f (Fused Multiply Add)
4 * MADDF.fmt: FPR[fd] = FPR[fd] + (FPR[fs] x FPR[ft])
6 * MIPS floating point support
7 * Copyright (C) 2015 Imagination Technologies, Ltd.
8 * Author: Markos Chandras <markos.chandras@imgtec.com>
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; version 2 of the License.
15 #include "ieee754dp.h"
18 maddf_negate_product = 1 << 0,
21 static union ieee754dp _dp_maddf(union ieee754dp z, union ieee754dp x,
22 union ieee754dp y, enum maddf_flags flags)
40 u64 zm; int ze; int zs __maybe_unused; int zc;
44 EXPLODEDP(z, zc, zs, ze, zm)
48 FLUSHDP(z, zc, zs, ze, zm);
53 case IEEE754_CLASS_SNAN:
54 ieee754_setcx(IEEE754_INVALID_OPERATION);
55 return ieee754dp_nanxcpt(z);
56 case IEEE754_CLASS_DNORM:
58 /* QNAN is handled separately below */
61 switch (CLPAIR(xc, yc)) {
62 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_SNAN):
63 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_SNAN):
64 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_SNAN):
65 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_SNAN):
66 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_SNAN):
67 return ieee754dp_nanxcpt(y);
69 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN):
70 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN):
71 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_ZERO):
72 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_NORM):
73 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_DNORM):
74 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF):
75 return ieee754dp_nanxcpt(x);
77 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN):
78 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN):
79 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_QNAN):
80 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_QNAN):
83 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN):
84 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_ZERO):
85 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_NORM):
86 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_DNORM):
87 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_INF):
94 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_ZERO):
95 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_INF):
96 if (zc == IEEE754_CLASS_QNAN)
98 ieee754_setcx(IEEE754_INVALID_OPERATION);
99 return ieee754dp_indef();
101 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_INF):
102 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_INF):
103 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_NORM):
104 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_DNORM):
105 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF):
106 if (zc == IEEE754_CLASS_QNAN)
108 return ieee754dp_inf(xs ^ ys);
110 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_ZERO):
111 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_NORM):
112 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_DNORM):
113 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_ZERO):
114 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_ZERO):
115 if (zc == IEEE754_CLASS_INF)
116 return ieee754dp_inf(zs);
117 /* Multiplication is 0 so just return z */
120 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_DNORM):
123 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_DNORM):
124 if (zc == IEEE754_CLASS_QNAN)
126 else if (zc == IEEE754_CLASS_INF)
127 return ieee754dp_inf(zs);
131 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_NORM):
132 if (zc == IEEE754_CLASS_QNAN)
134 else if (zc == IEEE754_CLASS_INF)
135 return ieee754dp_inf(zs);
139 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_NORM):
140 if (zc == IEEE754_CLASS_QNAN)
142 else if (zc == IEEE754_CLASS_INF)
143 return ieee754dp_inf(zs);
144 /* fall through to real computations */
147 /* Finally get to do some computation */
150 * Do the multiplication bit first
152 * rm = xm * ym, re = xe + ye basically
154 * At this point xm and ym should have been normalized.
156 assert(xm & DP_HIDDEN_BIT);
157 assert(ym & DP_HIDDEN_BIT);
161 if (flags & maddf_negate_product)
164 /* shunt to top of word */
165 xm <<= 64 - (DP_FBITS + 1);
166 ym <<= 64 - (DP_FBITS + 1);
169 * Multiply 32 bits xm, ym to give high 32 bits rm with stickness.
173 #define DPXMULT(x, y) ((u64)(x) * (u64)y)
180 lrm = DPXMULT(lxm, lym);
181 hrm = DPXMULT(hxm, hym);
183 t = DPXMULT(lxm, hym);
185 at = lrm + (t << 32);
189 hrm = hrm + (t >> 32);
191 t = DPXMULT(hxm, lym);
193 at = lrm + (t << 32);
197 hrm = hrm + (t >> 32);
199 rm = hrm | (lrm != 0);
202 * Sticky shift down to normal rounding precision.
205 rm = (rm >> (64 - (DP_FBITS + 1 + 3))) |
206 ((rm << (DP_FBITS + 1 + 3)) != 0);
209 rm = (rm >> (64 - (DP_FBITS + 1 + 3 + 1))) |
210 ((rm << (DP_FBITS + 1 + 3 + 1)) != 0);
212 assert(rm & (DP_HIDDEN_BIT << 3));
214 /* And now the addition */
215 assert(zm & DP_HIDDEN_BIT);
218 * Provide guard,round and stick bit space.
224 * Have to shift y fraction right to align.
229 } else if (re > ze) {
231 * Have to shift x fraction right to align.
238 assert(ze <= DP_EMAX);
242 * Generate 28 bit result of adding two 27 bit numbers
243 * leaving result in xm, xs and xe.
247 if (zm >> (DP_FBITS + 1 + 3)) { /* carry out */
259 return ieee754dp_zero(ieee754_csr.rm == FPU_CSR_RD);
262 * Normalize to rounding precision.
264 while ((zm >> (DP_FBITS + 3)) == 0) {
270 return ieee754dp_format(zs, ze, zm);
273 union ieee754dp ieee754dp_maddf(union ieee754dp z, union ieee754dp x,
276 return _dp_maddf(z, x, y, 0);
279 union ieee754dp ieee754dp_msubf(union ieee754dp z, union ieee754dp x,
282 return _dp_maddf(z, x, y, maddf_negate_product);