2 * cp1emu.c: a MIPS coprocessor 1 (fpu) instruction emulator
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
6 * http://www.algor.co.uk
8 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
9 * Copyright (C) 2000 MIPS Technologies, Inc.
11 * This program is free software; you can distribute it and/or modify it
12 * under the terms of the GNU General Public License (Version 2) as
13 * published by the Free Software Foundation.
15 * This program is distributed in the hope it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
24 * A complete emulator for MIPS coprocessor 1 instructions. This is
25 * required for #float(switch) or #float(trap), where it catches all
26 * COP1 instructions via the "CoProcessor Unusable" exception.
28 * More surprisingly it is also required for #float(ieee), to help out
29 * the hardware fpu at the boundaries of the IEEE-754 representation
30 * (denormalised values, infinities, underflow, etc). It is made
31 * quite nasty because emulation of some non-COP1 instructions is
32 * required, e.g. in branch delay slots.
34 * Note if you know that you won't have an fpu, then you'll get much
35 * better performance by compiling with -msoft-float!
37 #include <linux/sched.h>
38 #include <linux/debugfs.h>
41 #include <asm/bootinfo.h>
42 #include <asm/processor.h>
43 #include <asm/ptrace.h>
44 #include <asm/signal.h>
45 #include <asm/mipsregs.h>
46 #include <asm/fpu_emulator.h>
47 #include <asm/uaccess.h>
48 #include <asm/branch.h>
52 /* Strap kernel emulator for full MIPS IV emulation */
59 /* Function which emulates a floating point instruction. */
61 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
64 #if __mips >= 4 && __mips != 32
65 static int fpux_emu(struct pt_regs *,
66 struct mips_fpu_struct *, mips_instruction);
69 /* Further private data for which no space exists in mips_fpu_struct */
71 struct mips_fpu_emulator_stats fpuemustats;
73 /* Control registers */
75 #define FPCREG_RID 0 /* $0 = revision id */
76 #define FPCREG_CSR 31 /* $31 = csr */
78 /* Convert Mips rounding mode (0..3) to IEEE library modes. */
79 static const unsigned char ieee_rm[4] = {
80 [FPU_CSR_RN] = IEEE754_RN,
81 [FPU_CSR_RZ] = IEEE754_RZ,
82 [FPU_CSR_RU] = IEEE754_RU,
83 [FPU_CSR_RD] = IEEE754_RD,
85 /* Convert IEEE library modes to Mips rounding mode (0..3). */
86 static const unsigned char mips_rm[4] = {
87 [IEEE754_RN] = FPU_CSR_RN,
88 [IEEE754_RZ] = FPU_CSR_RZ,
89 [IEEE754_RD] = FPU_CSR_RD,
90 [IEEE754_RU] = FPU_CSR_RU,
94 /* convert condition code register number to csr bit */
95 static const unsigned int fpucondbit[8] = {
109 * Redundant with logic already in kernel/branch.c,
110 * embedded in compute_return_epc. At some point,
111 * a single subroutine should be used across both
114 static int isBranchInstr(mips_instruction * i)
116 switch (MIPSInst_OPCODE(*i)) {
118 switch (MIPSInst_FUNC(*i)) {
126 switch (MIPSInst_RT(*i)) {
156 if (MIPSInst_RS(*i) == bc_op)
165 * In the Linux kernel, we support selection of FPR format on the
166 * basis of the Status.FR bit. If an FPU is not present, the FR bit
167 * is hardwired to zero, which would imply a 32-bit FPU even for
168 * 64-bit CPUs. For 64-bit kernels with no FPU we use TIF_32BIT_REGS
169 * as a proxy for the FR bit so that a 64-bit FPU is emulated. In any
170 * case, for a 32-bit kernel which uses the O32 MIPS ABI, only the
171 * even FPRs are used (Status.FR = 0).
173 static inline int cop1_64bit(struct pt_regs *xcp)
176 return xcp->cp0_status & ST0_FR;
178 return !test_thread_flag(TIF_32BIT_REGS);
184 #define SIFROMREG(si, x) ((si) = cop1_64bit(xcp) || !(x & 1) ? \
185 (int)ctx->fpr[x] : (int)(ctx->fpr[x & ~1] >> 32))
187 #define SITOREG(si, x) (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = \
188 cop1_64bit(xcp) || !(x & 1) ? \
189 ctx->fpr[x & ~1] >> 32 << 32 | (u32)(si) : \
190 ctx->fpr[x & ~1] << 32 >> 32 | (u64)(si) << 32)
192 #define DIFROMREG(di, x) ((di) = ctx->fpr[x & ~(cop1_64bit(xcp) == 0)])
193 #define DITOREG(di, x) (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = (di))
195 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
196 #define SPTOREG(sp, x) SITOREG((sp).bits, x)
197 #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
198 #define DPTOREG(dp, x) DITOREG((dp).bits, x)
201 * Emulate the single floating point instruction pointed at by EPC.
202 * Two instructions if the instruction is in a branch delay slot.
205 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
208 unsigned long emulpc, contpc;
211 if (get_user(ir, (mips_instruction __user *) xcp->cp0_epc)) {
212 fpuemustats.errors++;
216 /* XXX NEC Vr54xx bug workaround */
217 if ((xcp->cp0_cause & CAUSEF_BD) && !isBranchInstr(&ir))
218 xcp->cp0_cause &= ~CAUSEF_BD;
220 if (xcp->cp0_cause & CAUSEF_BD) {
222 * The instruction to be emulated is in a branch delay slot
223 * which means that we have to emulate the branch instruction
224 * BEFORE we do the cop1 instruction.
226 * This branch could be a COP1 branch, but in that case we
227 * would have had a trap for that instruction, and would not
228 * come through this route.
230 * Linux MIPS branch emulator operates on context, updating the
233 emulpc = xcp->cp0_epc + 4; /* Snapshot emulation target */
235 if (__compute_return_epc(xcp)) {
237 printk("failed to emulate branch at %p\n",
238 (void *) (xcp->cp0_epc));
242 if (get_user(ir, (mips_instruction __user *) emulpc)) {
243 fpuemustats.errors++;
246 /* __compute_return_epc() will have updated cp0_epc */
247 contpc = xcp->cp0_epc;
248 /* In order not to confuse ptrace() et al, tweak context */
249 xcp->cp0_epc = emulpc - 4;
251 emulpc = xcp->cp0_epc;
252 contpc = xcp->cp0_epc + 4;
256 fpuemustats.emulated++;
257 switch (MIPSInst_OPCODE(ir)) {
259 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
264 if (get_user(val, va)) {
265 fpuemustats.errors++;
268 DITOREG(val, MIPSInst_RT(ir));
273 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
277 fpuemustats.stores++;
278 DIFROMREG(val, MIPSInst_RT(ir));
279 if (put_user(val, va)) {
280 fpuemustats.errors++;
287 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
292 if (get_user(val, va)) {
293 fpuemustats.errors++;
296 SITOREG(val, MIPSInst_RT(ir));
301 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
305 fpuemustats.stores++;
306 SIFROMREG(val, MIPSInst_RT(ir));
307 if (put_user(val, va)) {
308 fpuemustats.errors++;
315 switch (MIPSInst_RS(ir)) {
317 #if defined(__mips64)
319 /* copregister fs -> gpr[rt] */
320 if (MIPSInst_RT(ir) != 0) {
321 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
327 /* copregister fs <- rt */
328 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
333 /* copregister rd -> gpr[rt] */
334 if (MIPSInst_RT(ir) != 0) {
335 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
341 /* copregister rd <- rt */
342 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
346 /* cop control register rd -> gpr[rt] */
349 if (MIPSInst_RD(ir) == FPCREG_CSR) {
351 value = (value & ~0x3) | mips_rm[value & 0x3];
353 printk("%p gpr[%d]<-csr=%08x\n",
354 (void *) (xcp->cp0_epc),
355 MIPSInst_RT(ir), value);
358 else if (MIPSInst_RD(ir) == FPCREG_RID)
363 xcp->regs[MIPSInst_RT(ir)] = value;
368 /* copregister rd <- rt */
371 if (MIPSInst_RT(ir) == 0)
374 value = xcp->regs[MIPSInst_RT(ir)];
376 /* we only have one writable control reg
378 if (MIPSInst_RD(ir) == FPCREG_CSR) {
380 printk("%p gpr[%d]->csr=%08x\n",
381 (void *) (xcp->cp0_epc),
382 MIPSInst_RT(ir), value);
384 value &= (FPU_CSR_FLUSH | FPU_CSR_ALL_E | FPU_CSR_ALL_S | 0x03);
385 ctx->fcr31 &= ~(FPU_CSR_FLUSH | FPU_CSR_ALL_E | FPU_CSR_ALL_S | 0x03);
386 /* convert to ieee library modes */
387 ctx->fcr31 |= (value & ~0x3) | ieee_rm[value & 0x3];
389 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
398 if (xcp->cp0_cause & CAUSEF_BD)
402 cond = ctx->fcr31 & fpucondbit[MIPSInst_RT(ir) >> 2];
404 cond = ctx->fcr31 & FPU_CSR_COND;
406 switch (MIPSInst_RT(ir) & 3) {
417 /* thats an illegal instruction */
421 xcp->cp0_cause |= CAUSEF_BD;
423 /* branch taken: emulate dslot
427 contpc = (xcp->cp0_epc +
428 (MIPSInst_SIMM(ir) << 2));
431 (mips_instruction __user *) xcp->cp0_epc)) {
432 fpuemustats.errors++;
436 switch (MIPSInst_OPCODE(ir)) {
439 #if (__mips >= 2 || defined(__mips64))
444 #if __mips >= 4 && __mips != 32
447 /* its one of ours */
451 if (MIPSInst_FUNC(ir) == movc_op)
458 * Single step the non-cp1
459 * instruction in the dslot
461 return mips_dsemul(xcp, ir, contpc);
464 /* branch not taken */
467 * branch likely nullifies
473 * else continue & execute
474 * dslot as normal insn
482 if (!(MIPSInst_RS(ir) & 0x10))
487 /* a real fpu computation instruction */
488 if ((sig = fpu_emu(xcp, ctx, ir)))
494 #if __mips >= 4 && __mips != 32
498 if ((sig = fpux_emu(xcp, ctx, ir)))
506 if (MIPSInst_FUNC(ir) != movc_op)
508 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
509 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
510 xcp->regs[MIPSInst_RD(ir)] =
511 xcp->regs[MIPSInst_RS(ir)];
520 xcp->cp0_epc = contpc;
521 xcp->cp0_cause &= ~CAUSEF_BD;
527 * Conversion table from MIPS compare ops 48-63
528 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
530 static const unsigned char cmptab[8] = {
531 0, /* cmp_0 (sig) cmp_sf */
532 IEEE754_CUN, /* cmp_un (sig) cmp_ngle */
533 IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */
534 IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */
535 IEEE754_CLT, /* cmp_olt (sig) cmp_lt */
536 IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */
537 IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */
538 IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */
542 #if __mips >= 4 && __mips != 32
545 * Additional MIPS4 instructions
548 #define DEF3OP(name, p, f1, f2, f3) \
549 static ieee754##p fpemu_##p##_##name(ieee754##p r, ieee754##p s, \
552 struct _ieee754_csr ieee754_csr_save; \
554 ieee754_csr_save = ieee754_csr; \
556 ieee754_csr_save.cx |= ieee754_csr.cx; \
557 ieee754_csr_save.sx |= ieee754_csr.sx; \
559 ieee754_csr.cx |= ieee754_csr_save.cx; \
560 ieee754_csr.sx |= ieee754_csr_save.sx; \
564 static ieee754dp fpemu_dp_recip(ieee754dp d)
566 return ieee754dp_div(ieee754dp_one(0), d);
569 static ieee754dp fpemu_dp_rsqrt(ieee754dp d)
571 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
574 static ieee754sp fpemu_sp_recip(ieee754sp s)
576 return ieee754sp_div(ieee754sp_one(0), s);
579 static ieee754sp fpemu_sp_rsqrt(ieee754sp s)
581 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
584 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
585 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
586 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
587 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
588 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
589 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
590 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
591 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
593 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
596 unsigned rcsr = 0; /* resulting csr */
598 fpuemustats.cp1xops++;
600 switch (MIPSInst_FMA_FFMT(ir)) {
603 ieee754sp(*handler) (ieee754sp, ieee754sp, ieee754sp);
604 ieee754sp fd, fr, fs, ft;
608 switch (MIPSInst_FUNC(ir)) {
610 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
611 xcp->regs[MIPSInst_FT(ir)]);
614 if (get_user(val, va)) {
615 fpuemustats.errors++;
618 SITOREG(val, MIPSInst_FD(ir));
622 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
623 xcp->regs[MIPSInst_FT(ir)]);
625 fpuemustats.stores++;
627 SIFROMREG(val, MIPSInst_FS(ir));
628 if (put_user(val, va)) {
629 fpuemustats.errors++;
635 handler = fpemu_sp_madd;
638 handler = fpemu_sp_msub;
641 handler = fpemu_sp_nmadd;
644 handler = fpemu_sp_nmsub;
648 SPFROMREG(fr, MIPSInst_FR(ir));
649 SPFROMREG(fs, MIPSInst_FS(ir));
650 SPFROMREG(ft, MIPSInst_FT(ir));
651 fd = (*handler) (fr, fs, ft);
652 SPTOREG(fd, MIPSInst_FD(ir));
655 if (ieee754_cxtest(IEEE754_INEXACT))
656 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
657 if (ieee754_cxtest(IEEE754_UNDERFLOW))
658 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
659 if (ieee754_cxtest(IEEE754_OVERFLOW))
660 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
661 if (ieee754_cxtest(IEEE754_INVALID_OPERATION))
662 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
664 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
665 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
666 /*printk ("SIGFPE: fpu csr = %08x\n",
680 ieee754dp(*handler) (ieee754dp, ieee754dp, ieee754dp);
681 ieee754dp fd, fr, fs, ft;
685 switch (MIPSInst_FUNC(ir)) {
687 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
688 xcp->regs[MIPSInst_FT(ir)]);
691 if (get_user(val, va)) {
692 fpuemustats.errors++;
695 DITOREG(val, MIPSInst_FD(ir));
699 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
700 xcp->regs[MIPSInst_FT(ir)]);
702 fpuemustats.stores++;
703 DIFROMREG(val, MIPSInst_FS(ir));
704 if (put_user(val, va)) {
705 fpuemustats.errors++;
711 handler = fpemu_dp_madd;
714 handler = fpemu_dp_msub;
717 handler = fpemu_dp_nmadd;
720 handler = fpemu_dp_nmsub;
724 DPFROMREG(fr, MIPSInst_FR(ir));
725 DPFROMREG(fs, MIPSInst_FS(ir));
726 DPFROMREG(ft, MIPSInst_FT(ir));
727 fd = (*handler) (fr, fs, ft);
728 DPTOREG(fd, MIPSInst_FD(ir));
738 if (MIPSInst_FUNC(ir) != pfetch_op) {
741 /* ignore prefx operation */
755 * Emulate a single COP1 arithmetic instruction.
757 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
760 int rfmt; /* resulting format */
761 unsigned rcsr = 0; /* resulting csr */
770 } rv; /* resulting value */
772 fpuemustats.cp1ops++;
773 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
776 ieee754sp(*b) (ieee754sp, ieee754sp);
777 ieee754sp(*u) (ieee754sp);
780 switch (MIPSInst_FUNC(ir)) {
783 handler.b = ieee754sp_add;
786 handler.b = ieee754sp_sub;
789 handler.b = ieee754sp_mul;
792 handler.b = ieee754sp_div;
796 #if __mips >= 2 || defined(__mips64)
798 handler.u = ieee754sp_sqrt;
801 #if __mips >= 4 && __mips != 32
803 handler.u = fpemu_sp_rsqrt;
806 handler.u = fpemu_sp_recip;
811 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
812 if (((ctx->fcr31 & cond) != 0) !=
813 ((MIPSInst_FT(ir) & 1) != 0))
815 SPFROMREG(rv.s, MIPSInst_FS(ir));
818 if (xcp->regs[MIPSInst_FT(ir)] != 0)
820 SPFROMREG(rv.s, MIPSInst_FS(ir));
823 if (xcp->regs[MIPSInst_FT(ir)] == 0)
825 SPFROMREG(rv.s, MIPSInst_FS(ir));
829 handler.u = ieee754sp_abs;
832 handler.u = ieee754sp_neg;
836 SPFROMREG(rv.s, MIPSInst_FS(ir));
839 /* binary op on handler */
844 SPFROMREG(fs, MIPSInst_FS(ir));
845 SPFROMREG(ft, MIPSInst_FT(ir));
847 rv.s = (*handler.b) (fs, ft);
854 SPFROMREG(fs, MIPSInst_FS(ir));
855 rv.s = (*handler.u) (fs);
859 if (ieee754_cxtest(IEEE754_INEXACT))
860 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
861 if (ieee754_cxtest(IEEE754_UNDERFLOW))
862 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
863 if (ieee754_cxtest(IEEE754_OVERFLOW))
864 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
865 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE))
866 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
867 if (ieee754_cxtest(IEEE754_INVALID_OPERATION))
868 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
873 return SIGILL; /* not defined */
877 SPFROMREG(fs, MIPSInst_FS(ir));
878 rv.d = ieee754dp_fsp(fs);
885 SPFROMREG(fs, MIPSInst_FS(ir));
886 rv.w = ieee754sp_tint(fs);
891 #if __mips >= 2 || defined(__mips64)
896 unsigned int oldrm = ieee754_csr.rm;
899 SPFROMREG(fs, MIPSInst_FS(ir));
900 ieee754_csr.rm = ieee_rm[MIPSInst_FUNC(ir) & 0x3];
901 rv.w = ieee754sp_tint(fs);
902 ieee754_csr.rm = oldrm;
906 #endif /* __mips >= 2 */
908 #if defined(__mips64)
912 SPFROMREG(fs, MIPSInst_FS(ir));
913 rv.l = ieee754sp_tlong(fs);
922 unsigned int oldrm = ieee754_csr.rm;
925 SPFROMREG(fs, MIPSInst_FS(ir));
926 ieee754_csr.rm = ieee_rm[MIPSInst_FUNC(ir) & 0x3];
927 rv.l = ieee754sp_tlong(fs);
928 ieee754_csr.rm = oldrm;
932 #endif /* defined(__mips64) */
935 if (MIPSInst_FUNC(ir) >= fcmp_op) {
936 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
939 SPFROMREG(fs, MIPSInst_FS(ir));
940 SPFROMREG(ft, MIPSInst_FT(ir));
941 rv.w = ieee754sp_cmp(fs, ft,
942 cmptab[cmpop & 0x7], cmpop & 0x8);
944 if ((cmpop & 0x8) && ieee754_cxtest
945 (IEEE754_INVALID_OPERATION))
946 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
961 ieee754dp(*b) (ieee754dp, ieee754dp);
962 ieee754dp(*u) (ieee754dp);
965 switch (MIPSInst_FUNC(ir)) {
968 handler.b = ieee754dp_add;
971 handler.b = ieee754dp_sub;
974 handler.b = ieee754dp_mul;
977 handler.b = ieee754dp_div;
981 #if __mips >= 2 || defined(__mips64)
983 handler.u = ieee754dp_sqrt;
986 #if __mips >= 4 && __mips != 32
988 handler.u = fpemu_dp_rsqrt;
991 handler.u = fpemu_dp_recip;
996 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
997 if (((ctx->fcr31 & cond) != 0) !=
998 ((MIPSInst_FT(ir) & 1) != 0))
1000 DPFROMREG(rv.d, MIPSInst_FS(ir));
1003 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1005 DPFROMREG(rv.d, MIPSInst_FS(ir));
1008 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1010 DPFROMREG(rv.d, MIPSInst_FS(ir));
1014 handler.u = ieee754dp_abs;
1018 handler.u = ieee754dp_neg;
1023 DPFROMREG(rv.d, MIPSInst_FS(ir));
1026 /* binary op on handler */
1030 DPFROMREG(fs, MIPSInst_FS(ir));
1031 DPFROMREG(ft, MIPSInst_FT(ir));
1033 rv.d = (*handler.b) (fs, ft);
1039 DPFROMREG(fs, MIPSInst_FS(ir));
1040 rv.d = (*handler.u) (fs);
1044 /* unary conv ops */
1048 DPFROMREG(fs, MIPSInst_FS(ir));
1049 rv.s = ieee754sp_fdp(fs);
1054 return SIGILL; /* not defined */
1059 DPFROMREG(fs, MIPSInst_FS(ir));
1060 rv.w = ieee754dp_tint(fs); /* wrong */
1065 #if __mips >= 2 || defined(__mips64)
1070 unsigned int oldrm = ieee754_csr.rm;
1073 DPFROMREG(fs, MIPSInst_FS(ir));
1074 ieee754_csr.rm = ieee_rm[MIPSInst_FUNC(ir) & 0x3];
1075 rv.w = ieee754dp_tint(fs);
1076 ieee754_csr.rm = oldrm;
1082 #if defined(__mips64)
1086 DPFROMREG(fs, MIPSInst_FS(ir));
1087 rv.l = ieee754dp_tlong(fs);
1096 unsigned int oldrm = ieee754_csr.rm;
1099 DPFROMREG(fs, MIPSInst_FS(ir));
1100 ieee754_csr.rm = ieee_rm[MIPSInst_FUNC(ir) & 0x3];
1101 rv.l = ieee754dp_tlong(fs);
1102 ieee754_csr.rm = oldrm;
1106 #endif /* __mips >= 3 */
1109 if (MIPSInst_FUNC(ir) >= fcmp_op) {
1110 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1113 DPFROMREG(fs, MIPSInst_FS(ir));
1114 DPFROMREG(ft, MIPSInst_FT(ir));
1115 rv.w = ieee754dp_cmp(fs, ft,
1116 cmptab[cmpop & 0x7], cmpop & 0x8);
1121 (IEEE754_INVALID_OPERATION))
1122 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1138 switch (MIPSInst_FUNC(ir)) {
1140 /* convert word to single precision real */
1141 SPFROMREG(fs, MIPSInst_FS(ir));
1142 rv.s = ieee754sp_fint(fs.bits);
1146 /* convert word to double precision real */
1147 SPFROMREG(fs, MIPSInst_FS(ir));
1148 rv.d = ieee754dp_fint(fs.bits);
1157 #if defined(__mips64)
1159 switch (MIPSInst_FUNC(ir)) {
1161 /* convert long to single precision real */
1162 rv.s = ieee754sp_flong(ctx->fpr[MIPSInst_FS(ir)]);
1166 /* convert long to double precision real */
1167 rv.d = ieee754dp_flong(ctx->fpr[MIPSInst_FS(ir)]);
1182 * Update the fpu CSR register for this operation.
1183 * If an exception is required, generate a tidy SIGFPE exception,
1184 * without updating the result register.
1185 * Note: cause exception bits do not accumulate, they are rewritten
1186 * for each op; only the flag/sticky bits accumulate.
1188 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1189 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1190 /*printk ("SIGFPE: fpu csr = %08x\n",ctx->fcr31); */
1195 * Now we can safely write the result back to the register file.
1200 cond = fpucondbit[MIPSInst_FD(ir) >> 2];
1202 cond = FPU_CSR_COND;
1207 ctx->fcr31 &= ~cond;
1211 DPTOREG(rv.d, MIPSInst_FD(ir));
1214 SPTOREG(rv.s, MIPSInst_FD(ir));
1217 SITOREG(rv.w, MIPSInst_FD(ir));
1219 #if defined(__mips64)
1221 DITOREG(rv.l, MIPSInst_FD(ir));
1231 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1234 unsigned long oldepc, prevepc;
1235 mips_instruction insn;
1238 oldepc = xcp->cp0_epc;
1240 prevepc = xcp->cp0_epc;
1242 if (get_user(insn, (mips_instruction __user *) xcp->cp0_epc)) {
1243 fpuemustats.errors++;
1247 xcp->cp0_epc += 4; /* skip nops */
1250 * The 'ieee754_csr' is an alias of
1251 * ctx->fcr31. No need to copy ctx->fcr31 to
1252 * ieee754_csr. But ieee754_csr.rm is ieee
1253 * library modes. (not mips rounding mode)
1255 /* convert to ieee library modes */
1256 ieee754_csr.rm = ieee_rm[ieee754_csr.rm];
1257 sig = cop1Emulate(xcp, ctx);
1258 /* revert to mips rounding mode */
1259 ieee754_csr.rm = mips_rm[ieee754_csr.rm];
1268 } while (xcp->cp0_epc > prevepc);
1270 /* SIGILL indicates a non-fpu instruction */
1271 if (sig == SIGILL && xcp->cp0_epc != oldepc)
1272 /* but if epc has advanced, then ignore it */
1278 #ifdef CONFIG_DEBUG_FS
1279 extern struct dentry *mips_debugfs_dir;
1280 static int __init debugfs_fpuemu(void)
1282 struct dentry *d, *dir;
1287 } vars[] __initdata = {
1288 { "emulated", &fpuemustats.emulated },
1289 { "loads", &fpuemustats.loads },
1290 { "stores", &fpuemustats.stores },
1291 { "cp1ops", &fpuemustats.cp1ops },
1292 { "cp1xops", &fpuemustats.cp1xops },
1293 { "errors", &fpuemustats.errors },
1296 if (!mips_debugfs_dir)
1298 dir = debugfs_create_dir("fpuemustats", mips_debugfs_dir);
1301 for (i = 0; i < ARRAY_SIZE(vars); i++) {
1302 d = debugfs_create_u32(vars[i].name, S_IRUGO, dir, vars[i].v);
1308 __initcall(debugfs_fpuemu);