2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
23 * A complete emulator for MIPS coprocessor 1 instructions. This is
24 * required for #float(switch) or #float(trap), where it catches all
25 * COP1 instructions via the "CoProcessor Unusable" exception.
27 * More surprisingly it is also required for #float(ieee), to help out
28 * the hardware FPU at the boundaries of the IEEE-754 representation
29 * (denormalised values, infinities, underflow, etc). It is made
30 * quite nasty because emulation of some non-COP1 instructions is
31 * required, e.g. in branch delay slots.
33 * Note if you know that you won't have an FPU, then you'll get much
34 * better performance by compiling with -msoft-float!
36 #include <linux/sched.h>
37 #include <linux/debugfs.h>
38 #include <linux/kconfig.h>
39 #include <linux/percpu-defs.h>
40 #include <linux/perf_event.h>
42 #include <asm/branch.h>
44 #include <asm/ptrace.h>
45 #include <asm/signal.h>
46 #include <asm/uaccess.h>
48 #include <asm/processor.h>
49 #include <asm/fpu_emulator.h>
54 /* Function which emulates a floating point instruction. */
56 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
59 static int fpux_emu(struct pt_regs *,
60 struct mips_fpu_struct *, mips_instruction, void *__user *);
62 /* Control registers */
64 #define FPCREG_RID 0 /* $0 = revision id */
65 #define FPCREG_CSR 31 /* $31 = csr */
67 /* Determine rounding mode from the RM bits of the FCSR */
68 #define modeindex(v) ((v) & FPU_CSR_RM)
70 /* convert condition code register number to csr bit */
71 static const unsigned int fpucondbit[8] = {
82 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
83 static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0};
84 static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0};
85 static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0};
86 static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0};
89 * This functions translates a 32-bit microMIPS instruction
90 * into a 32-bit MIPS32 instruction. Returns 0 on success
91 * and SIGILL otherwise.
93 static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
95 union mips_instruction insn = *insn_ptr;
96 union mips_instruction mips32_insn = insn;
99 switch (insn.mm_i_format.opcode) {
101 mips32_insn.mm_i_format.opcode = ldc1_op;
102 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
103 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
106 mips32_insn.mm_i_format.opcode = lwc1_op;
107 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
108 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
111 mips32_insn.mm_i_format.opcode = sdc1_op;
112 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
113 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
116 mips32_insn.mm_i_format.opcode = swc1_op;
117 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
118 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
121 /* NOTE: offset is << by 1 if in microMIPS mode. */
122 if ((insn.mm_i_format.rt == mm_bc1f_op) ||
123 (insn.mm_i_format.rt == mm_bc1t_op)) {
124 mips32_insn.fb_format.opcode = cop1_op;
125 mips32_insn.fb_format.bc = bc_op;
126 mips32_insn.fb_format.flag =
127 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0;
132 switch (insn.mm_fp0_format.func) {
141 op = insn.mm_fp0_format.func;
142 if (op == mm_32f_01_op)
144 else if (op == mm_32f_11_op)
146 else if (op == mm_32f_02_op)
148 else if (op == mm_32f_12_op)
150 else if (op == mm_32f_41_op)
152 else if (op == mm_32f_51_op)
154 else if (op == mm_32f_42_op)
158 mips32_insn.fp6_format.opcode = cop1x_op;
159 mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr;
160 mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft;
161 mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs;
162 mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd;
163 mips32_insn.fp6_format.func = func;
166 func = -1; /* Invalid */
167 op = insn.mm_fp5_format.op & 0x7;
168 if (op == mm_ldxc1_op)
170 else if (op == mm_sdxc1_op)
172 else if (op == mm_lwxc1_op)
174 else if (op == mm_swxc1_op)
178 mips32_insn.r_format.opcode = cop1x_op;
179 mips32_insn.r_format.rs =
180 insn.mm_fp5_format.base;
181 mips32_insn.r_format.rt =
182 insn.mm_fp5_format.index;
183 mips32_insn.r_format.rd = 0;
184 mips32_insn.r_format.re = insn.mm_fp5_format.fd;
185 mips32_insn.r_format.func = func;
190 op = -1; /* Invalid */
191 if (insn.mm_fp2_format.op == mm_fmovt_op)
193 else if (insn.mm_fp2_format.op == mm_fmovf_op)
196 mips32_insn.fp0_format.opcode = cop1_op;
197 mips32_insn.fp0_format.fmt =
198 sdps_format[insn.mm_fp2_format.fmt];
199 mips32_insn.fp0_format.ft =
200 (insn.mm_fp2_format.cc<<2) + op;
201 mips32_insn.fp0_format.fs =
202 insn.mm_fp2_format.fs;
203 mips32_insn.fp0_format.fd =
204 insn.mm_fp2_format.fd;
205 mips32_insn.fp0_format.func = fmovc_op;
210 func = -1; /* Invalid */
211 if (insn.mm_fp0_format.op == mm_fadd_op)
213 else if (insn.mm_fp0_format.op == mm_fsub_op)
215 else if (insn.mm_fp0_format.op == mm_fmul_op)
217 else if (insn.mm_fp0_format.op == mm_fdiv_op)
220 mips32_insn.fp0_format.opcode = cop1_op;
221 mips32_insn.fp0_format.fmt =
222 sdps_format[insn.mm_fp0_format.fmt];
223 mips32_insn.fp0_format.ft =
224 insn.mm_fp0_format.ft;
225 mips32_insn.fp0_format.fs =
226 insn.mm_fp0_format.fs;
227 mips32_insn.fp0_format.fd =
228 insn.mm_fp0_format.fd;
229 mips32_insn.fp0_format.func = func;
234 func = -1; /* Invalid */
235 if (insn.mm_fp0_format.op == mm_fmovn_op)
237 else if (insn.mm_fp0_format.op == mm_fmovz_op)
240 mips32_insn.fp0_format.opcode = cop1_op;
241 mips32_insn.fp0_format.fmt =
242 sdps_format[insn.mm_fp0_format.fmt];
243 mips32_insn.fp0_format.ft =
244 insn.mm_fp0_format.ft;
245 mips32_insn.fp0_format.fs =
246 insn.mm_fp0_format.fs;
247 mips32_insn.fp0_format.fd =
248 insn.mm_fp0_format.fd;
249 mips32_insn.fp0_format.func = func;
253 case mm_32f_73_op: /* POOL32FXF */
254 switch (insn.mm_fp1_format.op) {
259 if ((insn.mm_fp1_format.op & 0x7f) ==
264 mips32_insn.r_format.opcode = spec_op;
265 mips32_insn.r_format.rs = insn.mm_fp4_format.fs;
266 mips32_insn.r_format.rt =
267 (insn.mm_fp4_format.cc << 2) + op;
268 mips32_insn.r_format.rd = insn.mm_fp4_format.rt;
269 mips32_insn.r_format.re = 0;
270 mips32_insn.r_format.func = movc_op;
276 if ((insn.mm_fp1_format.op & 0x7f) ==
279 fmt = swl_format[insn.mm_fp3_format.fmt];
282 fmt = dwl_format[insn.mm_fp3_format.fmt];
284 mips32_insn.fp0_format.opcode = cop1_op;
285 mips32_insn.fp0_format.fmt = fmt;
286 mips32_insn.fp0_format.ft = 0;
287 mips32_insn.fp0_format.fs =
288 insn.mm_fp3_format.fs;
289 mips32_insn.fp0_format.fd =
290 insn.mm_fp3_format.rt;
291 mips32_insn.fp0_format.func = func;
299 if ((insn.mm_fp1_format.op & 0x7f) ==
302 else if ((insn.mm_fp1_format.op & 0x7f) ==
307 mips32_insn.fp0_format.opcode = cop1_op;
308 mips32_insn.fp0_format.fmt =
309 sdps_format[insn.mm_fp3_format.fmt];
310 mips32_insn.fp0_format.ft = 0;
311 mips32_insn.fp0_format.fs =
312 insn.mm_fp3_format.fs;
313 mips32_insn.fp0_format.fd =
314 insn.mm_fp3_format.rt;
315 mips32_insn.fp0_format.func = func;
327 if (insn.mm_fp1_format.op == mm_ffloorl_op)
329 else if (insn.mm_fp1_format.op == mm_ffloorw_op)
331 else if (insn.mm_fp1_format.op == mm_fceill_op)
333 else if (insn.mm_fp1_format.op == mm_fceilw_op)
335 else if (insn.mm_fp1_format.op == mm_ftruncl_op)
337 else if (insn.mm_fp1_format.op == mm_ftruncw_op)
339 else if (insn.mm_fp1_format.op == mm_froundl_op)
341 else if (insn.mm_fp1_format.op == mm_froundw_op)
343 else if (insn.mm_fp1_format.op == mm_fcvtl_op)
347 mips32_insn.fp0_format.opcode = cop1_op;
348 mips32_insn.fp0_format.fmt =
349 sd_format[insn.mm_fp1_format.fmt];
350 mips32_insn.fp0_format.ft = 0;
351 mips32_insn.fp0_format.fs =
352 insn.mm_fp1_format.fs;
353 mips32_insn.fp0_format.fd =
354 insn.mm_fp1_format.rt;
355 mips32_insn.fp0_format.func = func;
360 if (insn.mm_fp1_format.op == mm_frsqrt_op)
362 else if (insn.mm_fp1_format.op == mm_fsqrt_op)
366 mips32_insn.fp0_format.opcode = cop1_op;
367 mips32_insn.fp0_format.fmt =
368 sdps_format[insn.mm_fp1_format.fmt];
369 mips32_insn.fp0_format.ft = 0;
370 mips32_insn.fp0_format.fs =
371 insn.mm_fp1_format.fs;
372 mips32_insn.fp0_format.fd =
373 insn.mm_fp1_format.rt;
374 mips32_insn.fp0_format.func = func;
382 if (insn.mm_fp1_format.op == mm_mfc1_op)
384 else if (insn.mm_fp1_format.op == mm_mtc1_op)
386 else if (insn.mm_fp1_format.op == mm_cfc1_op)
388 else if (insn.mm_fp1_format.op == mm_ctc1_op)
390 else if (insn.mm_fp1_format.op == mm_mfhc1_op)
394 mips32_insn.fp1_format.opcode = cop1_op;
395 mips32_insn.fp1_format.op = op;
396 mips32_insn.fp1_format.rt =
397 insn.mm_fp1_format.rt;
398 mips32_insn.fp1_format.fs =
399 insn.mm_fp1_format.fs;
400 mips32_insn.fp1_format.fd = 0;
401 mips32_insn.fp1_format.func = 0;
407 case mm_32f_74_op: /* c.cond.fmt */
408 mips32_insn.fp0_format.opcode = cop1_op;
409 mips32_insn.fp0_format.fmt =
410 sdps_format[insn.mm_fp4_format.fmt];
411 mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt;
412 mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs;
413 mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2;
414 mips32_insn.fp0_format.func =
415 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
425 *insn_ptr = mips32_insn;
430 * Redundant with logic already in kernel/branch.c,
431 * embedded in compute_return_epc. At some point,
432 * a single subroutine should be used across both
435 static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
436 unsigned long *contpc)
438 union mips_instruction insn = (union mips_instruction)dec_insn.insn;
440 unsigned int bit = 0;
442 switch (insn.i_format.opcode) {
444 switch (insn.r_format.func) {
446 regs->regs[insn.r_format.rd] =
447 regs->cp0_epc + dec_insn.pc_inc +
448 dec_insn.next_pc_inc;
451 /* For R6, JR already emulated in jalr_op */
452 if (NO_R6EMU && insn.r_format.opcode == jr_op)
454 *contpc = regs->regs[insn.r_format.rs];
459 switch (insn.i_format.rt) {
462 if (NO_R6EMU && (insn.i_format.rs ||
463 insn.i_format.rt == bltzall_op))
466 regs->regs[31] = regs->cp0_epc +
468 dec_insn.next_pc_inc;
474 if ((long)regs->regs[insn.i_format.rs] < 0)
475 *contpc = regs->cp0_epc +
477 (insn.i_format.simmediate << 2);
479 *contpc = regs->cp0_epc +
481 dec_insn.next_pc_inc;
485 if (NO_R6EMU && (insn.i_format.rs ||
486 insn.i_format.rt == bgezall_op))
489 regs->regs[31] = regs->cp0_epc +
491 dec_insn.next_pc_inc;
497 if ((long)regs->regs[insn.i_format.rs] >= 0)
498 *contpc = regs->cp0_epc +
500 (insn.i_format.simmediate << 2);
502 *contpc = regs->cp0_epc +
504 dec_insn.next_pc_inc;
511 regs->regs[31] = regs->cp0_epc +
513 dec_insn.next_pc_inc;
516 *contpc = regs->cp0_epc + dec_insn.pc_inc;
519 *contpc |= (insn.j_format.target << 2);
520 /* Set microMIPS mode bit: XOR for jalx. */
527 if (regs->regs[insn.i_format.rs] ==
528 regs->regs[insn.i_format.rt])
529 *contpc = regs->cp0_epc +
531 (insn.i_format.simmediate << 2);
533 *contpc = regs->cp0_epc +
535 dec_insn.next_pc_inc;
541 if (regs->regs[insn.i_format.rs] !=
542 regs->regs[insn.i_format.rt])
543 *contpc = regs->cp0_epc +
545 (insn.i_format.simmediate << 2);
547 *contpc = regs->cp0_epc +
549 dec_insn.next_pc_inc;
557 * Compact branches for R6 for the
558 * blez and blezl opcodes.
559 * BLEZ | rs = 0 | rt != 0 == BLEZALC
560 * BLEZ | rs = rt != 0 == BGEZALC
561 * BLEZ | rs != 0 | rt != 0 == BGEUC
562 * BLEZL | rs = 0 | rt != 0 == BLEZC
563 * BLEZL | rs = rt != 0 == BGEZC
564 * BLEZL | rs != 0 | rt != 0 == BGEC
566 * For real BLEZ{,L}, rt is always 0.
568 if (cpu_has_mips_r6 && insn.i_format.rt) {
569 if ((insn.i_format.opcode == blez_op) &&
570 ((!insn.i_format.rs && insn.i_format.rt) ||
571 (insn.i_format.rs == insn.i_format.rt)))
572 regs->regs[31] = regs->cp0_epc +
574 *contpc = regs->cp0_epc + dec_insn.pc_inc +
575 dec_insn.next_pc_inc;
579 if ((long)regs->regs[insn.i_format.rs] <= 0)
580 *contpc = regs->cp0_epc +
582 (insn.i_format.simmediate << 2);
584 *contpc = regs->cp0_epc +
586 dec_insn.next_pc_inc;
593 * Compact branches for R6 for the
594 * bgtz and bgtzl opcodes.
595 * BGTZ | rs = 0 | rt != 0 == BGTZALC
596 * BGTZ | rs = rt != 0 == BLTZALC
597 * BGTZ | rs != 0 | rt != 0 == BLTUC
598 * BGTZL | rs = 0 | rt != 0 == BGTZC
599 * BGTZL | rs = rt != 0 == BLTZC
600 * BGTZL | rs != 0 | rt != 0 == BLTC
602 * *ZALC varint for BGTZ &&& rt != 0
603 * For real GTZ{,L}, rt is always 0.
605 if (cpu_has_mips_r6 && insn.i_format.rt) {
606 if ((insn.i_format.opcode == blez_op) &&
607 ((!insn.i_format.rs && insn.i_format.rt) ||
608 (insn.i_format.rs == insn.i_format.rt)))
609 regs->regs[31] = regs->cp0_epc +
611 *contpc = regs->cp0_epc + dec_insn.pc_inc +
612 dec_insn.next_pc_inc;
617 if ((long)regs->regs[insn.i_format.rs] > 0)
618 *contpc = regs->cp0_epc +
620 (insn.i_format.simmediate << 2);
622 *contpc = regs->cp0_epc +
624 dec_insn.next_pc_inc;
627 if (!cpu_has_mips_r6)
629 if (insn.i_format.rt && !insn.i_format.rs)
630 regs->regs[31] = regs->cp0_epc + 4;
631 *contpc = regs->cp0_epc + dec_insn.pc_inc +
632 dec_insn.next_pc_inc;
635 #ifdef CONFIG_CPU_CAVIUM_OCTEON
636 case lwc2_op: /* This is bbit0 on Octeon */
637 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
638 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
640 *contpc = regs->cp0_epc + 8;
642 case ldc2_op: /* This is bbit032 on Octeon */
643 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)
644 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
646 *contpc = regs->cp0_epc + 8;
648 case swc2_op: /* This is bbit1 on Octeon */
649 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
650 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
652 *contpc = regs->cp0_epc + 8;
654 case sdc2_op: /* This is bbit132 on Octeon */
655 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))
656 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
658 *contpc = regs->cp0_epc + 8;
663 * Only valid for MIPS R6 but we can still end up
664 * here from a broken userland so just tell emulator
665 * this is not a branch and let it break later on.
667 if (!cpu_has_mips_r6)
669 *contpc = regs->cp0_epc + dec_insn.pc_inc +
670 dec_insn.next_pc_inc;
676 /* Need to check for R6 bc1nez and bc1eqz branches */
677 if (cpu_has_mips_r6 &&
678 ((insn.i_format.rs == bc1eqz_op) ||
679 (insn.i_format.rs == bc1nez_op))) {
681 switch (insn.i_format.rs) {
683 if (get_fpr32(¤t->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1)
687 if (!(get_fpr32(¤t->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1))
692 *contpc = regs->cp0_epc +
694 (insn.i_format.simmediate << 2);
696 *contpc = regs->cp0_epc +
698 dec_insn.next_pc_inc;
702 /* R2/R6 compatible cop1 instruction. Fall through */
705 if (insn.i_format.rs == bc_op) {
708 fcr31 = read_32bit_cp1_register(CP1_STATUS);
710 fcr31 = current->thread.fpu.fcr31;
713 bit = (insn.i_format.rt >> 2);
716 switch (insn.i_format.rt & 3) {
719 if (~fcr31 & (1 << bit))
720 *contpc = regs->cp0_epc +
722 (insn.i_format.simmediate << 2);
724 *contpc = regs->cp0_epc +
726 dec_insn.next_pc_inc;
730 if (fcr31 & (1 << bit))
731 *contpc = regs->cp0_epc +
733 (insn.i_format.simmediate << 2);
735 *contpc = regs->cp0_epc +
737 dec_insn.next_pc_inc;
747 * In the Linux kernel, we support selection of FPR format on the
748 * basis of the Status.FR bit. If an FPU is not present, the FR bit
749 * is hardwired to zero, which would imply a 32-bit FPU even for
750 * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
751 * FPU emu is slow and bulky and optimizing this function offers fairly
752 * sizeable benefits so we try to be clever and make this function return
753 * a constant whenever possible, that is on 64-bit kernels without O32
754 * compatibility enabled and on 32-bit without 64-bit FPU support.
756 static inline int cop1_64bit(struct pt_regs *xcp)
758 if (config_enabled(CONFIG_64BIT) && !config_enabled(CONFIG_MIPS32_O32))
760 else if (config_enabled(CONFIG_32BIT) &&
761 !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT))
764 return !test_thread_flag(TIF_32BIT_FPREGS);
767 static inline bool hybrid_fprs(void)
769 return test_thread_flag(TIF_HYBRID_FPREGS);
772 #define SIFROMREG(si, x) \
774 if (cop1_64bit(xcp) && !hybrid_fprs()) \
775 (si) = (int)get_fpr32(&ctx->fpr[x], 0); \
777 (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \
780 #define SITOREG(si, x) \
782 if (cop1_64bit(xcp) && !hybrid_fprs()) { \
784 set_fpr32(&ctx->fpr[x], 0, si); \
785 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
786 set_fpr32(&ctx->fpr[x], i, 0); \
788 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \
792 #define SIFROMHREG(si, x) ((si) = (int)get_fpr32(&ctx->fpr[x], 1))
794 #define SITOHREG(si, x) \
797 set_fpr32(&ctx->fpr[x], 1, si); \
798 for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
799 set_fpr32(&ctx->fpr[x], i, 0); \
802 #define DIFROMREG(di, x) \
803 ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0))
805 #define DITOREG(di, x) \
808 fpr = (x) & ~(cop1_64bit(xcp) == 0); \
809 set_fpr64(&ctx->fpr[fpr], 0, di); \
810 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \
811 set_fpr64(&ctx->fpr[fpr], i, 0); \
814 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
815 #define SPTOREG(sp, x) SITOREG((sp).bits, x)
816 #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
817 #define DPTOREG(dp, x) DITOREG((dp).bits, x)
820 * Emulate the single floating point instruction pointed at by EPC.
821 * Two instructions if the instruction is in a branch delay slot.
824 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
825 struct mm_decoded_insn dec_insn, void *__user *fault_addr)
827 unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
828 unsigned int cond, cbit;
839 * These are giving gcc a gentle hint about what to expect in
840 * dec_inst in order to do better optimization.
842 if (!cpu_has_mmips && dec_insn.micro_mips_mode)
845 /* XXX NEC Vr54xx bug workaround */
846 if (delay_slot(xcp)) {
847 if (dec_insn.micro_mips_mode) {
848 if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
849 clear_delay_slot(xcp);
851 if (!isBranchInstr(xcp, dec_insn, &contpc))
852 clear_delay_slot(xcp);
856 if (delay_slot(xcp)) {
858 * The instruction to be emulated is in a branch delay slot
859 * which means that we have to emulate the branch instruction
860 * BEFORE we do the cop1 instruction.
862 * This branch could be a COP1 branch, but in that case we
863 * would have had a trap for that instruction, and would not
864 * come through this route.
866 * Linux MIPS branch emulator operates on context, updating the
869 ir = dec_insn.next_insn; /* process delay slot instr */
870 pc_inc = dec_insn.next_pc_inc;
872 ir = dec_insn.insn; /* process current instr */
873 pc_inc = dec_insn.pc_inc;
877 * Since microMIPS FPU instructios are a subset of MIPS32 FPU
878 * instructions, we want to convert microMIPS FPU instructions
879 * into MIPS32 instructions so that we could reuse all of the
880 * FPU emulation code.
882 * NOTE: We cannot do this for branch instructions since they
883 * are not a subset. Example: Cannot emulate a 16-bit
884 * aligned target address with a MIPS32 instruction.
886 if (dec_insn.micro_mips_mode) {
888 * If next instruction is a 16-bit instruction, then it
889 * it cannot be a FPU instruction. This could happen
890 * since we can be called for non-FPU instructions.
893 (microMIPS32_to_MIPS32((union mips_instruction *)&ir)
899 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
900 MIPS_FPU_EMU_INC_STATS(emulated);
901 switch (MIPSInst_OPCODE(ir)) {
903 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
905 MIPS_FPU_EMU_INC_STATS(loads);
907 if (!access_ok(VERIFY_READ, dva, sizeof(u64))) {
908 MIPS_FPU_EMU_INC_STATS(errors);
912 if (__get_user(dval, dva)) {
913 MIPS_FPU_EMU_INC_STATS(errors);
917 DITOREG(dval, MIPSInst_RT(ir));
921 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
923 MIPS_FPU_EMU_INC_STATS(stores);
924 DIFROMREG(dval, MIPSInst_RT(ir));
925 if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) {
926 MIPS_FPU_EMU_INC_STATS(errors);
930 if (__put_user(dval, dva)) {
931 MIPS_FPU_EMU_INC_STATS(errors);
938 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
940 MIPS_FPU_EMU_INC_STATS(loads);
941 if (!access_ok(VERIFY_READ, wva, sizeof(u32))) {
942 MIPS_FPU_EMU_INC_STATS(errors);
946 if (__get_user(wval, wva)) {
947 MIPS_FPU_EMU_INC_STATS(errors);
951 SITOREG(wval, MIPSInst_RT(ir));
955 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
957 MIPS_FPU_EMU_INC_STATS(stores);
958 SIFROMREG(wval, MIPSInst_RT(ir));
959 if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) {
960 MIPS_FPU_EMU_INC_STATS(errors);
964 if (__put_user(wval, wva)) {
965 MIPS_FPU_EMU_INC_STATS(errors);
972 switch (MIPSInst_RS(ir)) {
974 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
977 /* copregister fs -> gpr[rt] */
978 if (MIPSInst_RT(ir) != 0) {
979 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
985 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
988 /* copregister fs <- rt */
989 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
993 if (!cpu_has_mips_r2)
996 /* copregister rd -> gpr[rt] */
997 if (MIPSInst_RT(ir) != 0) {
998 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
1004 if (!cpu_has_mips_r2)
1007 /* copregister rd <- gpr[rt] */
1008 SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1012 /* copregister rd -> gpr[rt] */
1013 if (MIPSInst_RT(ir) != 0) {
1014 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1020 /* copregister rd <- rt */
1021 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1025 /* cop control register rd -> gpr[rt] */
1026 if (MIPSInst_RD(ir) == FPCREG_CSR) {
1028 value = (value & ~FPU_CSR_RM) | modeindex(value);
1029 pr_debug("%p gpr[%d]<-csr=%08x\n",
1030 (void *) (xcp->cp0_epc),
1031 MIPSInst_RT(ir), value);
1033 else if (MIPSInst_RD(ir) == FPCREG_RID)
1037 if (MIPSInst_RT(ir))
1038 xcp->regs[MIPSInst_RT(ir)] = value;
1042 /* copregister rd <- rt */
1043 if (MIPSInst_RT(ir) == 0)
1046 value = xcp->regs[MIPSInst_RT(ir)];
1048 /* we only have one writable control reg
1050 if (MIPSInst_RD(ir) == FPCREG_CSR) {
1051 pr_debug("%p gpr[%d]->csr=%08x\n",
1052 (void *) (xcp->cp0_epc),
1053 MIPSInst_RT(ir), value);
1056 * Don't write reserved bits,
1057 * and convert to ieee library modes
1059 ctx->fcr31 = (value & ~(FPU_CSR_RSVD | FPU_CSR_RM)) |
1062 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1068 if (delay_slot(xcp))
1071 if (cpu_has_mips_4_5_r)
1072 cbit = fpucondbit[MIPSInst_RT(ir) >> 2];
1074 cbit = FPU_CSR_COND;
1075 cond = ctx->fcr31 & cbit;
1078 switch (MIPSInst_RT(ir) & 3) {
1089 /* thats an illegal instruction */
1093 set_delay_slot(xcp);
1096 * Branch taken: emulate dslot instruction
1098 xcp->cp0_epc += dec_insn.pc_inc;
1100 contpc = MIPSInst_SIMM(ir);
1101 ir = dec_insn.next_insn;
1102 if (dec_insn.micro_mips_mode) {
1103 contpc = (xcp->cp0_epc + (contpc << 1));
1105 /* If 16-bit instruction, not FPU. */
1106 if ((dec_insn.next_pc_inc == 2) ||
1107 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) {
1110 * Since this instruction will
1111 * be put on the stack with
1112 * 32-bit words, get around
1113 * this problem by putting a
1114 * NOP16 as the second one.
1116 if (dec_insn.next_pc_inc == 2)
1117 ir = (ir & (~0xffff)) | MM_NOP16;
1120 * Single step the non-CP1
1121 * instruction in the dslot.
1123 return mips_dsemul(xcp, ir, contpc);
1126 contpc = (xcp->cp0_epc + (contpc << 2));
1128 switch (MIPSInst_OPCODE(ir)) {
1137 if (cpu_has_mips_2_3_4_5 ||
1148 if (cpu_has_mips_4_5 || cpu_has_mips64 || cpu_has_mips32r2)
1149 /* its one of ours */
1155 if (!cpu_has_mips_4_5_r)
1158 if (MIPSInst_FUNC(ir) == movc_op)
1164 * Single step the non-cp1
1165 * instruction in the dslot
1167 return mips_dsemul(xcp, ir, contpc);
1168 } else if (likely) { /* branch not taken */
1170 * branch likely nullifies
1171 * dslot if not taken
1173 xcp->cp0_epc += dec_insn.pc_inc;
1174 contpc += dec_insn.pc_inc;
1176 * else continue & execute
1177 * dslot as normal insn
1183 if (!(MIPSInst_RS(ir) & 0x10))
1186 /* a real fpu computation instruction */
1187 if ((sig = fpu_emu(xcp, ctx, ir)))
1193 if (!cpu_has_mips_4_5 && !cpu_has_mips64 && !cpu_has_mips32r2)
1196 sig = fpux_emu(xcp, ctx, ir, fault_addr);
1202 if (!cpu_has_mips_4_5_r)
1205 if (MIPSInst_FUNC(ir) != movc_op)
1207 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
1208 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
1209 xcp->regs[MIPSInst_RD(ir)] =
1210 xcp->regs[MIPSInst_RS(ir)];
1218 xcp->cp0_epc = contpc;
1219 clear_delay_slot(xcp);
1225 * Conversion table from MIPS compare ops 48-63
1226 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1228 static const unsigned char cmptab[8] = {
1229 0, /* cmp_0 (sig) cmp_sf */
1230 IEEE754_CUN, /* cmp_un (sig) cmp_ngle */
1231 IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */
1232 IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */
1233 IEEE754_CLT, /* cmp_olt (sig) cmp_lt */
1234 IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */
1235 IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */
1236 IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */
1241 * Additional MIPS4 instructions
1244 #define DEF3OP(name, p, f1, f2, f3) \
1245 static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \
1246 union ieee754##p s, union ieee754##p t) \
1248 struct _ieee754_csr ieee754_csr_save; \
1250 ieee754_csr_save = ieee754_csr; \
1252 ieee754_csr_save.cx |= ieee754_csr.cx; \
1253 ieee754_csr_save.sx |= ieee754_csr.sx; \
1255 ieee754_csr.cx |= ieee754_csr_save.cx; \
1256 ieee754_csr.sx |= ieee754_csr_save.sx; \
1260 static union ieee754dp fpemu_dp_recip(union ieee754dp d)
1262 return ieee754dp_div(ieee754dp_one(0), d);
1265 static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d)
1267 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
1270 static union ieee754sp fpemu_sp_recip(union ieee754sp s)
1272 return ieee754sp_div(ieee754sp_one(0), s);
1275 static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s)
1277 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
1280 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
1281 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
1282 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
1283 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
1284 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
1285 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
1286 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
1287 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
1289 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1290 mips_instruction ir, void *__user *fault_addr)
1292 unsigned rcsr = 0; /* resulting csr */
1294 MIPS_FPU_EMU_INC_STATS(cp1xops);
1296 switch (MIPSInst_FMA_FFMT(ir)) {
1297 case s_fmt:{ /* 0 */
1299 union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp);
1300 union ieee754sp fd, fr, fs, ft;
1304 switch (MIPSInst_FUNC(ir)) {
1306 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1307 xcp->regs[MIPSInst_FT(ir)]);
1309 MIPS_FPU_EMU_INC_STATS(loads);
1310 if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
1311 MIPS_FPU_EMU_INC_STATS(errors);
1315 if (__get_user(val, va)) {
1316 MIPS_FPU_EMU_INC_STATS(errors);
1320 SITOREG(val, MIPSInst_FD(ir));
1324 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1325 xcp->regs[MIPSInst_FT(ir)]);
1327 MIPS_FPU_EMU_INC_STATS(stores);
1329 SIFROMREG(val, MIPSInst_FS(ir));
1330 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
1331 MIPS_FPU_EMU_INC_STATS(errors);
1335 if (put_user(val, va)) {
1336 MIPS_FPU_EMU_INC_STATS(errors);
1343 handler = fpemu_sp_madd;
1346 handler = fpemu_sp_msub;
1349 handler = fpemu_sp_nmadd;
1352 handler = fpemu_sp_nmsub;
1356 SPFROMREG(fr, MIPSInst_FR(ir));
1357 SPFROMREG(fs, MIPSInst_FS(ir));
1358 SPFROMREG(ft, MIPSInst_FT(ir));
1359 fd = (*handler) (fr, fs, ft);
1360 SPTOREG(fd, MIPSInst_FD(ir));
1363 if (ieee754_cxtest(IEEE754_INEXACT)) {
1364 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1365 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1367 if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1368 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1369 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1371 if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1372 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1373 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1375 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1376 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1377 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1380 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1381 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1382 /*printk ("SIGFPE: FPU csr = %08x\n",
1395 case d_fmt:{ /* 1 */
1396 union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp);
1397 union ieee754dp fd, fr, fs, ft;
1401 switch (MIPSInst_FUNC(ir)) {
1403 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1404 xcp->regs[MIPSInst_FT(ir)]);
1406 MIPS_FPU_EMU_INC_STATS(loads);
1407 if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
1408 MIPS_FPU_EMU_INC_STATS(errors);
1412 if (__get_user(val, va)) {
1413 MIPS_FPU_EMU_INC_STATS(errors);
1417 DITOREG(val, MIPSInst_FD(ir));
1421 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1422 xcp->regs[MIPSInst_FT(ir)]);
1424 MIPS_FPU_EMU_INC_STATS(stores);
1425 DIFROMREG(val, MIPSInst_FS(ir));
1426 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
1427 MIPS_FPU_EMU_INC_STATS(errors);
1431 if (__put_user(val, va)) {
1432 MIPS_FPU_EMU_INC_STATS(errors);
1439 handler = fpemu_dp_madd;
1442 handler = fpemu_dp_msub;
1445 handler = fpemu_dp_nmadd;
1448 handler = fpemu_dp_nmsub;
1452 DPFROMREG(fr, MIPSInst_FR(ir));
1453 DPFROMREG(fs, MIPSInst_FS(ir));
1454 DPFROMREG(ft, MIPSInst_FT(ir));
1455 fd = (*handler) (fr, fs, ft);
1456 DPTOREG(fd, MIPSInst_FD(ir));
1466 if (MIPSInst_FUNC(ir) != pfetch_op)
1469 /* ignore prefx operation */
1482 * Emulate a single COP1 arithmetic instruction.
1484 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1485 mips_instruction ir)
1487 int rfmt; /* resulting format */
1488 unsigned rcsr = 0; /* resulting csr */
1497 } rv; /* resulting value */
1500 MIPS_FPU_EMU_INC_STATS(cp1ops);
1501 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
1502 case s_fmt: { /* 0 */
1504 union ieee754sp(*b) (union ieee754sp, union ieee754sp);
1505 union ieee754sp(*u) (union ieee754sp);
1507 union ieee754sp fs, ft;
1509 switch (MIPSInst_FUNC(ir)) {
1512 handler.b = ieee754sp_add;
1515 handler.b = ieee754sp_sub;
1518 handler.b = ieee754sp_mul;
1521 handler.b = ieee754sp_div;
1526 if (!cpu_has_mips_4_5_r)
1529 handler.u = ieee754sp_sqrt;
1533 * Note that on some MIPS IV implementations such as the
1534 * R5000 and R8000 the FSQRT and FRECIP instructions do not
1535 * achieve full IEEE-754 accuracy - however this emulator does.
1538 if (!cpu_has_mips_4_5_r2)
1541 handler.u = fpemu_sp_rsqrt;
1545 if (!cpu_has_mips_4_5_r2)
1548 handler.u = fpemu_sp_recip;
1552 if (!cpu_has_mips_4_5_r)
1555 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1556 if (((ctx->fcr31 & cond) != 0) !=
1557 ((MIPSInst_FT(ir) & 1) != 0))
1559 SPFROMREG(rv.s, MIPSInst_FS(ir));
1563 if (!cpu_has_mips_4_5_r)
1566 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1568 SPFROMREG(rv.s, MIPSInst_FS(ir));
1572 if (!cpu_has_mips_4_5_r)
1575 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1577 SPFROMREG(rv.s, MIPSInst_FS(ir));
1581 handler.u = ieee754sp_abs;
1585 handler.u = ieee754sp_neg;
1590 SPFROMREG(rv.s, MIPSInst_FS(ir));
1593 /* binary op on handler */
1595 SPFROMREG(fs, MIPSInst_FS(ir));
1596 SPFROMREG(ft, MIPSInst_FT(ir));
1598 rv.s = (*handler.b) (fs, ft);
1601 SPFROMREG(fs, MIPSInst_FS(ir));
1602 rv.s = (*handler.u) (fs);
1605 if (ieee754_cxtest(IEEE754_INEXACT)) {
1606 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1607 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1609 if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1610 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1611 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1613 if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1614 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1615 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1617 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) {
1618 MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv);
1619 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
1621 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1622 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1623 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1627 /* unary conv ops */
1629 return SIGILL; /* not defined */
1632 SPFROMREG(fs, MIPSInst_FS(ir));
1633 rv.d = ieee754dp_fsp(fs);
1638 SPFROMREG(fs, MIPSInst_FS(ir));
1639 rv.w = ieee754sp_tint(fs);
1647 if (!cpu_has_mips_2_3_4_5 && !cpu_has_mips64)
1650 oldrm = ieee754_csr.rm;
1651 SPFROMREG(fs, MIPSInst_FS(ir));
1652 ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
1653 rv.w = ieee754sp_tint(fs);
1654 ieee754_csr.rm = oldrm;
1659 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1662 SPFROMREG(fs, MIPSInst_FS(ir));
1663 rv.l = ieee754sp_tlong(fs);
1671 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1674 oldrm = ieee754_csr.rm;
1675 SPFROMREG(fs, MIPSInst_FS(ir));
1676 ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
1677 rv.l = ieee754sp_tlong(fs);
1678 ieee754_csr.rm = oldrm;
1683 if (MIPSInst_FUNC(ir) >= fcmp_op) {
1684 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1685 union ieee754sp fs, ft;
1687 SPFROMREG(fs, MIPSInst_FS(ir));
1688 SPFROMREG(ft, MIPSInst_FT(ir));
1689 rv.w = ieee754sp_cmp(fs, ft,
1690 cmptab[cmpop & 0x7], cmpop & 0x8);
1692 if ((cmpop & 0x8) && ieee754_cxtest
1693 (IEEE754_INVALID_OPERATION))
1694 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1706 union ieee754dp fs, ft;
1708 union ieee754dp(*b) (union ieee754dp, union ieee754dp);
1709 union ieee754dp(*u) (union ieee754dp);
1712 switch (MIPSInst_FUNC(ir)) {
1715 handler.b = ieee754dp_add;
1718 handler.b = ieee754dp_sub;
1721 handler.b = ieee754dp_mul;
1724 handler.b = ieee754dp_div;
1729 if (!cpu_has_mips_2_3_4_5_r)
1732 handler.u = ieee754dp_sqrt;
1735 * Note that on some MIPS IV implementations such as the
1736 * R5000 and R8000 the FSQRT and FRECIP instructions do not
1737 * achieve full IEEE-754 accuracy - however this emulator does.
1740 if (!cpu_has_mips_4_5_r2)
1743 handler.u = fpemu_dp_rsqrt;
1746 if (!cpu_has_mips_4_5_r2)
1749 handler.u = fpemu_dp_recip;
1752 if (!cpu_has_mips_4_5_r)
1755 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1756 if (((ctx->fcr31 & cond) != 0) !=
1757 ((MIPSInst_FT(ir) & 1) != 0))
1759 DPFROMREG(rv.d, MIPSInst_FS(ir));
1762 if (!cpu_has_mips_4_5_r)
1765 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1767 DPFROMREG(rv.d, MIPSInst_FS(ir));
1770 if (!cpu_has_mips_4_5_r)
1773 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1775 DPFROMREG(rv.d, MIPSInst_FS(ir));
1778 handler.u = ieee754dp_abs;
1782 handler.u = ieee754dp_neg;
1787 DPFROMREG(rv.d, MIPSInst_FS(ir));
1790 /* binary op on handler */
1792 DPFROMREG(fs, MIPSInst_FS(ir));
1793 DPFROMREG(ft, MIPSInst_FT(ir));
1795 rv.d = (*handler.b) (fs, ft);
1798 DPFROMREG(fs, MIPSInst_FS(ir));
1799 rv.d = (*handler.u) (fs);
1806 DPFROMREG(fs, MIPSInst_FS(ir));
1807 rv.s = ieee754sp_fdp(fs);
1812 return SIGILL; /* not defined */
1815 DPFROMREG(fs, MIPSInst_FS(ir));
1816 rv.w = ieee754dp_tint(fs); /* wrong */
1824 if (!cpu_has_mips_2_3_4_5_r)
1827 oldrm = ieee754_csr.rm;
1828 DPFROMREG(fs, MIPSInst_FS(ir));
1829 ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
1830 rv.w = ieee754dp_tint(fs);
1831 ieee754_csr.rm = oldrm;
1836 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1839 DPFROMREG(fs, MIPSInst_FS(ir));
1840 rv.l = ieee754dp_tlong(fs);
1848 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1851 oldrm = ieee754_csr.rm;
1852 DPFROMREG(fs, MIPSInst_FS(ir));
1853 ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
1854 rv.l = ieee754dp_tlong(fs);
1855 ieee754_csr.rm = oldrm;
1860 if (MIPSInst_FUNC(ir) >= fcmp_op) {
1861 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1862 union ieee754dp fs, ft;
1864 DPFROMREG(fs, MIPSInst_FS(ir));
1865 DPFROMREG(ft, MIPSInst_FT(ir));
1866 rv.w = ieee754dp_cmp(fs, ft,
1867 cmptab[cmpop & 0x7], cmpop & 0x8);
1872 (IEEE754_INVALID_OPERATION))
1873 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1886 switch (MIPSInst_FUNC(ir)) {
1888 /* convert word to single precision real */
1889 SPFROMREG(fs, MIPSInst_FS(ir));
1890 rv.s = ieee754sp_fint(fs.bits);
1894 /* convert word to double precision real */
1895 SPFROMREG(fs, MIPSInst_FS(ir));
1896 rv.d = ieee754dp_fint(fs.bits);
1907 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1910 DIFROMREG(bits, MIPSInst_FS(ir));
1912 switch (MIPSInst_FUNC(ir)) {
1914 /* convert long to single precision real */
1915 rv.s = ieee754sp_flong(bits);
1919 /* convert long to double precision real */
1920 rv.d = ieee754dp_flong(bits);
1933 * Update the fpu CSR register for this operation.
1934 * If an exception is required, generate a tidy SIGFPE exception,
1935 * without updating the result register.
1936 * Note: cause exception bits do not accumulate, they are rewritten
1937 * for each op; only the flag/sticky bits accumulate.
1939 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1940 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1941 /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */
1946 * Now we can safely write the result back to the register file.
1951 if (cpu_has_mips_4_5_r)
1952 cbit = fpucondbit[MIPSInst_FD(ir) >> 2];
1954 cbit = FPU_CSR_COND;
1958 ctx->fcr31 &= ~cbit;
1962 DPTOREG(rv.d, MIPSInst_FD(ir));
1965 SPTOREG(rv.s, MIPSInst_FD(ir));
1968 SITOREG(rv.w, MIPSInst_FD(ir));
1971 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1974 DITOREG(rv.l, MIPSInst_FD(ir));
1983 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1984 int has_fpu, void *__user *fault_addr)
1986 unsigned long oldepc, prevepc;
1987 struct mm_decoded_insn dec_insn;
1992 oldepc = xcp->cp0_epc;
1994 prevepc = xcp->cp0_epc;
1996 if (get_isa16_mode(prevepc) && cpu_has_mmips) {
1998 * Get next 2 microMIPS instructions and convert them
1999 * into 32-bit instructions.
2001 if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) ||
2002 (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) ||
2003 (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) ||
2004 (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) {
2005 MIPS_FPU_EMU_INC_STATS(errors);
2010 /* Get first instruction. */
2011 if (mm_insn_16bit(*instr_ptr)) {
2012 /* Duplicate the half-word. */
2013 dec_insn.insn = (*instr_ptr << 16) |
2015 /* 16-bit instruction. */
2016 dec_insn.pc_inc = 2;
2019 dec_insn.insn = (*instr_ptr << 16) |
2021 /* 32-bit instruction. */
2022 dec_insn.pc_inc = 4;
2025 /* Get second instruction. */
2026 if (mm_insn_16bit(*instr_ptr)) {
2027 /* Duplicate the half-word. */
2028 dec_insn.next_insn = (*instr_ptr << 16) |
2030 /* 16-bit instruction. */
2031 dec_insn.next_pc_inc = 2;
2033 dec_insn.next_insn = (*instr_ptr << 16) |
2035 /* 32-bit instruction. */
2036 dec_insn.next_pc_inc = 4;
2038 dec_insn.micro_mips_mode = 1;
2040 if ((get_user(dec_insn.insn,
2041 (mips_instruction __user *) xcp->cp0_epc)) ||
2042 (get_user(dec_insn.next_insn,
2043 (mips_instruction __user *)(xcp->cp0_epc+4)))) {
2044 MIPS_FPU_EMU_INC_STATS(errors);
2047 dec_insn.pc_inc = 4;
2048 dec_insn.next_pc_inc = 4;
2049 dec_insn.micro_mips_mode = 0;
2052 if ((dec_insn.insn == 0) ||
2053 ((dec_insn.pc_inc == 2) &&
2054 ((dec_insn.insn & 0xffff) == MM_NOP16)))
2055 xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */
2058 * The 'ieee754_csr' is an alias of
2059 * ctx->fcr31. No need to copy ctx->fcr31 to
2060 * ieee754_csr. But ieee754_csr.rm is ieee
2061 * library modes. (not mips rounding mode)
2063 sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
2072 } while (xcp->cp0_epc > prevepc);
2074 /* SIGILL indicates a non-fpu instruction */
2075 if (sig == SIGILL && xcp->cp0_epc != oldepc)
2076 /* but if EPC has advanced, then ignore it */