2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Main entry point for the guest, exception handling.
8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
9 * Authors: Sanjay Lal <sanjayl@kymasys.com>
13 #include <asm/asmmacro.h>
14 #include <asm/regdef.h>
15 #include <asm/mipsregs.h>
16 #include <asm/stackframe.h>
17 #include <asm/asm-offsets.h>
20 #define MIPSX(name) mips32_ ## name
21 #define CALLFRAME_SIZ 32
25 * exception vector entrypoint
27 #define VECTOR(x, regmask) \
31 #define VECTOR_END(x) \
34 /* Overload, Danger Will Robinson!! */
35 #define PT_HOST_USERLOCAL PT_EPC
37 #define CP0_DDATA_LO $28,3
40 #define RESUME_FLAG_HOST (1<<1) /* Resume host? */
42 #define RESUME_GUEST 0
43 #define RESUME_HOST RESUME_FLAG_HOST
46 * __kvm_mips_vcpu_run: entry point to the guest
52 FEXPORT(__kvm_mips_vcpu_run)
53 /* k0/k1 not being used in host kernel context */
54 INT_ADDIU k1, sp, -PT_SIZE
55 LONG_S $16, PT_R16(k1)
56 LONG_S $17, PT_R17(k1)
57 LONG_S $18, PT_R18(k1)
58 LONG_S $19, PT_R19(k1)
59 LONG_S $20, PT_R20(k1)
60 LONG_S $21, PT_R21(k1)
61 LONG_S $22, PT_R22(k1)
62 LONG_S $23, PT_R23(k1)
64 LONG_S $28, PT_R28(k1)
65 LONG_S $29, PT_R29(k1)
66 LONG_S $30, PT_R30(k1)
67 LONG_S $31, PT_R31(k1)
75 /* Save host status */
77 LONG_S v0, PT_STATUS(k1)
79 /* Save DDATA_LO, will be used to store pointer to vcpu */
81 LONG_S v1, PT_HOST_USERLOCAL(k1)
83 /* DDATA_LO has pointer to vcpu */
86 /* Offset into vcpu->arch */
87 INT_ADDIU k1, a1, VCPU_HOST_ARCH
90 * Save the host stack to VCPU, used for exception processing
91 * when we exit from the Guest
93 LONG_S sp, VCPU_HOST_STACK(k1)
95 /* Save the kernel gp as well */
96 LONG_S gp, VCPU_HOST_GP(k1)
99 * Setup status register for running the guest in UM, interrupts
102 li k0, (ST0_EXL | KSU_USER | ST0_BEV)
106 /* load up the new EBASE */
107 LONG_L k0, VCPU_GUEST_EBASE(k1)
111 * Now that the new EBASE has been loaded, unset BEV, set
112 * interrupt mask as it was but make sure that timer interrupts
115 li k0, (ST0_EXL | KSU_USER | ST0_IE)
122 LONG_L t0, VCPU_PC(k1)
125 FEXPORT(__kvm_mips_load_asid)
126 /* Set the ASID for the Guest Kernel */
127 PTR_L t0, VCPU_COP0(k1)
128 LONG_L t0, COP0_STATUS(t0)
129 andi t0, KSU_USER | ST0_ERL | ST0_EXL
131 bnez t0, 1f /* If kernel */
132 INT_ADDIU t1, k1, VCPU_GUEST_KERNEL_ASID /* (BD) */
133 INT_ADDIU t1, k1, VCPU_GUEST_USER_ASID /* else user */
135 /* t1: contains the base of the ASID array, need to get the cpu id */
136 LONG_L t2, TI_CPU($28) /* smp_processor_id */
137 INT_SLL t2, t2, 2 /* x4 */
140 #ifdef CONFIG_MIPS_ASID_BITS_VARIABLE
141 li t3, CPUINFO_SIZE/4
142 mul t2, t2, t3 /* x sizeof(struct cpuinfo_mips)/4 */
143 LONG_L t2, (cpu_data + CPUINFO_ASID_MASK)(t2)
146 andi k0, k0, MIPS_ENTRYHI_ASID
151 /* Disable RDHWR access */
152 mtc0 zero, CP0_HWRENA
155 /* Now load up the Guest Context from VCPU */
156 LONG_L $1, VCPU_R1(k1)
157 LONG_L $2, VCPU_R2(k1)
158 LONG_L $3, VCPU_R3(k1)
160 LONG_L $4, VCPU_R4(k1)
161 LONG_L $5, VCPU_R5(k1)
162 LONG_L $6, VCPU_R6(k1)
163 LONG_L $7, VCPU_R7(k1)
165 LONG_L $8, VCPU_R8(k1)
166 LONG_L $9, VCPU_R9(k1)
167 LONG_L $10, VCPU_R10(k1)
168 LONG_L $11, VCPU_R11(k1)
169 LONG_L $12, VCPU_R12(k1)
170 LONG_L $13, VCPU_R13(k1)
171 LONG_L $14, VCPU_R14(k1)
172 LONG_L $15, VCPU_R15(k1)
173 LONG_L $16, VCPU_R16(k1)
174 LONG_L $17, VCPU_R17(k1)
175 LONG_L $18, VCPU_R18(k1)
176 LONG_L $19, VCPU_R19(k1)
177 LONG_L $20, VCPU_R20(k1)
178 LONG_L $21, VCPU_R21(k1)
179 LONG_L $22, VCPU_R22(k1)
180 LONG_L $23, VCPU_R23(k1)
181 LONG_L $24, VCPU_R24(k1)
182 LONG_L $25, VCPU_R25(k1)
184 /* k0/k1 loaded up later */
186 LONG_L $28, VCPU_R28(k1)
187 LONG_L $29, VCPU_R29(k1)
188 LONG_L $30, VCPU_R30(k1)
189 LONG_L $31, VCPU_R31(k1)
192 LONG_L k0, VCPU_LO(k1)
195 LONG_L k0, VCPU_HI(k1)
198 FEXPORT(__kvm_mips_load_k0k1)
199 /* Restore the guest's k0/k1 registers */
200 LONG_L k0, VCPU_R26(k1)
201 LONG_L k1, VCPU_R27(k1)
206 VECTOR(MIPSX(exception), unknown)
207 /* Find out what mode we came from and jump to the proper handler. */
208 mtc0 k0, CP0_ERROREPC #01: Save guest k0
211 mfc0 k0, CP0_EBASE #02: Get EBASE
212 INT_SRL k0, k0, 10 #03: Get rid of CPUNum
213 INT_SLL k0, k0, 10 #04
214 LONG_S k1, 0x3000(k0) #05: Save k1 @ offset 0x3000
215 INT_ADDIU k0, k0, 0x2000 #06: Exception handler is
216 # installed @ offset 0x2000
217 j k0 #07: jump to the function
218 nop #08: branch delay slot
219 VECTOR_END(MIPSX(exceptionEnd))
220 .end MIPSX(exception)
223 * Generic Guest exception handler. We end up here when the guest
224 * does something that causes a trap to kernel mode.
226 NESTED (MIPSX(GuestException), CALLFRAME_SIZ, ra)
227 /* Get the VCPU pointer from DDTATA_LO */
228 mfc0 k1, CP0_DDATA_LO
229 INT_ADDIU k1, k1, VCPU_HOST_ARCH
231 /* Start saving Guest context to VCPU */
232 LONG_S $0, VCPU_R0(k1)
233 LONG_S $1, VCPU_R1(k1)
234 LONG_S $2, VCPU_R2(k1)
235 LONG_S $3, VCPU_R3(k1)
236 LONG_S $4, VCPU_R4(k1)
237 LONG_S $5, VCPU_R5(k1)
238 LONG_S $6, VCPU_R6(k1)
239 LONG_S $7, VCPU_R7(k1)
240 LONG_S $8, VCPU_R8(k1)
241 LONG_S $9, VCPU_R9(k1)
242 LONG_S $10, VCPU_R10(k1)
243 LONG_S $11, VCPU_R11(k1)
244 LONG_S $12, VCPU_R12(k1)
245 LONG_S $13, VCPU_R13(k1)
246 LONG_S $14, VCPU_R14(k1)
247 LONG_S $15, VCPU_R15(k1)
248 LONG_S $16, VCPU_R16(k1)
249 LONG_S $17, VCPU_R17(k1)
250 LONG_S $18, VCPU_R18(k1)
251 LONG_S $19, VCPU_R19(k1)
252 LONG_S $20, VCPU_R20(k1)
253 LONG_S $21, VCPU_R21(k1)
254 LONG_S $22, VCPU_R22(k1)
255 LONG_S $23, VCPU_R23(k1)
256 LONG_S $24, VCPU_R24(k1)
257 LONG_S $25, VCPU_R25(k1)
259 /* Guest k0/k1 saved later */
261 LONG_S $28, VCPU_R28(k1)
262 LONG_S $29, VCPU_R29(k1)
263 LONG_S $30, VCPU_R30(k1)
264 LONG_S $31, VCPU_R31(k1)
268 /* We need to save hi/lo and restore them on the way out */
270 LONG_S t0, VCPU_HI(k1)
273 LONG_S t0, VCPU_LO(k1)
275 /* Finally save guest k0/k1 to VCPU */
276 mfc0 t0, CP0_ERROREPC
277 LONG_S t0, VCPU_R26(k1)
279 /* Get GUEST k1 and save it in VCPU */
283 LONG_L t0, 0x3000(t0)
284 LONG_S t0, VCPU_R27(k1)
286 /* Now that context has been saved, we can use other registers */
289 mfc0 a1, CP0_DDATA_LO
292 /* Restore run (vcpu->run) */
293 LONG_L a0, VCPU_RUN(a1)
294 /* Save pointer to run in s0, will be saved by the compiler */
298 * Save Host level EPC, BadVaddr and Cause to VCPU, useful to
299 * process the exception
302 LONG_S k0, VCPU_PC(k1)
304 mfc0 k0, CP0_BADVADDR
305 LONG_S k0, VCPU_HOST_CP0_BADVADDR(k1)
308 LONG_S k0, VCPU_HOST_CP0_CAUSE(k1)
311 LONG_S k0, VCPU_HOST_ENTRYHI(k1)
313 /* Now restore the host state just enough to run the handlers */
315 /* Switch EBASE to the one used by Linux */
316 /* load up the host EBASE */
324 LONG_L k0, VCPU_HOST_EBASE(k1)
328 * If FPU is enabled, save FCR31 and clear it so that later ctc1's don't
329 * trigger FPE for pending exceptions.
337 sw t0, VCPU_FCR31(k1)
342 #ifdef CONFIG_CPU_HAS_MSA
344 * If MSA is enabled, save MSACSR and clear it so that later
345 * instructions don't trigger MSAFPE for pending exceptions.
348 ext t0, t0, 28, 1 /* MIPS_CONF3_MSAP */
352 ext t0, t0, 27, 1 /* MIPS_CONF5_MSAEN */
356 sw t0, VCPU_MSA_CSR(k1)
357 _ctcmsa MSA_CSR, zero
361 /* Now that the new EBASE has been loaded, unset BEV and KSU_USER */
362 and v0, v0, ~(ST0_EXL | KSU_USER | ST0_IE)
367 /* Load up host GP */
368 LONG_L gp, VCPU_HOST_GP(k1)
370 /* Need a stack before we can jump to "C" */
371 LONG_L sp, VCPU_HOST_STACK(k1)
373 /* Saved host state */
374 INT_ADDIU sp, sp, -PT_SIZE
377 * XXXKYMA do we need to load the host ASID, maybe not because the
378 * kernel entries are marked GLOBAL, need to verify
381 /* Restore host DDATA_LO */
382 LONG_L k0, PT_HOST_USERLOCAL(sp)
383 mtc0 k0, CP0_DDATA_LO
385 /* Restore RDHWR access */
386 PTR_LI k0, 0x2000000F
389 /* Jump to handler */
390 FEXPORT(__kvm_mips_jump_to_handler)
392 * XXXKYMA: not sure if this is safe, how large is the stack??
393 * Now jump to the kvm_mips_handle_exit() to see if we can deal
394 * with this in the kernel
396 PTR_LA t9, kvm_mips_handle_exit
398 INT_ADDIU sp, sp, -CALLFRAME_SIZ /* BD Slot */
400 /* Return from handler Make sure interrupts are disabled */
405 * XXXKYMA: k0/k1 could have been blown away if we processed
406 * an exception while we were handling the exception from the
411 INT_ADDIU k1, k1, VCPU_HOST_ARCH
414 * Check return value, should tell us if we are returning to the
415 * host (handle I/O etc)or resuming the guest
417 andi t0, v0, RESUME_HOST
418 bnez t0, __kvm_mips_return_to_host
421 __kvm_mips_return_to_guest:
422 /* Put the saved pointer to vcpu (s1) back into the DDATA_LO Register */
423 mtc0 s1, CP0_DDATA_LO
425 /* Load up the Guest EBASE to minimize the window where BEV is set */
426 LONG_L t0, VCPU_GUEST_EBASE(k1)
428 /* Switch EBASE back to the one used by KVM */
435 /* Setup status register for running guest in UM */
436 or v1, v1, (ST0_EXL | KSU_USER | ST0_IE)
437 and v1, v1, ~(ST0_CU0 | ST0_MX)
442 LONG_L t0, VCPU_PC(k1)
445 /* Set the ASID for the Guest Kernel */
446 PTR_L t0, VCPU_COP0(k1)
447 LONG_L t0, COP0_STATUS(t0)
448 andi t0, KSU_USER | ST0_ERL | ST0_EXL
450 bnez t0, 1f /* If kernel */
451 INT_ADDIU t1, k1, VCPU_GUEST_KERNEL_ASID /* (BD) */
452 INT_ADDIU t1, k1, VCPU_GUEST_USER_ASID /* else user */
454 /* t1: contains the base of the ASID array, need to get the cpu id */
455 LONG_L t2, TI_CPU($28) /* smp_processor_id */
456 INT_SLL t2, t2, 2 /* x4 */
459 #ifdef CONFIG_MIPS_ASID_BITS_VARIABLE
460 li t3, CPUINFO_SIZE/4
461 mul t2, t2, t3 /* x sizeof(struct cpuinfo_mips)/4 */
462 LONG_L t2, (cpu_data + CPUINFO_ASID_MASK)(t2)
465 andi k0, k0, MIPS_ENTRYHI_ASID
470 /* Disable RDHWR access */
471 mtc0 zero, CP0_HWRENA
474 /* load the guest context from VCPU and return */
475 LONG_L $0, VCPU_R0(k1)
476 LONG_L $1, VCPU_R1(k1)
477 LONG_L $2, VCPU_R2(k1)
478 LONG_L $3, VCPU_R3(k1)
479 LONG_L $4, VCPU_R4(k1)
480 LONG_L $5, VCPU_R5(k1)
481 LONG_L $6, VCPU_R6(k1)
482 LONG_L $7, VCPU_R7(k1)
483 LONG_L $8, VCPU_R8(k1)
484 LONG_L $9, VCPU_R9(k1)
485 LONG_L $10, VCPU_R10(k1)
486 LONG_L $11, VCPU_R11(k1)
487 LONG_L $12, VCPU_R12(k1)
488 LONG_L $13, VCPU_R13(k1)
489 LONG_L $14, VCPU_R14(k1)
490 LONG_L $15, VCPU_R15(k1)
491 LONG_L $16, VCPU_R16(k1)
492 LONG_L $17, VCPU_R17(k1)
493 LONG_L $18, VCPU_R18(k1)
494 LONG_L $19, VCPU_R19(k1)
495 LONG_L $20, VCPU_R20(k1)
496 LONG_L $21, VCPU_R21(k1)
497 LONG_L $22, VCPU_R22(k1)
498 LONG_L $23, VCPU_R23(k1)
499 LONG_L $24, VCPU_R24(k1)
500 LONG_L $25, VCPU_R25(k1)
502 /* $/k1 loaded later */
503 LONG_L $28, VCPU_R28(k1)
504 LONG_L $29, VCPU_R29(k1)
505 LONG_L $30, VCPU_R30(k1)
506 LONG_L $31, VCPU_R31(k1)
508 FEXPORT(__kvm_mips_skip_guest_restore)
509 LONG_L k0, VCPU_HI(k1)
512 LONG_L k0, VCPU_LO(k1)
515 LONG_L k0, VCPU_R26(k1)
516 LONG_L k1, VCPU_R27(k1)
521 __kvm_mips_return_to_host:
522 /* EBASE is already pointing to Linux */
523 LONG_L k1, VCPU_HOST_STACK(k1)
524 INT_ADDIU k1,k1, -PT_SIZE
526 /* Restore host DDATA_LO */
527 LONG_L k0, PT_HOST_USERLOCAL(k1)
528 mtc0 k0, CP0_DDATA_LO
531 * r2/v0 is the return code, shift it down by 2 (arithmetic)
532 * to recover the err code
537 /* Load context saved on the host stack */
538 LONG_L $16, PT_R16(k1)
539 LONG_L $17, PT_R17(k1)
540 LONG_L $18, PT_R18(k1)
541 LONG_L $19, PT_R19(k1)
542 LONG_L $20, PT_R20(k1)
543 LONG_L $21, PT_R21(k1)
544 LONG_L $22, PT_R22(k1)
545 LONG_L $23, PT_R23(k1)
547 LONG_L $28, PT_R28(k1)
548 LONG_L $29, PT_R29(k1)
549 LONG_L $30, PT_R30(k1)
557 /* Restore RDHWR access */
558 PTR_LI k0, 0x2000000F
561 /* Restore RA, which is the address we will return to */
562 LONG_L ra, PT_R31(k1)
566 VECTOR_END(MIPSX(GuestExceptionEnd))
567 .end MIPSX(GuestException)
571 ##### The exception handlers.
573 .word _C_LABEL(MIPSX(GuestException)) # 0
574 .word _C_LABEL(MIPSX(GuestException)) # 1
575 .word _C_LABEL(MIPSX(GuestException)) # 2
576 .word _C_LABEL(MIPSX(GuestException)) # 3
577 .word _C_LABEL(MIPSX(GuestException)) # 4
578 .word _C_LABEL(MIPSX(GuestException)) # 5
579 .word _C_LABEL(MIPSX(GuestException)) # 6
580 .word _C_LABEL(MIPSX(GuestException)) # 7
581 .word _C_LABEL(MIPSX(GuestException)) # 8
582 .word _C_LABEL(MIPSX(GuestException)) # 9
583 .word _C_LABEL(MIPSX(GuestException)) # 10
584 .word _C_LABEL(MIPSX(GuestException)) # 11
585 .word _C_LABEL(MIPSX(GuestException)) # 12
586 .word _C_LABEL(MIPSX(GuestException)) # 13
587 .word _C_LABEL(MIPSX(GuestException)) # 14
588 .word _C_LABEL(MIPSX(GuestException)) # 15
589 .word _C_LABEL(MIPSX(GuestException)) # 16
590 .word _C_LABEL(MIPSX(GuestException)) # 17
591 .word _C_LABEL(MIPSX(GuestException)) # 18
592 .word _C_LABEL(MIPSX(GuestException)) # 19
593 .word _C_LABEL(MIPSX(GuestException)) # 20
594 .word _C_LABEL(MIPSX(GuestException)) # 21
595 .word _C_LABEL(MIPSX(GuestException)) # 22
596 .word _C_LABEL(MIPSX(GuestException)) # 23
597 .word _C_LABEL(MIPSX(GuestException)) # 24
598 .word _C_LABEL(MIPSX(GuestException)) # 25
599 .word _C_LABEL(MIPSX(GuestException)) # 26
600 .word _C_LABEL(MIPSX(GuestException)) # 27
601 .word _C_LABEL(MIPSX(GuestException)) # 28
602 .word _C_LABEL(MIPSX(GuestException)) # 29
603 .word _C_LABEL(MIPSX(GuestException)) # 30
604 .word _C_LABEL(MIPSX(GuestException)) # 31