2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * KVM/MIPS: Binary Patching for privileged instructions, reduces traps.
8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
9 * Authors: Sanjay Lal <sanjayl@kymasys.com>
12 #include <linux/errno.h>
13 #include <linux/err.h>
14 #include <linux/kvm_host.h>
15 #include <linux/module.h>
16 #include <linux/vmalloc.h>
18 #include <linux/bootmem.h>
19 #include <asm/cacheflush.h>
23 #define SYNCI_TEMPLATE 0x041f0000
24 #define SYNCI_BASE(x) (((x) >> 21) & 0x1f)
25 #define SYNCI_OFFSET ((x) & 0xffff)
27 #define LW_TEMPLATE 0x8c000000
28 #define CLEAR_TEMPLATE 0x00000020
29 #define SW_TEMPLATE 0xac000000
31 int kvm_mips_trans_cache_index(uint32_t inst, uint32_t *opc,
32 struct kvm_vcpu *vcpu)
35 unsigned long kseg0_opc;
36 uint32_t synci_inst = 0x0;
38 /* Replace the CACHE instruction, with a NOP */
40 CKSEG0ADDR(kvm_mips_translate_guest_kseg0_to_hpa
41 (vcpu, (unsigned long) opc));
42 memcpy((void *)kseg0_opc, (void *)&synci_inst, sizeof(uint32_t));
43 local_flush_icache_range(kseg0_opc, kseg0_opc + 32);
49 * Address based CACHE instructions are transformed into synci(s). A little
50 * heavy for just D-cache invalidates, but avoids an expensive trap
52 int kvm_mips_trans_cache_va(uint32_t inst, uint32_t *opc,
53 struct kvm_vcpu *vcpu)
56 unsigned long kseg0_opc;
57 uint32_t synci_inst = SYNCI_TEMPLATE, base, offset;
59 base = (inst >> 21) & 0x1f;
60 offset = inst & 0xffff;
61 synci_inst |= (base << 21);
65 CKSEG0ADDR(kvm_mips_translate_guest_kseg0_to_hpa
66 (vcpu, (unsigned long) opc));
67 memcpy((void *)kseg0_opc, (void *)&synci_inst, sizeof(uint32_t));
68 local_flush_icache_range(kseg0_opc, kseg0_opc + 32);
73 int kvm_mips_trans_mfc0(uint32_t inst, uint32_t *opc, struct kvm_vcpu *vcpu)
77 unsigned long kseg0_opc, flags;
79 rt = (inst >> 16) & 0x1f;
80 rd = (inst >> 11) & 0x1f;
83 if ((rd == MIPS_CP0_ERRCTL) && (sel == 0)) {
84 mfc0_inst = CLEAR_TEMPLATE;
85 mfc0_inst |= ((rt & 0x1f) << 16);
87 mfc0_inst = LW_TEMPLATE;
88 mfc0_inst |= ((rt & 0x1f) << 16);
89 mfc0_inst |= offsetof(struct kvm_mips_commpage,
93 if (KVM_GUEST_KSEGX(opc) == KVM_GUEST_KSEG0) {
95 CKSEG0ADDR(kvm_mips_translate_guest_kseg0_to_hpa
96 (vcpu, (unsigned long) opc));
97 memcpy((void *)kseg0_opc, (void *)&mfc0_inst, sizeof(uint32_t));
98 local_flush_icache_range(kseg0_opc, kseg0_opc + 32);
99 } else if (KVM_GUEST_KSEGX((unsigned long) opc) == KVM_GUEST_KSEG23) {
100 local_irq_save(flags);
101 memcpy((void *)opc, (void *)&mfc0_inst, sizeof(uint32_t));
102 local_flush_icache_range((unsigned long)opc,
103 (unsigned long)opc + 32);
104 local_irq_restore(flags);
106 kvm_err("%s: Invalid address: %p\n", __func__, opc);
113 int kvm_mips_trans_mtc0(uint32_t inst, uint32_t *opc, struct kvm_vcpu *vcpu)
116 uint32_t mtc0_inst = SW_TEMPLATE;
117 unsigned long kseg0_opc, flags;
119 rt = (inst >> 16) & 0x1f;
120 rd = (inst >> 11) & 0x1f;
123 mtc0_inst |= ((rt & 0x1f) << 16);
124 mtc0_inst |= offsetof(struct kvm_mips_commpage, cop0.reg[rd][sel]);
126 if (KVM_GUEST_KSEGX(opc) == KVM_GUEST_KSEG0) {
128 CKSEG0ADDR(kvm_mips_translate_guest_kseg0_to_hpa
129 (vcpu, (unsigned long) opc));
130 memcpy((void *)kseg0_opc, (void *)&mtc0_inst, sizeof(uint32_t));
131 local_flush_icache_range(kseg0_opc, kseg0_opc + 32);
132 } else if (KVM_GUEST_KSEGX((unsigned long) opc) == KVM_GUEST_KSEG23) {
133 local_irq_save(flags);
134 memcpy((void *)opc, (void *)&mtc0_inst, sizeof(uint32_t));
135 local_flush_icache_range((unsigned long)opc,
136 (unsigned long)opc + 32);
137 local_irq_restore(flags);
139 kvm_err("%s: Invalid address: %p\n", __func__, opc);