2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
12 * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved.
13 * Copyright (C) 2014, Imagination Technologies Ltd.
15 #include <linux/bitops.h>
16 #include <linux/bug.h>
17 #include <linux/compiler.h>
18 #include <linux/context_tracking.h>
19 #include <linux/cpu_pm.h>
20 #include <linux/kexec.h>
21 #include <linux/init.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/extable.h>
26 #include <linux/sched/mm.h>
27 #include <linux/sched/debug.h>
28 #include <linux/smp.h>
29 #include <linux/spinlock.h>
30 #include <linux/kallsyms.h>
31 #include <linux/bootmem.h>
32 #include <linux/interrupt.h>
33 #include <linux/ptrace.h>
34 #include <linux/kgdb.h>
35 #include <linux/kdebug.h>
36 #include <linux/kprobes.h>
37 #include <linux/notifier.h>
38 #include <linux/kdb.h>
39 #include <linux/irq.h>
40 #include <linux/perf_event.h>
42 #include <asm/addrspace.h>
43 #include <asm/bootinfo.h>
44 #include <asm/branch.h>
45 #include <asm/break.h>
48 #include <asm/cpu-type.h>
51 #include <asm/fpu_emulator.h>
53 #include <asm/mips-cps.h>
54 #include <asm/mips-r2-to-r6-emul.h>
55 #include <asm/mipsregs.h>
56 #include <asm/mipsmtregs.h>
57 #include <asm/module.h>
59 #include <asm/pgtable.h>
60 #include <asm/ptrace.h>
61 #include <asm/sections.h>
62 #include <asm/siginfo.h>
63 #include <asm/tlbdebug.h>
64 #include <asm/traps.h>
65 #include <linux/uaccess.h>
66 #include <asm/watch.h>
67 #include <asm/mmu_context.h>
68 #include <asm/types.h>
69 #include <asm/stacktrace.h>
72 extern void check_wait(void);
73 extern asmlinkage void rollback_handle_int(void);
74 extern asmlinkage void handle_int(void);
75 extern u32 handle_tlbl[];
76 extern u32 handle_tlbs[];
77 extern u32 handle_tlbm[];
78 extern asmlinkage void handle_adel(void);
79 extern asmlinkage void handle_ades(void);
80 extern asmlinkage void handle_ibe(void);
81 extern asmlinkage void handle_dbe(void);
82 extern asmlinkage void handle_sys(void);
83 extern asmlinkage void handle_bp(void);
84 extern asmlinkage void handle_ri(void);
85 extern asmlinkage void handle_ri_rdhwr_tlbp(void);
86 extern asmlinkage void handle_ri_rdhwr(void);
87 extern asmlinkage void handle_cpu(void);
88 extern asmlinkage void handle_ov(void);
89 extern asmlinkage void handle_tr(void);
90 extern asmlinkage void handle_msa_fpe(void);
91 extern asmlinkage void handle_fpe(void);
92 extern asmlinkage void handle_ftlb(void);
93 extern asmlinkage void handle_msa(void);
94 extern asmlinkage void handle_mdmx(void);
95 extern asmlinkage void handle_watch(void);
96 extern asmlinkage void handle_mt(void);
97 extern asmlinkage void handle_dsp(void);
98 extern asmlinkage void handle_mcheck(void);
99 extern asmlinkage void handle_reserved(void);
100 extern void tlb_do_page_fault_0(void);
102 void (*board_be_init)(void);
103 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
104 void (*board_nmi_handler_setup)(void);
105 void (*board_ejtag_handler_setup)(void);
106 void (*board_bind_eic_interrupt)(int irq, int regset);
107 void (*board_ebase_setup)(void);
108 void(*board_cache_error_setup)(void);
110 static void show_raw_backtrace(unsigned long reg29)
112 unsigned long *sp = (unsigned long *)(reg29 & ~3);
115 printk("Call Trace:");
116 #ifdef CONFIG_KALLSYMS
119 while (!kstack_end(sp)) {
120 unsigned long __user *p =
121 (unsigned long __user *)(unsigned long)sp++;
122 if (__get_user(addr, p)) {
123 printk(" (Bad stack address)");
126 if (__kernel_text_address(addr))
132 #ifdef CONFIG_KALLSYMS
134 static int __init set_raw_show_trace(char *str)
139 __setup("raw_show_trace", set_raw_show_trace);
142 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs)
144 unsigned long sp = regs->regs[29];
145 unsigned long ra = regs->regs[31];
146 unsigned long pc = regs->cp0_epc;
151 if (raw_show_trace || user_mode(regs) || !__kernel_text_address(pc)) {
152 show_raw_backtrace(sp);
155 printk("Call Trace:\n");
158 pc = unwind_stack(task, &sp, pc, &ra);
164 * This routine abuses get_user()/put_user() to reference pointers
165 * with at least a bit of error checking ...
167 static void show_stacktrace(struct task_struct *task,
168 const struct pt_regs *regs)
170 const int field = 2 * sizeof(unsigned long);
173 unsigned long __user *sp = (unsigned long __user *)regs->regs[29];
177 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
178 if (i && ((i % (64 / field)) == 0)) {
187 if (__get_user(stackdata, sp++)) {
188 pr_cont(" (Bad stack address)");
192 pr_cont(" %0*lx", field, stackdata);
196 show_backtrace(task, regs);
199 void show_stack(struct task_struct *task, unsigned long *sp)
202 mm_segment_t old_fs = get_fs();
204 regs.cp0_status = KSU_KERNEL;
206 regs.regs[29] = (unsigned long)sp;
210 if (task && task != current) {
211 regs.regs[29] = task->thread.reg29;
213 regs.cp0_epc = task->thread.reg31;
214 #ifdef CONFIG_KGDB_KDB
215 } else if (atomic_read(&kgdb_active) != -1 &&
217 memcpy(®s, kdb_current_regs, sizeof(regs));
218 #endif /* CONFIG_KGDB_KDB */
220 prepare_frametrace(®s);
224 * show_stack() deals exclusively with kernel mode, so be sure to access
225 * the stack in the kernel (not user) address space.
228 show_stacktrace(task, ®s);
232 static void show_code(unsigned int __user *pc)
235 unsigned short __user *pc16 = NULL;
239 if ((unsigned long)pc & 1)
240 pc16 = (unsigned short __user *)((unsigned long)pc & ~1);
241 for(i = -3 ; i < 6 ; i++) {
243 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) {
244 pr_cont(" (Bad address in epc)\n");
247 pr_cont("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>'));
252 static void __show_regs(const struct pt_regs *regs)
254 const int field = 2 * sizeof(unsigned long);
255 unsigned int cause = regs->cp0_cause;
256 unsigned int exccode;
259 show_regs_print_info(KERN_DEFAULT);
262 * Saved main processor registers
264 for (i = 0; i < 32; ) {
268 pr_cont(" %0*lx", field, 0UL);
269 else if (i == 26 || i == 27)
270 pr_cont(" %*s", field, "");
272 pr_cont(" %0*lx", field, regs->regs[i]);
279 #ifdef CONFIG_CPU_HAS_SMARTMIPS
280 printk("Acx : %0*lx\n", field, regs->acx);
282 printk("Hi : %0*lx\n", field, regs->hi);
283 printk("Lo : %0*lx\n", field, regs->lo);
286 * Saved cp0 registers
288 printk("epc : %0*lx %pS\n", field, regs->cp0_epc,
289 (void *) regs->cp0_epc);
290 printk("ra : %0*lx %pS\n", field, regs->regs[31],
291 (void *) regs->regs[31]);
293 printk("Status: %08x ", (uint32_t) regs->cp0_status);
296 if (regs->cp0_status & ST0_KUO)
298 if (regs->cp0_status & ST0_IEO)
300 if (regs->cp0_status & ST0_KUP)
302 if (regs->cp0_status & ST0_IEP)
304 if (regs->cp0_status & ST0_KUC)
306 if (regs->cp0_status & ST0_IEC)
308 } else if (cpu_has_4kex) {
309 if (regs->cp0_status & ST0_KX)
311 if (regs->cp0_status & ST0_SX)
313 if (regs->cp0_status & ST0_UX)
315 switch (regs->cp0_status & ST0_KSU) {
320 pr_cont("SUPERVISOR ");
326 pr_cont("BAD_MODE ");
329 if (regs->cp0_status & ST0_ERL)
331 if (regs->cp0_status & ST0_EXL)
333 if (regs->cp0_status & ST0_IE)
338 exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
339 printk("Cause : %08x (ExcCode %02x)\n", cause, exccode);
341 if (1 <= exccode && exccode <= 5)
342 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
344 printk("PrId : %08x (%s)\n", read_c0_prid(),
349 * FIXME: really the generic show_regs should take a const pointer argument.
351 void show_regs(struct pt_regs *regs)
353 __show_regs((struct pt_regs *)regs);
357 void show_registers(struct pt_regs *regs)
359 const int field = 2 * sizeof(unsigned long);
360 mm_segment_t old_fs = get_fs();
364 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n",
365 current->comm, current->pid, current_thread_info(), current,
366 field, current_thread_info()->tp_value);
367 if (cpu_has_userlocal) {
370 tls = read_c0_userlocal();
371 if (tls != current_thread_info()->tp_value)
372 printk("*HwTLS: %0*lx\n", field, tls);
375 if (!user_mode(regs))
376 /* Necessary for getting the correct stack content */
378 show_stacktrace(current, regs);
379 show_code((unsigned int __user *) regs->cp0_epc);
384 static DEFINE_RAW_SPINLOCK(die_lock);
386 void __noreturn die(const char *str, struct pt_regs *regs)
388 static int die_counter;
393 if (notify_die(DIE_OOPS, str, regs, 0, current->thread.trap_nr,
394 SIGSEGV) == NOTIFY_STOP)
398 raw_spin_lock_irq(&die_lock);
401 printk("%s[#%d]:\n", str, ++die_counter);
402 show_registers(regs);
403 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
404 raw_spin_unlock_irq(&die_lock);
409 panic("Fatal exception in interrupt");
412 panic("Fatal exception");
414 if (regs && kexec_should_crash(current))
420 extern struct exception_table_entry __start___dbe_table[];
421 extern struct exception_table_entry __stop___dbe_table[];
424 " .section __dbe_table, \"a\"\n"
427 /* Given an address, look for it in the exception tables. */
428 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
430 const struct exception_table_entry *e;
432 e = search_extable(__start___dbe_table,
433 __stop___dbe_table - __start___dbe_table, addr);
435 e = search_module_dbetables(addr);
439 asmlinkage void do_be(struct pt_regs *regs)
441 const int field = 2 * sizeof(unsigned long);
442 const struct exception_table_entry *fixup = NULL;
443 int data = regs->cp0_cause & 4;
444 int action = MIPS_BE_FATAL;
445 enum ctx_state prev_state;
447 prev_state = exception_enter();
448 /* XXX For now. Fixme, this searches the wrong table ... */
449 if (data && !user_mode(regs))
450 fixup = search_dbe_tables(exception_epc(regs));
453 action = MIPS_BE_FIXUP;
455 if (board_be_handler)
456 action = board_be_handler(regs, fixup != NULL);
458 mips_cm_error_report();
461 case MIPS_BE_DISCARD:
465 regs->cp0_epc = fixup->nextinsn;
474 * Assume it would be too dangerous to continue ...
476 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
477 data ? "Data" : "Instruction",
478 field, regs->cp0_epc, field, regs->regs[31]);
479 if (notify_die(DIE_OOPS, "bus error", regs, 0, current->thread.trap_nr,
480 SIGBUS) == NOTIFY_STOP)
483 die_if_kernel("Oops", regs);
484 force_sig(SIGBUS, current);
487 exception_exit(prev_state);
491 * ll/sc, rdhwr, sync emulation
494 #define OPCODE 0xfc000000
495 #define BASE 0x03e00000
496 #define RT 0x001f0000
497 #define OFFSET 0x0000ffff
498 #define LL 0xc0000000
499 #define SC 0xe0000000
500 #define SPEC0 0x00000000
501 #define SPEC3 0x7c000000
502 #define RD 0x0000f800
503 #define FUNC 0x0000003f
504 #define SYNC 0x0000000f
505 #define RDHWR 0x0000003b
507 /* microMIPS definitions */
508 #define MM_POOL32A_FUNC 0xfc00ffff
509 #define MM_RDHWR 0x00006b3c
510 #define MM_RS 0x001f0000
511 #define MM_RT 0x03e00000
514 * The ll_bit is cleared by r*_switch.S
518 struct task_struct *ll_task;
520 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)
522 unsigned long value, __user *vaddr;
526 * analyse the ll instruction that just caused a ri exception
527 * and put the referenced address to addr.
530 /* sign extend offset */
531 offset = opcode & OFFSET;
535 vaddr = (unsigned long __user *)
536 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
538 if ((unsigned long)vaddr & 3)
540 if (get_user(value, vaddr))
545 if (ll_task == NULL || ll_task == current) {
554 regs->regs[(opcode & RT) >> 16] = value;
559 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
561 unsigned long __user *vaddr;
566 * analyse the sc instruction that just caused a ri exception
567 * and put the referenced address to addr.
570 /* sign extend offset */
571 offset = opcode & OFFSET;
575 vaddr = (unsigned long __user *)
576 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
577 reg = (opcode & RT) >> 16;
579 if ((unsigned long)vaddr & 3)
584 if (ll_bit == 0 || ll_task != current) {
592 if (put_user(regs->regs[reg], vaddr))
601 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
602 * opcodes are supposed to result in coprocessor unusable exceptions if
603 * executed on ll/sc-less processors. That's the theory. In practice a
604 * few processors such as NEC's VR4100 throw reserved instruction exceptions
605 * instead, so we're doing the emulation thing in both exception handlers.
607 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
609 if ((opcode & OPCODE) == LL) {
610 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
612 return simulate_ll(regs, opcode);
614 if ((opcode & OPCODE) == SC) {
615 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
617 return simulate_sc(regs, opcode);
620 return -1; /* Must be something else ... */
624 * Simulate trapping 'rdhwr' instructions to provide user accessible
625 * registers not implemented in hardware.
627 static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt)
629 struct thread_info *ti = task_thread_info(current);
631 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
634 case MIPS_HWR_CPUNUM: /* CPU number */
635 regs->regs[rt] = smp_processor_id();
637 case MIPS_HWR_SYNCISTEP: /* SYNCI length */
638 regs->regs[rt] = min(current_cpu_data.dcache.linesz,
639 current_cpu_data.icache.linesz);
641 case MIPS_HWR_CC: /* Read count register */
642 regs->regs[rt] = read_c0_count();
644 case MIPS_HWR_CCRES: /* Count register resolution */
645 switch (current_cpu_type()) {
654 case MIPS_HWR_ULR: /* Read UserLocal register */
655 regs->regs[rt] = ti->tp_value;
662 static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode)
664 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
665 int rd = (opcode & RD) >> 11;
666 int rt = (opcode & RT) >> 16;
668 simulate_rdhwr(regs, rd, rt);
676 static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned int opcode)
678 if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) {
679 int rd = (opcode & MM_RS) >> 16;
680 int rt = (opcode & MM_RT) >> 21;
681 simulate_rdhwr(regs, rd, rt);
689 static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
691 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) {
692 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
697 return -1; /* Must be something else ... */
700 asmlinkage void do_ov(struct pt_regs *regs)
702 enum ctx_state prev_state;
704 prev_state = exception_enter();
705 die_if_kernel("Integer overflow", regs);
707 force_sig_fault(SIGFPE, FPE_INTOVF, (void __user *)regs->cp0_epc, current);
708 exception_exit(prev_state);
712 * Send SIGFPE according to FCSR Cause bits, which must have already
713 * been masked against Enable bits. This is impotant as Inexact can
714 * happen together with Overflow or Underflow, and `ptrace' can set
717 void force_fcr31_sig(unsigned long fcr31, void __user *fault_addr,
718 struct task_struct *tsk)
720 int si_code = FPE_FLTUNK;
722 if (fcr31 & FPU_CSR_INV_X)
723 si_code = FPE_FLTINV;
724 else if (fcr31 & FPU_CSR_DIV_X)
725 si_code = FPE_FLTDIV;
726 else if (fcr31 & FPU_CSR_OVF_X)
727 si_code = FPE_FLTOVF;
728 else if (fcr31 & FPU_CSR_UDF_X)
729 si_code = FPE_FLTUND;
730 else if (fcr31 & FPU_CSR_INE_X)
731 si_code = FPE_FLTRES;
733 force_sig_fault(SIGFPE, si_code, fault_addr, tsk);
736 int process_fpemu_return(int sig, void __user *fault_addr, unsigned long fcr31)
739 struct vm_area_struct *vma;
746 force_fcr31_sig(fcr31, fault_addr, current);
750 force_sig_fault(SIGBUS, BUS_ADRERR, fault_addr, current);
754 down_read(¤t->mm->mmap_sem);
755 vma = find_vma(current->mm, (unsigned long)fault_addr);
756 if (vma && (vma->vm_start <= (unsigned long)fault_addr))
757 si_code = SEGV_ACCERR;
759 si_code = SEGV_MAPERR;
760 up_read(¤t->mm->mmap_sem);
761 force_sig_fault(SIGSEGV, si_code, fault_addr, current);
765 force_sig(sig, current);
770 static int simulate_fp(struct pt_regs *regs, unsigned int opcode,
771 unsigned long old_epc, unsigned long old_ra)
773 union mips_instruction inst = { .word = opcode };
774 void __user *fault_addr;
778 /* If it's obviously not an FP instruction, skip it */
779 switch (inst.i_format.opcode) {
793 * do_ri skipped over the instruction via compute_return_epc, undo
794 * that for the FPU emulator.
796 regs->cp0_epc = old_epc;
797 regs->regs[31] = old_ra;
799 /* Save the FP context to struct thread_struct */
802 /* Run the emulator */
803 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1,
807 * We can't allow the emulated instruction to leave any
808 * enabled Cause bits set in $fcr31.
810 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31);
811 current->thread.fpu.fcr31 &= ~fcr31;
813 /* Restore the hardware register state */
816 /* Send a signal if required. */
817 process_fpemu_return(sig, fault_addr, fcr31);
823 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
825 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
827 enum ctx_state prev_state;
828 void __user *fault_addr;
831 prev_state = exception_enter();
832 if (notify_die(DIE_FP, "FP exception", regs, 0, current->thread.trap_nr,
833 SIGFPE) == NOTIFY_STOP)
836 /* Clear FCSR.Cause before enabling interrupts */
837 write_32bit_cp1_register(CP1_STATUS, fcr31 & ~mask_fcr31_x(fcr31));
840 die_if_kernel("FP exception in kernel code", regs);
842 if (fcr31 & FPU_CSR_UNI_X) {
844 * Unimplemented operation exception. If we've got the full
845 * software emulator on-board, let's use it...
847 * Force FPU to dump state into task/thread context. We're
848 * moving a lot of data here for what is probably a single
849 * instruction, but the alternative is to pre-decode the FP
850 * register operands before invoking the emulator, which seems
851 * a bit extreme for what should be an infrequent event.
853 /* Ensure 'resume' not overwrite saved fp context again. */
856 /* Run the emulator */
857 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1,
861 * We can't allow the emulated instruction to leave any
862 * enabled Cause bits set in $fcr31.
864 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31);
865 current->thread.fpu.fcr31 &= ~fcr31;
867 /* Restore the hardware register state */
868 own_fpu(1); /* Using the FPU again. */
871 fault_addr = (void __user *) regs->cp0_epc;
874 /* Send a signal if required. */
875 process_fpemu_return(sig, fault_addr, fcr31);
878 exception_exit(prev_state);
881 void do_trap_or_bp(struct pt_regs *regs, unsigned int code, int si_code,
886 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
887 if (kgdb_ll_trap(DIE_TRAP, str, regs, code, current->thread.trap_nr,
888 SIGTRAP) == NOTIFY_STOP)
890 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
892 if (notify_die(DIE_TRAP, str, regs, code, current->thread.trap_nr,
893 SIGTRAP) == NOTIFY_STOP)
897 * A short test says that IRIX 5.3 sends SIGTRAP for all trap
898 * insns, even for trap and break codes that indicate arithmetic
899 * failures. Weird ...
900 * But should we continue the brokenness??? --macro
905 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
906 die_if_kernel(b, regs);
907 force_sig_fault(SIGFPE,
908 code == BRK_DIVZERO ? FPE_INTDIV : FPE_INTOVF,
909 (void __user *) regs->cp0_epc, current);
912 die_if_kernel("Kernel bug detected", regs);
913 force_sig(SIGTRAP, current);
917 * This breakpoint code is used by the FPU emulator to retake
918 * control of the CPU after executing the instruction from the
919 * delay slot of an emulated branch.
921 * Terminate if exception was recognized as a delay slot return
922 * otherwise handle as normal.
924 if (do_dsemulret(regs))
927 die_if_kernel("Math emu break/trap", regs);
928 force_sig(SIGTRAP, current);
931 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
932 die_if_kernel(b, regs);
934 force_sig_fault(SIGTRAP, si_code, NULL, current);
936 force_sig(SIGTRAP, current);
941 asmlinkage void do_bp(struct pt_regs *regs)
943 unsigned long epc = msk_isa16_mode(exception_epc(regs));
944 unsigned int opcode, bcode;
945 enum ctx_state prev_state;
949 if (!user_mode(regs))
952 prev_state = exception_enter();
953 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
954 if (get_isa16_mode(regs->cp0_epc)) {
957 if (__get_user(instr[0], (u16 __user *)epc))
960 if (!cpu_has_mmips) {
962 bcode = (instr[0] >> 5) & 0x3f;
963 } else if (mm_insn_16bit(instr[0])) {
964 /* 16-bit microMIPS BREAK */
965 bcode = instr[0] & 0xf;
967 /* 32-bit microMIPS BREAK */
968 if (__get_user(instr[1], (u16 __user *)(epc + 2)))
970 opcode = (instr[0] << 16) | instr[1];
971 bcode = (opcode >> 6) & ((1 << 20) - 1);
974 if (__get_user(opcode, (unsigned int __user *)epc))
976 bcode = (opcode >> 6) & ((1 << 20) - 1);
980 * There is the ancient bug in the MIPS assemblers that the break
981 * code starts left to bit 16 instead to bit 6 in the opcode.
982 * Gas is bug-compatible, but not always, grrr...
983 * We handle both cases with a simple heuristics. --macro
985 if (bcode >= (1 << 10))
986 bcode = ((bcode & ((1 << 10) - 1)) << 10) | (bcode >> 10);
989 * notify the kprobe handlers, if instruction is likely to
994 if (notify_die(DIE_UPROBE, "uprobe", regs, bcode,
995 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1000 if (notify_die(DIE_UPROBE_XOL, "uprobe_xol", regs, bcode,
1001 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1006 if (notify_die(DIE_BREAK, "debug", regs, bcode,
1007 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1011 case BRK_KPROBE_SSTEPBP:
1012 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode,
1013 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1021 do_trap_or_bp(regs, bcode, TRAP_BRKPT, "Break");
1025 exception_exit(prev_state);
1029 force_sig(SIGSEGV, current);
1033 asmlinkage void do_tr(struct pt_regs *regs)
1035 u32 opcode, tcode = 0;
1036 enum ctx_state prev_state;
1039 unsigned long epc = msk_isa16_mode(exception_epc(regs));
1042 if (!user_mode(regs))
1045 prev_state = exception_enter();
1046 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
1047 if (get_isa16_mode(regs->cp0_epc)) {
1048 if (__get_user(instr[0], (u16 __user *)(epc + 0)) ||
1049 __get_user(instr[1], (u16 __user *)(epc + 2)))
1051 opcode = (instr[0] << 16) | instr[1];
1052 /* Immediate versions don't provide a code. */
1053 if (!(opcode & OPCODE))
1054 tcode = (opcode >> 12) & ((1 << 4) - 1);
1056 if (__get_user(opcode, (u32 __user *)epc))
1058 /* Immediate versions don't provide a code. */
1059 if (!(opcode & OPCODE))
1060 tcode = (opcode >> 6) & ((1 << 10) - 1);
1063 do_trap_or_bp(regs, tcode, 0, "Trap");
1067 exception_exit(prev_state);
1071 force_sig(SIGSEGV, current);
1075 asmlinkage void do_ri(struct pt_regs *regs)
1077 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs);
1078 unsigned long old_epc = regs->cp0_epc;
1079 unsigned long old31 = regs->regs[31];
1080 enum ctx_state prev_state;
1081 unsigned int opcode = 0;
1085 * Avoid any kernel code. Just emulate the R2 instruction
1086 * as quickly as possible.
1088 if (mipsr2_emulation && cpu_has_mips_r6 &&
1089 likely(user_mode(regs)) &&
1090 likely(get_user(opcode, epc) >= 0)) {
1091 unsigned long fcr31 = 0;
1093 status = mipsr2_decoder(regs, opcode, &fcr31);
1101 process_fpemu_return(status,
1102 ¤t->thread.cp0_baduaddr,
1110 prev_state = exception_enter();
1111 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
1113 if (notify_die(DIE_RI, "RI Fault", regs, 0, current->thread.trap_nr,
1114 SIGILL) == NOTIFY_STOP)
1117 die_if_kernel("Reserved instruction in kernel code", regs);
1119 if (unlikely(compute_return_epc(regs) < 0))
1122 if (!get_isa16_mode(regs->cp0_epc)) {
1123 if (unlikely(get_user(opcode, epc) < 0))
1126 if (!cpu_has_llsc && status < 0)
1127 status = simulate_llsc(regs, opcode);
1130 status = simulate_rdhwr_normal(regs, opcode);
1133 status = simulate_sync(regs, opcode);
1136 status = simulate_fp(regs, opcode, old_epc, old31);
1137 } else if (cpu_has_mmips) {
1138 unsigned short mmop[2] = { 0 };
1140 if (unlikely(get_user(mmop[0], (u16 __user *)epc + 0) < 0))
1142 if (unlikely(get_user(mmop[1], (u16 __user *)epc + 1) < 0))
1145 opcode = (opcode << 16) | mmop[1];
1148 status = simulate_rdhwr_mm(regs, opcode);
1154 if (unlikely(status > 0)) {
1155 regs->cp0_epc = old_epc; /* Undo skip-over. */
1156 regs->regs[31] = old31;
1157 force_sig(status, current);
1161 exception_exit(prev_state);
1165 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
1166 * emulated more than some threshold number of instructions, force migration to
1167 * a "CPU" that has FP support.
1169 static void mt_ase_fp_affinity(void)
1171 #ifdef CONFIG_MIPS_MT_FPAFF
1172 if (mt_fpemul_threshold > 0 &&
1173 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) {
1175 * If there's no FPU present, or if the application has already
1176 * restricted the allowed set to exclude any CPUs with FPUs,
1177 * we'll skip the procedure.
1179 if (cpumask_intersects(¤t->cpus_allowed, &mt_fpu_cpumask)) {
1182 current->thread.user_cpus_allowed
1183 = current->cpus_allowed;
1184 cpumask_and(&tmask, ¤t->cpus_allowed,
1186 set_cpus_allowed_ptr(current, &tmask);
1187 set_thread_flag(TIF_FPUBOUND);
1190 #endif /* CONFIG_MIPS_MT_FPAFF */
1194 * No lock; only written during early bootup by CPU 0.
1196 static RAW_NOTIFIER_HEAD(cu2_chain);
1198 int __ref register_cu2_notifier(struct notifier_block *nb)
1200 return raw_notifier_chain_register(&cu2_chain, nb);
1203 int cu2_notifier_call_chain(unsigned long val, void *v)
1205 return raw_notifier_call_chain(&cu2_chain, val, v);
1208 static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
1211 struct pt_regs *regs = data;
1213 die_if_kernel("COP2: Unhandled kernel unaligned access or invalid "
1214 "instruction", regs);
1215 force_sig(SIGILL, current);
1220 static int enable_restore_fp_context(int msa)
1222 int err, was_fpu_owner, prior_msa;
1225 /* First time FP context user. */
1231 set_thread_flag(TIF_USEDMSA);
1232 set_thread_flag(TIF_MSA_CTX_LIVE);
1241 * This task has formerly used the FP context.
1243 * If this thread has no live MSA vector context then we can simply
1244 * restore the scalar FP context. If it has live MSA vector context
1245 * (that is, it has or may have used MSA since last performing a
1246 * function call) then we'll need to restore the vector context. This
1247 * applies even if we're currently only executing a scalar FP
1248 * instruction. This is because if we were to later execute an MSA
1249 * instruction then we'd either have to:
1251 * - Restore the vector context & clobber any registers modified by
1252 * scalar FP instructions between now & then.
1256 * - Not restore the vector context & lose the most significant bits
1257 * of all vector registers.
1259 * Neither of those options is acceptable. We cannot restore the least
1260 * significant bits of the registers now & only restore the most
1261 * significant bits later because the most significant bits of any
1262 * vector registers whose aliased FP register is modified now will have
1263 * been zeroed. We'd have no way to know that when restoring the vector
1264 * context & thus may load an outdated value for the most significant
1265 * bits of a vector register.
1267 if (!msa && !thread_msa_context_live())
1271 * This task is using or has previously used MSA. Thus we require
1272 * that Status.FR == 1.
1275 was_fpu_owner = is_fpu_owner();
1276 err = own_fpu_inatomic(0);
1281 write_msa_csr(current->thread.fpu.msacsr);
1282 set_thread_flag(TIF_USEDMSA);
1285 * If this is the first time that the task is using MSA and it has
1286 * previously used scalar FP in this time slice then we already nave
1287 * FP context which we shouldn't clobber. We do however need to clear
1288 * the upper 64b of each vector register so that this task has no
1289 * opportunity to see data left behind by another.
1291 prior_msa = test_and_set_thread_flag(TIF_MSA_CTX_LIVE);
1292 if (!prior_msa && was_fpu_owner) {
1300 * Restore the least significant 64b of each vector register
1301 * from the existing scalar FP context.
1303 _restore_fp(current);
1306 * The task has not formerly used MSA, so clear the upper 64b
1307 * of each vector register such that it cannot see data left
1308 * behind by another task.
1312 /* We need to restore the vector context. */
1313 restore_msa(current);
1315 /* Restore the scalar FP control & status register */
1317 write_32bit_cp1_register(CP1_STATUS,
1318 current->thread.fpu.fcr31);
1327 asmlinkage void do_cpu(struct pt_regs *regs)
1329 enum ctx_state prev_state;
1330 unsigned int __user *epc;
1331 unsigned long old_epc, old31;
1332 void __user *fault_addr;
1333 unsigned int opcode;
1334 unsigned long fcr31;
1339 prev_state = exception_enter();
1340 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
1343 die_if_kernel("do_cpu invoked from kernel context!", regs);
1347 epc = (unsigned int __user *)exception_epc(regs);
1348 old_epc = regs->cp0_epc;
1349 old31 = regs->regs[31];
1353 if (unlikely(compute_return_epc(regs) < 0))
1356 if (!get_isa16_mode(regs->cp0_epc)) {
1357 if (unlikely(get_user(opcode, epc) < 0))
1360 if (!cpu_has_llsc && status < 0)
1361 status = simulate_llsc(regs, opcode);
1367 if (unlikely(status > 0)) {
1368 regs->cp0_epc = old_epc; /* Undo skip-over. */
1369 regs->regs[31] = old31;
1370 force_sig(status, current);
1377 * The COP3 opcode space and consequently the CP0.Status.CU3
1378 * bit and the CP0.Cause.CE=3 encoding have been removed as
1379 * of the MIPS III ISA. From the MIPS IV and MIPS32r2 ISAs
1380 * up the space has been reused for COP1X instructions, that
1381 * are enabled by the CP0.Status.CU1 bit and consequently
1382 * use the CP0.Cause.CE=1 encoding for Coprocessor Unusable
1383 * exceptions. Some FPU-less processors that implement one
1384 * of these ISAs however use this code erroneously for COP1X
1385 * instructions. Therefore we redirect this trap to the FP
1388 if (raw_cpu_has_fpu || !cpu_has_mips_4_5_64_r2_r6) {
1389 force_sig(SIGILL, current);
1395 err = enable_restore_fp_context(0);
1397 if (raw_cpu_has_fpu && !err)
1400 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 0,
1404 * We can't allow the emulated instruction to leave
1405 * any enabled Cause bits set in $fcr31.
1407 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31);
1408 current->thread.fpu.fcr31 &= ~fcr31;
1410 /* Send a signal if required. */
1411 if (!process_fpemu_return(sig, fault_addr, fcr31) && !err)
1412 mt_ase_fp_affinity();
1417 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
1421 exception_exit(prev_state);
1424 asmlinkage void do_msa_fpe(struct pt_regs *regs, unsigned int msacsr)
1426 enum ctx_state prev_state;
1428 prev_state = exception_enter();
1429 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
1430 if (notify_die(DIE_MSAFP, "MSA FP exception", regs, 0,
1431 current->thread.trap_nr, SIGFPE) == NOTIFY_STOP)
1434 /* Clear MSACSR.Cause before enabling interrupts */
1435 write_msa_csr(msacsr & ~MSA_CSR_CAUSEF);
1438 die_if_kernel("do_msa_fpe invoked from kernel context!", regs);
1439 force_sig(SIGFPE, current);
1441 exception_exit(prev_state);
1444 asmlinkage void do_msa(struct pt_regs *regs)
1446 enum ctx_state prev_state;
1449 prev_state = exception_enter();
1451 if (!cpu_has_msa || test_thread_flag(TIF_32BIT_FPREGS)) {
1452 force_sig(SIGILL, current);
1456 die_if_kernel("do_msa invoked from kernel context!", regs);
1458 err = enable_restore_fp_context(1);
1460 force_sig(SIGILL, current);
1462 exception_exit(prev_state);
1465 asmlinkage void do_mdmx(struct pt_regs *regs)
1467 enum ctx_state prev_state;
1469 prev_state = exception_enter();
1470 force_sig(SIGILL, current);
1471 exception_exit(prev_state);
1475 * Called with interrupts disabled.
1477 asmlinkage void do_watch(struct pt_regs *regs)
1479 enum ctx_state prev_state;
1481 prev_state = exception_enter();
1483 * Clear WP (bit 22) bit of cause register so we don't loop
1486 clear_c0_cause(CAUSEF_WP);
1489 * If the current thread has the watch registers loaded, save
1490 * their values and send SIGTRAP. Otherwise another thread
1491 * left the registers set, clear them and continue.
1493 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
1494 mips_read_watch_registers();
1496 force_sig_fault(SIGTRAP, TRAP_HWBKPT, NULL, current);
1498 mips_clear_watch_registers();
1501 exception_exit(prev_state);
1504 asmlinkage void do_mcheck(struct pt_regs *regs)
1506 int multi_match = regs->cp0_status & ST0_TS;
1507 enum ctx_state prev_state;
1508 mm_segment_t old_fs = get_fs();
1510 prev_state = exception_enter();
1519 if (!user_mode(regs))
1522 show_code((unsigned int __user *) regs->cp0_epc);
1527 * Some chips may have other causes of machine check (e.g. SB1
1530 panic("Caught Machine Check exception - %scaused by multiple "
1531 "matching entries in the TLB.",
1532 (multi_match) ? "" : "not ");
1535 asmlinkage void do_mt(struct pt_regs *regs)
1539 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
1540 >> VPECONTROL_EXCPT_SHIFT;
1543 printk(KERN_DEBUG "Thread Underflow\n");
1546 printk(KERN_DEBUG "Thread Overflow\n");
1549 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
1552 printk(KERN_DEBUG "Gating Storage Exception\n");
1555 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
1558 printk(KERN_DEBUG "Gating Storage Scheduler Exception\n");
1561 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
1565 die_if_kernel("MIPS MT Thread exception in kernel", regs);
1567 force_sig(SIGILL, current);
1571 asmlinkage void do_dsp(struct pt_regs *regs)
1574 panic("Unexpected DSP exception");
1576 force_sig(SIGILL, current);
1579 asmlinkage void do_reserved(struct pt_regs *regs)
1582 * Game over - no way to handle this if it ever occurs. Most probably
1583 * caused by a new unknown cpu type or after another deadly
1584 * hard/software error.
1587 panic("Caught reserved exception %ld - should not happen.",
1588 (regs->cp0_cause & 0x7f) >> 2);
1591 static int __initdata l1parity = 1;
1592 static int __init nol1parity(char *s)
1597 __setup("nol1par", nol1parity);
1598 static int __initdata l2parity = 1;
1599 static int __init nol2parity(char *s)
1604 __setup("nol2par", nol2parity);
1607 * Some MIPS CPUs can enable/disable for cache parity detection, but do
1608 * it different ways.
1610 static inline void parity_protection_init(void)
1612 #define ERRCTL_PE 0x80000000
1613 #define ERRCTL_L2P 0x00800000
1615 if (mips_cm_revision() >= CM_REV_CM3) {
1616 ulong gcr_ectl, cp0_ectl;
1619 * With CM3 systems we need to ensure that the L1 & L2
1620 * parity enables are set to the same value, since this
1621 * is presumed by the hardware engineers.
1623 * If the user disabled either of L1 or L2 ECC checking,
1626 l1parity &= l2parity;
1627 l2parity &= l1parity;
1629 /* Probe L1 ECC support */
1630 cp0_ectl = read_c0_ecc();
1631 write_c0_ecc(cp0_ectl | ERRCTL_PE);
1632 back_to_back_c0_hazard();
1633 cp0_ectl = read_c0_ecc();
1635 /* Probe L2 ECC support */
1636 gcr_ectl = read_gcr_err_control();
1638 if (!(gcr_ectl & CM_GCR_ERR_CONTROL_L2_ECC_SUPPORT) ||
1639 !(cp0_ectl & ERRCTL_PE)) {
1641 * One of L1 or L2 ECC checking isn't supported,
1642 * so we cannot enable either.
1644 l1parity = l2parity = 0;
1647 /* Configure L1 ECC checking */
1649 cp0_ectl |= ERRCTL_PE;
1651 cp0_ectl &= ~ERRCTL_PE;
1652 write_c0_ecc(cp0_ectl);
1653 back_to_back_c0_hazard();
1654 WARN_ON(!!(read_c0_ecc() & ERRCTL_PE) != l1parity);
1656 /* Configure L2 ECC checking */
1658 gcr_ectl |= CM_GCR_ERR_CONTROL_L2_ECC_EN;
1660 gcr_ectl &= ~CM_GCR_ERR_CONTROL_L2_ECC_EN;
1661 write_gcr_err_control(gcr_ectl);
1662 gcr_ectl = read_gcr_err_control();
1663 gcr_ectl &= CM_GCR_ERR_CONTROL_L2_ECC_EN;
1664 WARN_ON(!!gcr_ectl != l2parity);
1666 pr_info("Cache parity protection %sabled\n",
1667 l1parity ? "en" : "dis");
1671 switch (current_cpu_type()) {
1677 case CPU_INTERAPTIV:
1680 case CPU_QEMU_GENERIC:
1683 unsigned long errctl;
1684 unsigned int l1parity_present, l2parity_present;
1686 errctl = read_c0_ecc();
1687 errctl &= ~(ERRCTL_PE|ERRCTL_L2P);
1689 /* probe L1 parity support */
1690 write_c0_ecc(errctl | ERRCTL_PE);
1691 back_to_back_c0_hazard();
1692 l1parity_present = (read_c0_ecc() & ERRCTL_PE);
1694 /* probe L2 parity support */
1695 write_c0_ecc(errctl|ERRCTL_L2P);
1696 back_to_back_c0_hazard();
1697 l2parity_present = (read_c0_ecc() & ERRCTL_L2P);
1699 if (l1parity_present && l2parity_present) {
1701 errctl |= ERRCTL_PE;
1702 if (l1parity ^ l2parity)
1703 errctl |= ERRCTL_L2P;
1704 } else if (l1parity_present) {
1706 errctl |= ERRCTL_PE;
1707 } else if (l2parity_present) {
1709 errctl |= ERRCTL_L2P;
1711 /* No parity available */
1714 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl);
1716 write_c0_ecc(errctl);
1717 back_to_back_c0_hazard();
1718 errctl = read_c0_ecc();
1719 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl);
1721 if (l1parity_present)
1722 printk(KERN_INFO "Cache parity protection %sabled\n",
1723 (errctl & ERRCTL_PE) ? "en" : "dis");
1725 if (l2parity_present) {
1726 if (l1parity_present && l1parity)
1727 errctl ^= ERRCTL_L2P;
1728 printk(KERN_INFO "L2 cache parity protection %sabled\n",
1729 (errctl & ERRCTL_L2P) ? "en" : "dis");
1737 write_c0_ecc(0x80000000);
1738 back_to_back_c0_hazard();
1739 /* Set the PE bit (bit 31) in the c0_errctl register. */
1740 printk(KERN_INFO "Cache parity protection %sabled\n",
1741 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
1745 /* Clear the DE bit (bit 16) in the c0_status register. */
1746 printk(KERN_INFO "Enable cache parity protection for "
1747 "MIPS 20KC/25KF CPUs.\n");
1748 clear_c0_status(ST0_DE);
1755 asmlinkage void cache_parity_error(void)
1757 const int field = 2 * sizeof(unsigned long);
1758 unsigned int reg_val;
1760 /* For the moment, report the problem and hang. */
1761 printk("Cache error exception:\n");
1762 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1763 reg_val = read_c0_cacheerr();
1764 printk("c0_cacheerr == %08x\n", reg_val);
1766 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1767 reg_val & (1<<30) ? "secondary" : "primary",
1768 reg_val & (1<<31) ? "data" : "insn");
1769 if ((cpu_has_mips_r2_r6) &&
1770 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) {
1771 pr_err("Error bits: %s%s%s%s%s%s%s%s\n",
1772 reg_val & (1<<29) ? "ED " : "",
1773 reg_val & (1<<28) ? "ET " : "",
1774 reg_val & (1<<27) ? "ES " : "",
1775 reg_val & (1<<26) ? "EE " : "",
1776 reg_val & (1<<25) ? "EB " : "",
1777 reg_val & (1<<24) ? "EI " : "",
1778 reg_val & (1<<23) ? "E1 " : "",
1779 reg_val & (1<<22) ? "E0 " : "");
1781 pr_err("Error bits: %s%s%s%s%s%s%s\n",
1782 reg_val & (1<<29) ? "ED " : "",
1783 reg_val & (1<<28) ? "ET " : "",
1784 reg_val & (1<<26) ? "EE " : "",
1785 reg_val & (1<<25) ? "EB " : "",
1786 reg_val & (1<<24) ? "EI " : "",
1787 reg_val & (1<<23) ? "E1 " : "",
1788 reg_val & (1<<22) ? "E0 " : "");
1790 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1792 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1793 if (reg_val & (1<<22))
1794 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1796 if (reg_val & (1<<23))
1797 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1800 panic("Can't handle the cache error!");
1803 asmlinkage void do_ftlb(void)
1805 const int field = 2 * sizeof(unsigned long);
1806 unsigned int reg_val;
1808 /* For the moment, report the problem and hang. */
1809 if ((cpu_has_mips_r2_r6) &&
1810 (((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS) ||
1811 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_LOONGSON))) {
1812 pr_err("FTLB error exception, cp0_ecc=0x%08x:\n",
1814 pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1815 reg_val = read_c0_cacheerr();
1816 pr_err("c0_cacheerr == %08x\n", reg_val);
1818 if ((reg_val & 0xc0000000) == 0xc0000000) {
1819 pr_err("Decoded c0_cacheerr: FTLB parity error\n");
1821 pr_err("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1822 reg_val & (1<<30) ? "secondary" : "primary",
1823 reg_val & (1<<31) ? "data" : "insn");
1826 pr_err("FTLB error exception\n");
1828 /* Just print the cacheerr bits for now */
1829 cache_parity_error();
1833 * SDBBP EJTAG debug exception handler.
1834 * We skip the instruction and return to the next instruction.
1836 void ejtag_exception_handler(struct pt_regs *regs)
1838 const int field = 2 * sizeof(unsigned long);
1839 unsigned long depc, old_epc, old_ra;
1842 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1843 depc = read_c0_depc();
1844 debug = read_c0_debug();
1845 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
1846 if (debug & 0x80000000) {
1848 * In branch delay slot.
1849 * We cheat a little bit here and use EPC to calculate the
1850 * debug return address (DEPC). EPC is restored after the
1853 old_epc = regs->cp0_epc;
1854 old_ra = regs->regs[31];
1855 regs->cp0_epc = depc;
1856 compute_return_epc(regs);
1857 depc = regs->cp0_epc;
1858 regs->cp0_epc = old_epc;
1859 regs->regs[31] = old_ra;
1862 write_c0_depc(depc);
1865 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1866 write_c0_debug(debug | 0x100);
1871 * NMI exception handler.
1872 * No lock; only written during early bootup by CPU 0.
1874 static RAW_NOTIFIER_HEAD(nmi_chain);
1876 int register_nmi_notifier(struct notifier_block *nb)
1878 return raw_notifier_chain_register(&nmi_chain, nb);
1881 void __noreturn nmi_exception_handler(struct pt_regs *regs)
1886 raw_notifier_call_chain(&nmi_chain, 0, regs);
1888 snprintf(str, 100, "CPU%d NMI taken, CP0_EPC=%lx\n",
1889 smp_processor_id(), regs->cp0_epc);
1890 regs->cp0_epc = read_c0_errorepc();
1895 #define VECTORSPACING 0x100 /* for EI/VI mode */
1897 unsigned long ebase;
1898 EXPORT_SYMBOL_GPL(ebase);
1899 unsigned long exception_handlers[32];
1900 unsigned long vi_handlers[64];
1902 void __init *set_except_vector(int n, void *addr)
1904 unsigned long handler = (unsigned long) addr;
1905 unsigned long old_handler;
1907 #ifdef CONFIG_CPU_MICROMIPS
1909 * Only the TLB handlers are cache aligned with an even
1910 * address. All other handlers are on an odd address and
1911 * require no modification. Otherwise, MIPS32 mode will
1912 * be entered when handling any TLB exceptions. That
1913 * would be bad...since we must stay in microMIPS mode.
1915 if (!(handler & 0x1))
1918 old_handler = xchg(&exception_handlers[n], handler);
1920 if (n == 0 && cpu_has_divec) {
1921 #ifdef CONFIG_CPU_MICROMIPS
1922 unsigned long jump_mask = ~((1 << 27) - 1);
1924 unsigned long jump_mask = ~((1 << 28) - 1);
1926 u32 *buf = (u32 *)(ebase + 0x200);
1927 unsigned int k0 = 26;
1928 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) {
1929 uasm_i_j(&buf, handler & ~jump_mask);
1932 UASM_i_LA(&buf, k0, handler);
1933 uasm_i_jr(&buf, k0);
1936 local_flush_icache_range(ebase + 0x200, (unsigned long)buf);
1938 return (void *)old_handler;
1941 static void do_default_vi(void)
1943 show_regs(get_irq_regs());
1944 panic("Caught unexpected vectored interrupt.");
1947 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1949 unsigned long handler;
1950 unsigned long old_handler = vi_handlers[n];
1951 int srssets = current_cpu_data.srsets;
1955 BUG_ON(!cpu_has_veic && !cpu_has_vint);
1958 handler = (unsigned long) do_default_vi;
1961 handler = (unsigned long) addr;
1962 vi_handlers[n] = handler;
1964 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1967 panic("Shadow register set %d not supported", srs);
1970 if (board_bind_eic_interrupt)
1971 board_bind_eic_interrupt(n, srs);
1972 } else if (cpu_has_vint) {
1973 /* SRSMap is only defined if shadow sets are implemented */
1975 change_c0_srsmap(0xf << n*4, srs << n*4);
1980 * If no shadow set is selected then use the default handler
1981 * that does normal register saving and standard interrupt exit
1983 extern char except_vec_vi, except_vec_vi_lui;
1984 extern char except_vec_vi_ori, except_vec_vi_end;
1985 extern char rollback_except_vec_vi;
1986 char *vec_start = using_rollback_handler() ?
1987 &rollback_except_vec_vi : &except_vec_vi;
1988 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
1989 const int lui_offset = &except_vec_vi_lui - vec_start + 2;
1990 const int ori_offset = &except_vec_vi_ori - vec_start + 2;
1992 const int lui_offset = &except_vec_vi_lui - vec_start;
1993 const int ori_offset = &except_vec_vi_ori - vec_start;
1995 const int handler_len = &except_vec_vi_end - vec_start;
1997 if (handler_len > VECTORSPACING) {
1999 * Sigh... panicing won't help as the console
2000 * is probably not configured :(
2002 panic("VECTORSPACING too small");
2005 set_handler(((unsigned long)b - ebase), vec_start,
2006 #ifdef CONFIG_CPU_MICROMIPS
2011 h = (u16 *)(b + lui_offset);
2012 *h = (handler >> 16) & 0xffff;
2013 h = (u16 *)(b + ori_offset);
2014 *h = (handler & 0xffff);
2015 local_flush_icache_range((unsigned long)b,
2016 (unsigned long)(b+handler_len));
2020 * In other cases jump directly to the interrupt handler. It
2021 * is the handler's responsibility to save registers if required
2022 * (eg hi/lo) and return from the exception using "eret".
2028 #ifdef CONFIG_CPU_MICROMIPS
2029 insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1);
2031 insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2);
2033 h[0] = (insn >> 16) & 0xffff;
2034 h[1] = insn & 0xffff;
2037 local_flush_icache_range((unsigned long)b,
2038 (unsigned long)(b+8));
2041 return (void *)old_handler;
2044 void *set_vi_handler(int n, vi_handler_t addr)
2046 return set_vi_srs_handler(n, addr, 0);
2049 extern void tlb_init(void);
2054 int cp0_compare_irq;
2055 EXPORT_SYMBOL_GPL(cp0_compare_irq);
2056 int cp0_compare_irq_shift;
2059 * Performance counter IRQ or -1 if shared with timer
2061 int cp0_perfcount_irq;
2062 EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
2065 * Fast debug channel IRQ or -1 if not present
2068 EXPORT_SYMBOL_GPL(cp0_fdc_irq);
2072 static int __init ulri_disable(char *s)
2074 pr_info("Disabling ulri\n");
2079 __setup("noulri", ulri_disable);
2081 /* configure STATUS register */
2082 static void configure_status(void)
2085 * Disable coprocessors and select 32-bit or 64-bit addressing
2086 * and the 16/32 or 32/32 FPR register model. Reset the BEV
2087 * flag that some firmware may have left set and the TS bit (for
2088 * IP27). Set XX for ISA IV code to work.
2090 unsigned int status_set = ST0_CU0;
2092 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
2094 if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV)
2095 status_set |= ST0_XX;
2097 status_set |= ST0_MX;
2099 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
2103 unsigned int hwrena;
2104 EXPORT_SYMBOL_GPL(hwrena);
2106 /* configure HWRENA register */
2107 static void configure_hwrena(void)
2109 hwrena = cpu_hwrena_impl_bits;
2111 if (cpu_has_mips_r2_r6)
2112 hwrena |= MIPS_HWRENA_CPUNUM |
2113 MIPS_HWRENA_SYNCISTEP |
2117 if (!noulri && cpu_has_userlocal)
2118 hwrena |= MIPS_HWRENA_ULR;
2121 write_c0_hwrena(hwrena);
2124 static void configure_exception_vector(void)
2126 if (cpu_has_veic || cpu_has_vint) {
2127 unsigned long sr = set_c0_status(ST0_BEV);
2128 /* If available, use WG to set top bits of EBASE */
2129 if (cpu_has_ebase_wg) {
2131 write_c0_ebase_64(ebase | MIPS_EBASE_WG);
2133 write_c0_ebase(ebase | MIPS_EBASE_WG);
2136 write_c0_ebase(ebase);
2137 write_c0_status(sr);
2138 /* Setting vector spacing enables EI/VI mode */
2139 change_c0_intctl(0x3e0, VECTORSPACING);
2141 if (cpu_has_divec) {
2142 if (cpu_has_mipsmt) {
2143 unsigned int vpflags = dvpe();
2144 set_c0_cause(CAUSEF_IV);
2147 set_c0_cause(CAUSEF_IV);
2151 void per_cpu_trap_init(bool is_boot_cpu)
2153 unsigned int cpu = smp_processor_id();
2158 configure_exception_vector();
2161 * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
2163 * o read IntCtl.IPTI to determine the timer interrupt
2164 * o read IntCtl.IPPCI to determine the performance counter interrupt
2165 * o read IntCtl.IPFDC to determine the fast debug channel interrupt
2167 if (cpu_has_mips_r2_r6) {
2169 * We shouldn't trust a secondary core has a sane EBASE register
2170 * so use the one calculated by the boot CPU.
2173 /* If available, use WG to set top bits of EBASE */
2174 if (cpu_has_ebase_wg) {
2176 write_c0_ebase_64(ebase | MIPS_EBASE_WG);
2178 write_c0_ebase(ebase | MIPS_EBASE_WG);
2181 write_c0_ebase(ebase);
2184 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
2185 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
2186 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
2187 cp0_fdc_irq = (read_c0_intctl() >> INTCTLB_IPFDC) & 7;
2192 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
2193 cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ;
2194 cp0_perfcount_irq = -1;
2198 if (!cpu_data[cpu].asid_cache)
2199 cpu_data[cpu].asid_cache = asid_first_version(cpu);
2202 current->active_mm = &init_mm;
2203 BUG_ON(current->mm);
2204 enter_lazy_tlb(&init_mm, current);
2206 /* Boot CPU's cache setup in setup_arch(). */
2210 TLBMISS_HANDLER_SETUP();
2213 /* Install CPU exception handler */
2214 void set_handler(unsigned long offset, void *addr, unsigned long size)
2216 #ifdef CONFIG_CPU_MICROMIPS
2217 memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size);
2219 memcpy((void *)(ebase + offset), addr, size);
2221 local_flush_icache_range(ebase + offset, ebase + offset + size);
2224 static const char panic_null_cerr[] =
2225 "Trying to set NULL cache error exception handler\n";
2228 * Install uncached CPU exception handler.
2229 * This is suitable only for the cache error exception which is the only
2230 * exception handler that is being run uncached.
2232 void set_uncached_handler(unsigned long offset, void *addr,
2235 unsigned long uncached_ebase = CKSEG1ADDR(ebase);
2238 panic(panic_null_cerr);
2240 memcpy((void *)(uncached_ebase + offset), addr, size);
2243 static int __initdata rdhwr_noopt;
2244 static int __init set_rdhwr_noopt(char *str)
2250 __setup("rdhwr_noopt", set_rdhwr_noopt);
2252 void __init trap_init(void)
2254 extern char except_vec3_generic;
2255 extern char except_vec4;
2256 extern char except_vec3_r4000;
2261 if (cpu_has_veic || cpu_has_vint) {
2262 unsigned long size = 0x200 + VECTORSPACING*64;
2263 phys_addr_t ebase_pa;
2265 ebase = (unsigned long)
2266 __alloc_bootmem(size, 1 << fls(size), 0);
2269 * Try to ensure ebase resides in KSeg0 if possible.
2271 * It shouldn't generally be in XKPhys on MIPS64 to avoid
2272 * hitting a poorly defined exception base for Cache Errors.
2273 * The allocation is likely to be in the low 512MB of physical,
2274 * in which case we should be able to convert to KSeg0.
2276 * EVA is special though as it allows segments to be rearranged
2277 * and to become uncached during cache error handling.
2279 ebase_pa = __pa(ebase);
2280 if (!IS_ENABLED(CONFIG_EVA) && !WARN_ON(ebase_pa >= 0x20000000))
2281 ebase = CKSEG0ADDR(ebase_pa);
2285 if (cpu_has_mips_r2_r6) {
2286 if (cpu_has_ebase_wg) {
2288 ebase = (read_c0_ebase_64() & ~0xfff);
2290 ebase = (read_c0_ebase() & ~0xfff);
2293 ebase += (read_c0_ebase() & 0x3ffff000);
2298 if (cpu_has_mmips) {
2299 unsigned int config3 = read_c0_config3();
2301 if (IS_ENABLED(CONFIG_CPU_MICROMIPS))
2302 write_c0_config3(config3 | MIPS_CONF3_ISA_OE);
2304 write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE);
2307 if (board_ebase_setup)
2308 board_ebase_setup();
2309 per_cpu_trap_init(true);
2312 * Copy the generic exception handlers to their final destination.
2313 * This will be overridden later as suitable for a particular
2316 set_handler(0x180, &except_vec3_generic, 0x80);
2319 * Setup default vectors
2321 for (i = 0; i <= 31; i++)
2322 set_except_vector(i, handle_reserved);
2325 * Copy the EJTAG debug exception vector handler code to it's final
2328 if (cpu_has_ejtag && board_ejtag_handler_setup)
2329 board_ejtag_handler_setup();
2332 * Only some CPUs have the watch exceptions.
2335 set_except_vector(EXCCODE_WATCH, handle_watch);
2338 * Initialise interrupt handlers
2340 if (cpu_has_veic || cpu_has_vint) {
2341 int nvec = cpu_has_veic ? 64 : 8;
2342 for (i = 0; i < nvec; i++)
2343 set_vi_handler(i, NULL);
2345 else if (cpu_has_divec)
2346 set_handler(0x200, &except_vec4, 0x8);
2349 * Some CPUs can enable/disable for cache parity detection, but does
2350 * it different ways.
2352 parity_protection_init();
2355 * The Data Bus Errors / Instruction Bus Errors are signaled
2356 * by external hardware. Therefore these two exceptions
2357 * may have board specific handlers.
2362 set_except_vector(EXCCODE_INT, using_rollback_handler() ?
2363 rollback_handle_int : handle_int);
2364 set_except_vector(EXCCODE_MOD, handle_tlbm);
2365 set_except_vector(EXCCODE_TLBL, handle_tlbl);
2366 set_except_vector(EXCCODE_TLBS, handle_tlbs);
2368 set_except_vector(EXCCODE_ADEL, handle_adel);
2369 set_except_vector(EXCCODE_ADES, handle_ades);
2371 set_except_vector(EXCCODE_IBE, handle_ibe);
2372 set_except_vector(EXCCODE_DBE, handle_dbe);
2374 set_except_vector(EXCCODE_SYS, handle_sys);
2375 set_except_vector(EXCCODE_BP, handle_bp);
2378 set_except_vector(EXCCODE_RI, handle_ri);
2380 if (cpu_has_vtag_icache)
2381 set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp);
2382 else if (current_cpu_type() == CPU_LOONGSON3)
2383 set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp);
2385 set_except_vector(EXCCODE_RI, handle_ri_rdhwr);
2388 set_except_vector(EXCCODE_CPU, handle_cpu);
2389 set_except_vector(EXCCODE_OV, handle_ov);
2390 set_except_vector(EXCCODE_TR, handle_tr);
2391 set_except_vector(EXCCODE_MSAFPE, handle_msa_fpe);
2393 if (board_nmi_handler_setup)
2394 board_nmi_handler_setup();
2396 if (cpu_has_fpu && !cpu_has_nofpuex)
2397 set_except_vector(EXCCODE_FPE, handle_fpe);
2399 set_except_vector(MIPS_EXCCODE_TLBPAR, handle_ftlb);
2401 if (cpu_has_rixiex) {
2402 set_except_vector(EXCCODE_TLBRI, tlb_do_page_fault_0);
2403 set_except_vector(EXCCODE_TLBXI, tlb_do_page_fault_0);
2406 set_except_vector(EXCCODE_MSADIS, handle_msa);
2407 set_except_vector(EXCCODE_MDMX, handle_mdmx);
2410 set_except_vector(EXCCODE_MCHECK, handle_mcheck);
2413 set_except_vector(EXCCODE_THREAD, handle_mt);
2415 set_except_vector(EXCCODE_DSPDIS, handle_dsp);
2417 if (board_cache_error_setup)
2418 board_cache_error_setup();
2421 /* Special exception: R4[04]00 uses also the divec space. */
2422 set_handler(0x180, &except_vec3_r4000, 0x100);
2423 else if (cpu_has_4kex)
2424 set_handler(0x180, &except_vec3_generic, 0x80);
2426 set_handler(0x080, &except_vec3_generic, 0x80);
2428 local_flush_icache_range(ebase, ebase + 0x400);
2430 sort_extable(__start___dbe_table, __stop___dbe_table);
2432 cu2_notifier(default_cu2_call, 0x80000000); /* Run last */
2435 static int trap_pm_notifier(struct notifier_block *self, unsigned long cmd,
2439 case CPU_PM_ENTER_FAILED:
2443 configure_exception_vector();
2445 /* Restore register with CPU number for TLB handlers */
2446 TLBMISS_HANDLER_RESTORE();
2454 static struct notifier_block trap_pm_notifier_block = {
2455 .notifier_call = trap_pm_notifier,
2458 static int __init trap_pm_init(void)
2460 return cpu_pm_register_notifier(&trap_pm_notifier_block);
2462 arch_initcall(trap_pm_init);