2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
12 * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved.
13 * Copyright (C) 2014, Imagination Technologies Ltd.
15 #include <linux/bitops.h>
16 #include <linux/bug.h>
17 #include <linux/compiler.h>
18 #include <linux/context_tracking.h>
19 #include <linux/cpu_pm.h>
20 #include <linux/kexec.h>
21 #include <linux/init.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
25 #include <linux/sched.h>
26 #include <linux/smp.h>
27 #include <linux/spinlock.h>
28 #include <linux/kallsyms.h>
29 #include <linux/bootmem.h>
30 #include <linux/interrupt.h>
31 #include <linux/ptrace.h>
32 #include <linux/kgdb.h>
33 #include <linux/kdebug.h>
34 #include <linux/kprobes.h>
35 #include <linux/notifier.h>
36 #include <linux/kdb.h>
37 #include <linux/irq.h>
38 #include <linux/perf_event.h>
40 #include <asm/addrspace.h>
41 #include <asm/bootinfo.h>
42 #include <asm/branch.h>
43 #include <asm/break.h>
46 #include <asm/cpu-type.h>
49 #include <asm/fpu_emulator.h>
51 #include <asm/mips-r2-to-r6-emul.h>
52 #include <asm/mipsregs.h>
53 #include <asm/mipsmtregs.h>
54 #include <asm/module.h>
56 #include <asm/pgtable.h>
57 #include <asm/ptrace.h>
58 #include <asm/sections.h>
59 #include <asm/tlbdebug.h>
60 #include <asm/traps.h>
61 #include <asm/uaccess.h>
62 #include <asm/watch.h>
63 #include <asm/mmu_context.h>
64 #include <asm/types.h>
65 #include <asm/stacktrace.h>
68 extern void check_wait(void);
69 extern asmlinkage void rollback_handle_int(void);
70 extern asmlinkage void handle_int(void);
71 extern u32 handle_tlbl[];
72 extern u32 handle_tlbs[];
73 extern u32 handle_tlbm[];
74 extern asmlinkage void handle_adel(void);
75 extern asmlinkage void handle_ades(void);
76 extern asmlinkage void handle_ibe(void);
77 extern asmlinkage void handle_dbe(void);
78 extern asmlinkage void handle_sys(void);
79 extern asmlinkage void handle_bp(void);
80 extern asmlinkage void handle_ri(void);
81 extern asmlinkage void handle_ri_rdhwr_vivt(void);
82 extern asmlinkage void handle_ri_rdhwr(void);
83 extern asmlinkage void handle_cpu(void);
84 extern asmlinkage void handle_ov(void);
85 extern asmlinkage void handle_tr(void);
86 extern asmlinkage void handle_msa_fpe(void);
87 extern asmlinkage void handle_fpe(void);
88 extern asmlinkage void handle_ftlb(void);
89 extern asmlinkage void handle_msa(void);
90 extern asmlinkage void handle_mdmx(void);
91 extern asmlinkage void handle_watch(void);
92 extern asmlinkage void handle_mt(void);
93 extern asmlinkage void handle_dsp(void);
94 extern asmlinkage void handle_mcheck(void);
95 extern asmlinkage void handle_reserved(void);
96 extern void tlb_do_page_fault_0(void);
98 void (*board_be_init)(void);
99 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
100 void (*board_nmi_handler_setup)(void);
101 void (*board_ejtag_handler_setup)(void);
102 void (*board_bind_eic_interrupt)(int irq, int regset);
103 void (*board_ebase_setup)(void);
104 void(*board_cache_error_setup)(void);
106 static void show_raw_backtrace(unsigned long reg29)
108 unsigned long *sp = (unsigned long *)(reg29 & ~3);
111 printk("Call Trace:");
112 #ifdef CONFIG_KALLSYMS
115 while (!kstack_end(sp)) {
116 unsigned long __user *p =
117 (unsigned long __user *)(unsigned long)sp++;
118 if (__get_user(addr, p)) {
119 printk(" (Bad stack address)");
122 if (__kernel_text_address(addr))
128 #ifdef CONFIG_KALLSYMS
130 static int __init set_raw_show_trace(char *str)
135 __setup("raw_show_trace", set_raw_show_trace);
138 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs)
140 unsigned long sp = regs->regs[29];
141 unsigned long ra = regs->regs[31];
142 unsigned long pc = regs->cp0_epc;
147 if (raw_show_trace || !__kernel_text_address(pc)) {
148 show_raw_backtrace(sp);
151 printk("Call Trace:\n");
154 pc = unwind_stack(task, &sp, pc, &ra);
160 * This routine abuses get_user()/put_user() to reference pointers
161 * with at least a bit of error checking ...
163 static void show_stacktrace(struct task_struct *task,
164 const struct pt_regs *regs)
166 const int field = 2 * sizeof(unsigned long);
169 unsigned long __user *sp = (unsigned long __user *)regs->regs[29];
173 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
174 if (i && ((i % (64 / field)) == 0))
181 if (__get_user(stackdata, sp++)) {
182 printk(" (Bad stack address)");
186 printk(" %0*lx", field, stackdata);
190 show_backtrace(task, regs);
193 void show_stack(struct task_struct *task, unsigned long *sp)
196 mm_segment_t old_fs = get_fs();
198 regs.regs[29] = (unsigned long)sp;
202 if (task && task != current) {
203 regs.regs[29] = task->thread.reg29;
205 regs.cp0_epc = task->thread.reg31;
206 #ifdef CONFIG_KGDB_KDB
207 } else if (atomic_read(&kgdb_active) != -1 &&
209 memcpy(®s, kdb_current_regs, sizeof(regs));
210 #endif /* CONFIG_KGDB_KDB */
212 prepare_frametrace(®s);
216 * show_stack() deals exclusively with kernel mode, so be sure to access
217 * the stack in the kernel (not user) address space.
220 show_stacktrace(task, ®s);
224 static void show_code(unsigned int __user *pc)
227 unsigned short __user *pc16 = NULL;
231 if ((unsigned long)pc & 1)
232 pc16 = (unsigned short __user *)((unsigned long)pc & ~1);
233 for(i = -3 ; i < 6 ; i++) {
235 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) {
236 printk(" (Bad address in epc)\n");
239 printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>'));
243 static void __show_regs(const struct pt_regs *regs)
245 const int field = 2 * sizeof(unsigned long);
246 unsigned int cause = regs->cp0_cause;
247 unsigned int exccode;
250 show_regs_print_info(KERN_DEFAULT);
253 * Saved main processor registers
255 for (i = 0; i < 32; ) {
259 printk(" %0*lx", field, 0UL);
260 else if (i == 26 || i == 27)
261 printk(" %*s", field, "");
263 printk(" %0*lx", field, regs->regs[i]);
270 #ifdef CONFIG_CPU_HAS_SMARTMIPS
271 printk("Acx : %0*lx\n", field, regs->acx);
273 printk("Hi : %0*lx\n", field, regs->hi);
274 printk("Lo : %0*lx\n", field, regs->lo);
277 * Saved cp0 registers
279 printk("epc : %0*lx %pS\n", field, regs->cp0_epc,
280 (void *) regs->cp0_epc);
281 printk("ra : %0*lx %pS\n", field, regs->regs[31],
282 (void *) regs->regs[31]);
284 printk("Status: %08x ", (uint32_t) regs->cp0_status);
287 if (regs->cp0_status & ST0_KUO)
289 if (regs->cp0_status & ST0_IEO)
291 if (regs->cp0_status & ST0_KUP)
293 if (regs->cp0_status & ST0_IEP)
295 if (regs->cp0_status & ST0_KUC)
297 if (regs->cp0_status & ST0_IEC)
299 } else if (cpu_has_4kex) {
300 if (regs->cp0_status & ST0_KX)
302 if (regs->cp0_status & ST0_SX)
304 if (regs->cp0_status & ST0_UX)
306 switch (regs->cp0_status & ST0_KSU) {
311 printk("SUPERVISOR ");
320 if (regs->cp0_status & ST0_ERL)
322 if (regs->cp0_status & ST0_EXL)
324 if (regs->cp0_status & ST0_IE)
329 exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
330 printk("Cause : %08x (ExcCode %02x)\n", cause, exccode);
332 if (1 <= exccode && exccode <= 5)
333 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
335 printk("PrId : %08x (%s)\n", read_c0_prid(),
340 * FIXME: really the generic show_regs should take a const pointer argument.
342 void show_regs(struct pt_regs *regs)
344 __show_regs((struct pt_regs *)regs);
347 void show_registers(struct pt_regs *regs)
349 const int field = 2 * sizeof(unsigned long);
350 mm_segment_t old_fs = get_fs();
354 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n",
355 current->comm, current->pid, current_thread_info(), current,
356 field, current_thread_info()->tp_value);
357 if (cpu_has_userlocal) {
360 tls = read_c0_userlocal();
361 if (tls != current_thread_info()->tp_value)
362 printk("*HwTLS: %0*lx\n", field, tls);
365 if (!user_mode(regs))
366 /* Necessary for getting the correct stack content */
368 show_stacktrace(current, regs);
369 show_code((unsigned int __user *) regs->cp0_epc);
374 static DEFINE_RAW_SPINLOCK(die_lock);
376 void __noreturn die(const char *str, struct pt_regs *regs)
378 static int die_counter;
383 if (notify_die(DIE_OOPS, str, regs, 0, current->thread.trap_nr,
384 SIGSEGV) == NOTIFY_STOP)
388 raw_spin_lock_irq(&die_lock);
391 printk("%s[#%d]:\n", str, ++die_counter);
392 show_registers(regs);
393 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
394 raw_spin_unlock_irq(&die_lock);
399 panic("Fatal exception in interrupt");
402 printk(KERN_EMERG "Fatal exception: panic in 5 seconds");
404 panic("Fatal exception");
407 if (regs && kexec_should_crash(current))
413 extern struct exception_table_entry __start___dbe_table[];
414 extern struct exception_table_entry __stop___dbe_table[];
417 " .section __dbe_table, \"a\"\n"
420 /* Given an address, look for it in the exception tables. */
421 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
423 const struct exception_table_entry *e;
425 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
427 e = search_module_dbetables(addr);
431 asmlinkage void do_be(struct pt_regs *regs)
433 const int field = 2 * sizeof(unsigned long);
434 const struct exception_table_entry *fixup = NULL;
435 int data = regs->cp0_cause & 4;
436 int action = MIPS_BE_FATAL;
437 enum ctx_state prev_state;
439 prev_state = exception_enter();
440 /* XXX For now. Fixme, this searches the wrong table ... */
441 if (data && !user_mode(regs))
442 fixup = search_dbe_tables(exception_epc(regs));
445 action = MIPS_BE_FIXUP;
447 if (board_be_handler)
448 action = board_be_handler(regs, fixup != NULL);
451 case MIPS_BE_DISCARD:
455 regs->cp0_epc = fixup->nextinsn;
464 * Assume it would be too dangerous to continue ...
466 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
467 data ? "Data" : "Instruction",
468 field, regs->cp0_epc, field, regs->regs[31]);
469 if (notify_die(DIE_OOPS, "bus error", regs, 0, current->thread.trap_nr,
470 SIGBUS) == NOTIFY_STOP)
473 die_if_kernel("Oops", regs);
474 force_sig(SIGBUS, current);
477 exception_exit(prev_state);
481 * ll/sc, rdhwr, sync emulation
484 #define OPCODE 0xfc000000
485 #define BASE 0x03e00000
486 #define RT 0x001f0000
487 #define OFFSET 0x0000ffff
488 #define LL 0xc0000000
489 #define SC 0xe0000000
490 #define SPEC0 0x00000000
491 #define SPEC3 0x7c000000
492 #define RD 0x0000f800
493 #define FUNC 0x0000003f
494 #define SYNC 0x0000000f
495 #define RDHWR 0x0000003b
497 /* microMIPS definitions */
498 #define MM_POOL32A_FUNC 0xfc00ffff
499 #define MM_RDHWR 0x00006b3c
500 #define MM_RS 0x001f0000
501 #define MM_RT 0x03e00000
504 * The ll_bit is cleared by r*_switch.S
508 struct task_struct *ll_task;
510 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)
512 unsigned long value, __user *vaddr;
516 * analyse the ll instruction that just caused a ri exception
517 * and put the referenced address to addr.
520 /* sign extend offset */
521 offset = opcode & OFFSET;
525 vaddr = (unsigned long __user *)
526 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
528 if ((unsigned long)vaddr & 3)
530 if (get_user(value, vaddr))
535 if (ll_task == NULL || ll_task == current) {
544 regs->regs[(opcode & RT) >> 16] = value;
549 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
551 unsigned long __user *vaddr;
556 * analyse the sc instruction that just caused a ri exception
557 * and put the referenced address to addr.
560 /* sign extend offset */
561 offset = opcode & OFFSET;
565 vaddr = (unsigned long __user *)
566 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
567 reg = (opcode & RT) >> 16;
569 if ((unsigned long)vaddr & 3)
574 if (ll_bit == 0 || ll_task != current) {
582 if (put_user(regs->regs[reg], vaddr))
591 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
592 * opcodes are supposed to result in coprocessor unusable exceptions if
593 * executed on ll/sc-less processors. That's the theory. In practice a
594 * few processors such as NEC's VR4100 throw reserved instruction exceptions
595 * instead, so we're doing the emulation thing in both exception handlers.
597 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
599 if ((opcode & OPCODE) == LL) {
600 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
602 return simulate_ll(regs, opcode);
604 if ((opcode & OPCODE) == SC) {
605 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
607 return simulate_sc(regs, opcode);
610 return -1; /* Must be something else ... */
614 * Simulate trapping 'rdhwr' instructions to provide user accessible
615 * registers not implemented in hardware.
617 static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt)
619 struct thread_info *ti = task_thread_info(current);
621 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
624 case 0: /* CPU number */
625 regs->regs[rt] = smp_processor_id();
627 case 1: /* SYNCI length */
628 regs->regs[rt] = min(current_cpu_data.dcache.linesz,
629 current_cpu_data.icache.linesz);
631 case 2: /* Read count register */
632 regs->regs[rt] = read_c0_count();
634 case 3: /* Count register resolution */
635 switch (current_cpu_type()) {
645 regs->regs[rt] = ti->tp_value;
652 static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode)
654 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
655 int rd = (opcode & RD) >> 11;
656 int rt = (opcode & RT) >> 16;
658 simulate_rdhwr(regs, rd, rt);
666 static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned int opcode)
668 if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) {
669 int rd = (opcode & MM_RS) >> 16;
670 int rt = (opcode & MM_RT) >> 21;
671 simulate_rdhwr(regs, rd, rt);
679 static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
681 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) {
682 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
687 return -1; /* Must be something else ... */
690 asmlinkage void do_ov(struct pt_regs *regs)
692 enum ctx_state prev_state;
695 .si_code = FPE_INTOVF,
696 .si_addr = (void __user *)regs->cp0_epc,
699 prev_state = exception_enter();
700 die_if_kernel("Integer overflow", regs);
702 force_sig_info(SIGFPE, &info, current);
703 exception_exit(prev_state);
706 int process_fpemu_return(int sig, void __user *fault_addr, unsigned long fcr31)
708 struct siginfo si = { 0 };
715 si.si_addr = fault_addr;
718 * Inexact can happen together with Overflow or Underflow.
719 * Respect the mask to deliver the correct exception.
721 fcr31 &= (fcr31 & FPU_CSR_ALL_E) <<
722 (ffs(FPU_CSR_ALL_X) - ffs(FPU_CSR_ALL_E));
723 if (fcr31 & FPU_CSR_INV_X)
724 si.si_code = FPE_FLTINV;
725 else if (fcr31 & FPU_CSR_DIV_X)
726 si.si_code = FPE_FLTDIV;
727 else if (fcr31 & FPU_CSR_OVF_X)
728 si.si_code = FPE_FLTOVF;
729 else if (fcr31 & FPU_CSR_UDF_X)
730 si.si_code = FPE_FLTUND;
731 else if (fcr31 & FPU_CSR_INE_X)
732 si.si_code = FPE_FLTRES;
734 si.si_code = __SI_FAULT;
735 force_sig_info(sig, &si, current);
739 si.si_addr = fault_addr;
741 si.si_code = BUS_ADRERR;
742 force_sig_info(sig, &si, current);
746 si.si_addr = fault_addr;
748 down_read(¤t->mm->mmap_sem);
749 if (find_vma(current->mm, (unsigned long)fault_addr))
750 si.si_code = SEGV_ACCERR;
752 si.si_code = SEGV_MAPERR;
753 up_read(¤t->mm->mmap_sem);
754 force_sig_info(sig, &si, current);
758 force_sig(sig, current);
763 static int simulate_fp(struct pt_regs *regs, unsigned int opcode,
764 unsigned long old_epc, unsigned long old_ra)
766 union mips_instruction inst = { .word = opcode };
767 void __user *fault_addr;
771 /* If it's obviously not an FP instruction, skip it */
772 switch (inst.i_format.opcode) {
786 * do_ri skipped over the instruction via compute_return_epc, undo
787 * that for the FPU emulator.
789 regs->cp0_epc = old_epc;
790 regs->regs[31] = old_ra;
792 /* Save the FP context to struct thread_struct */
795 /* Run the emulator */
796 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1,
798 fcr31 = current->thread.fpu.fcr31;
801 * We can't allow the emulated instruction to leave any of
802 * the cause bits set in $fcr31.
804 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
806 /* Restore the hardware register state */
809 /* Send a signal if required. */
810 process_fpemu_return(sig, fault_addr, fcr31);
816 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
818 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
820 enum ctx_state prev_state;
821 void __user *fault_addr;
824 prev_state = exception_enter();
825 if (notify_die(DIE_FP, "FP exception", regs, 0, current->thread.trap_nr,
826 SIGFPE) == NOTIFY_STOP)
829 /* Clear FCSR.Cause before enabling interrupts */
830 write_32bit_cp1_register(CP1_STATUS, fcr31 & ~FPU_CSR_ALL_X);
833 die_if_kernel("FP exception in kernel code", regs);
835 if (fcr31 & FPU_CSR_UNI_X) {
837 * Unimplemented operation exception. If we've got the full
838 * software emulator on-board, let's use it...
840 * Force FPU to dump state into task/thread context. We're
841 * moving a lot of data here for what is probably a single
842 * instruction, but the alternative is to pre-decode the FP
843 * register operands before invoking the emulator, which seems
844 * a bit extreme for what should be an infrequent event.
846 /* Ensure 'resume' not overwrite saved fp context again. */
849 /* Run the emulator */
850 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1,
852 fcr31 = current->thread.fpu.fcr31;
855 * We can't allow the emulated instruction to leave any of
856 * the cause bits set in $fcr31.
858 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
860 /* Restore the hardware register state */
861 own_fpu(1); /* Using the FPU again. */
864 fault_addr = (void __user *) regs->cp0_epc;
867 /* Send a signal if required. */
868 process_fpemu_return(sig, fault_addr, fcr31);
871 exception_exit(prev_state);
874 void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
877 siginfo_t info = { 0 };
880 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
881 if (kgdb_ll_trap(DIE_TRAP, str, regs, code, current->thread.trap_nr,
882 SIGTRAP) == NOTIFY_STOP)
884 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
886 if (notify_die(DIE_TRAP, str, regs, code, current->thread.trap_nr,
887 SIGTRAP) == NOTIFY_STOP)
891 * A short test says that IRIX 5.3 sends SIGTRAP for all trap
892 * insns, even for trap and break codes that indicate arithmetic
893 * failures. Weird ...
894 * But should we continue the brokenness??? --macro
899 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
900 die_if_kernel(b, regs);
901 if (code == BRK_DIVZERO)
902 info.si_code = FPE_INTDIV;
904 info.si_code = FPE_INTOVF;
905 info.si_signo = SIGFPE;
906 info.si_addr = (void __user *) regs->cp0_epc;
907 force_sig_info(SIGFPE, &info, current);
910 die_if_kernel("Kernel bug detected", regs);
911 force_sig(SIGTRAP, current);
915 * This breakpoint code is used by the FPU emulator to retake
916 * control of the CPU after executing the instruction from the
917 * delay slot of an emulated branch.
919 * Terminate if exception was recognized as a delay slot return
920 * otherwise handle as normal.
922 if (do_dsemulret(regs))
925 die_if_kernel("Math emu break/trap", regs);
926 force_sig(SIGTRAP, current);
929 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
930 die_if_kernel(b, regs);
931 force_sig(SIGTRAP, current);
935 asmlinkage void do_bp(struct pt_regs *regs)
937 unsigned long epc = msk_isa16_mode(exception_epc(regs));
938 unsigned int opcode, bcode;
939 enum ctx_state prev_state;
943 if (!user_mode(regs))
946 prev_state = exception_enter();
947 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
948 if (get_isa16_mode(regs->cp0_epc)) {
951 if (__get_user(instr[0], (u16 __user *)epc))
954 if (!cpu_has_mmips) {
956 bcode = (instr[0] >> 5) & 0x3f;
957 } else if (mm_insn_16bit(instr[0])) {
958 /* 16-bit microMIPS BREAK */
959 bcode = instr[0] & 0xf;
961 /* 32-bit microMIPS BREAK */
962 if (__get_user(instr[1], (u16 __user *)(epc + 2)))
964 opcode = (instr[0] << 16) | instr[1];
965 bcode = (opcode >> 6) & ((1 << 20) - 1);
968 if (__get_user(opcode, (unsigned int __user *)epc))
970 bcode = (opcode >> 6) & ((1 << 20) - 1);
974 * There is the ancient bug in the MIPS assemblers that the break
975 * code starts left to bit 16 instead to bit 6 in the opcode.
976 * Gas is bug-compatible, but not always, grrr...
977 * We handle both cases with a simple heuristics. --macro
979 if (bcode >= (1 << 10))
980 bcode = ((bcode & ((1 << 10) - 1)) << 10) | (bcode >> 10);
983 * notify the kprobe handlers, if instruction is likely to
988 if (notify_die(DIE_UPROBE, "uprobe", regs, bcode,
989 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
994 if (notify_die(DIE_UPROBE_XOL, "uprobe_xol", regs, bcode,
995 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1000 if (notify_die(DIE_BREAK, "debug", regs, bcode,
1001 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1005 case BRK_KPROBE_SSTEPBP:
1006 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode,
1007 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1015 do_trap_or_bp(regs, bcode, "Break");
1019 exception_exit(prev_state);
1023 force_sig(SIGSEGV, current);
1027 asmlinkage void do_tr(struct pt_regs *regs)
1029 u32 opcode, tcode = 0;
1030 enum ctx_state prev_state;
1033 unsigned long epc = msk_isa16_mode(exception_epc(regs));
1036 if (!user_mode(regs))
1039 prev_state = exception_enter();
1040 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
1041 if (get_isa16_mode(regs->cp0_epc)) {
1042 if (__get_user(instr[0], (u16 __user *)(epc + 0)) ||
1043 __get_user(instr[1], (u16 __user *)(epc + 2)))
1045 opcode = (instr[0] << 16) | instr[1];
1046 /* Immediate versions don't provide a code. */
1047 if (!(opcode & OPCODE))
1048 tcode = (opcode >> 12) & ((1 << 4) - 1);
1050 if (__get_user(opcode, (u32 __user *)epc))
1052 /* Immediate versions don't provide a code. */
1053 if (!(opcode & OPCODE))
1054 tcode = (opcode >> 6) & ((1 << 10) - 1);
1057 do_trap_or_bp(regs, tcode, "Trap");
1061 exception_exit(prev_state);
1065 force_sig(SIGSEGV, current);
1069 asmlinkage void do_ri(struct pt_regs *regs)
1071 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs);
1072 unsigned long old_epc = regs->cp0_epc;
1073 unsigned long old31 = regs->regs[31];
1074 enum ctx_state prev_state;
1075 unsigned int opcode = 0;
1079 * Avoid any kernel code. Just emulate the R2 instruction
1080 * as quickly as possible.
1082 if (mipsr2_emulation && cpu_has_mips_r6 &&
1083 likely(user_mode(regs)) &&
1084 likely(get_user(opcode, epc) >= 0)) {
1085 unsigned long fcr31 = 0;
1087 status = mipsr2_decoder(regs, opcode, &fcr31);
1091 task_thread_info(current)->r2_emul_return = 1;
1096 process_fpemu_return(status,
1097 ¤t->thread.cp0_baduaddr,
1099 task_thread_info(current)->r2_emul_return = 1;
1106 prev_state = exception_enter();
1107 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
1109 if (notify_die(DIE_RI, "RI Fault", regs, 0, current->thread.trap_nr,
1110 SIGILL) == NOTIFY_STOP)
1113 die_if_kernel("Reserved instruction in kernel code", regs);
1115 if (unlikely(compute_return_epc(regs) < 0))
1118 if (get_isa16_mode(regs->cp0_epc)) {
1119 unsigned short mmop[2] = { 0 };
1121 if (unlikely(get_user(mmop[0], (u16 __user *)epc + 0) < 0))
1123 if (unlikely(get_user(mmop[1], (u16 __user *)epc + 1) < 0))
1126 opcode = (opcode << 16) | mmop[1];
1129 status = simulate_rdhwr_mm(regs, opcode);
1131 if (unlikely(get_user(opcode, epc) < 0))
1134 if (!cpu_has_llsc && status < 0)
1135 status = simulate_llsc(regs, opcode);
1138 status = simulate_rdhwr_normal(regs, opcode);
1141 status = simulate_sync(regs, opcode);
1144 status = simulate_fp(regs, opcode, old_epc, old31);
1150 if (unlikely(status > 0)) {
1151 regs->cp0_epc = old_epc; /* Undo skip-over. */
1152 regs->regs[31] = old31;
1153 force_sig(status, current);
1157 exception_exit(prev_state);
1161 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
1162 * emulated more than some threshold number of instructions, force migration to
1163 * a "CPU" that has FP support.
1165 static void mt_ase_fp_affinity(void)
1167 #ifdef CONFIG_MIPS_MT_FPAFF
1168 if (mt_fpemul_threshold > 0 &&
1169 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) {
1171 * If there's no FPU present, or if the application has already
1172 * restricted the allowed set to exclude any CPUs with FPUs,
1173 * we'll skip the procedure.
1175 if (cpumask_intersects(¤t->cpus_allowed, &mt_fpu_cpumask)) {
1178 current->thread.user_cpus_allowed
1179 = current->cpus_allowed;
1180 cpumask_and(&tmask, ¤t->cpus_allowed,
1182 set_cpus_allowed_ptr(current, &tmask);
1183 set_thread_flag(TIF_FPUBOUND);
1186 #endif /* CONFIG_MIPS_MT_FPAFF */
1190 * No lock; only written during early bootup by CPU 0.
1192 static RAW_NOTIFIER_HEAD(cu2_chain);
1194 int __ref register_cu2_notifier(struct notifier_block *nb)
1196 return raw_notifier_chain_register(&cu2_chain, nb);
1199 int cu2_notifier_call_chain(unsigned long val, void *v)
1201 return raw_notifier_call_chain(&cu2_chain, val, v);
1204 static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
1207 struct pt_regs *regs = data;
1209 die_if_kernel("COP2: Unhandled kernel unaligned access or invalid "
1210 "instruction", regs);
1211 force_sig(SIGILL, current);
1216 static int wait_on_fp_mode_switch(atomic_t *p)
1219 * The FP mode for this task is currently being switched. That may
1220 * involve modifications to the format of this tasks FP context which
1221 * make it unsafe to proceed with execution for the moment. Instead,
1222 * schedule some other task.
1228 static int enable_restore_fp_context(int msa)
1230 int err, was_fpu_owner, prior_msa;
1233 * If an FP mode switch is currently underway, wait for it to
1234 * complete before proceeding.
1236 wait_on_atomic_t(¤t->mm->context.fp_mode_switching,
1237 wait_on_fp_mode_switch, TASK_KILLABLE);
1240 /* First time FP context user. */
1246 set_thread_flag(TIF_USEDMSA);
1247 set_thread_flag(TIF_MSA_CTX_LIVE);
1256 * This task has formerly used the FP context.
1258 * If this thread has no live MSA vector context then we can simply
1259 * restore the scalar FP context. If it has live MSA vector context
1260 * (that is, it has or may have used MSA since last performing a
1261 * function call) then we'll need to restore the vector context. This
1262 * applies even if we're currently only executing a scalar FP
1263 * instruction. This is because if we were to later execute an MSA
1264 * instruction then we'd either have to:
1266 * - Restore the vector context & clobber any registers modified by
1267 * scalar FP instructions between now & then.
1271 * - Not restore the vector context & lose the most significant bits
1272 * of all vector registers.
1274 * Neither of those options is acceptable. We cannot restore the least
1275 * significant bits of the registers now & only restore the most
1276 * significant bits later because the most significant bits of any
1277 * vector registers whose aliased FP register is modified now will have
1278 * been zeroed. We'd have no way to know that when restoring the vector
1279 * context & thus may load an outdated value for the most significant
1280 * bits of a vector register.
1282 if (!msa && !thread_msa_context_live())
1286 * This task is using or has previously used MSA. Thus we require
1287 * that Status.FR == 1.
1290 was_fpu_owner = is_fpu_owner();
1291 err = own_fpu_inatomic(0);
1296 write_msa_csr(current->thread.fpu.msacsr);
1297 set_thread_flag(TIF_USEDMSA);
1300 * If this is the first time that the task is using MSA and it has
1301 * previously used scalar FP in this time slice then we already nave
1302 * FP context which we shouldn't clobber. We do however need to clear
1303 * the upper 64b of each vector register so that this task has no
1304 * opportunity to see data left behind by another.
1306 prior_msa = test_and_set_thread_flag(TIF_MSA_CTX_LIVE);
1307 if (!prior_msa && was_fpu_owner) {
1315 * Restore the least significant 64b of each vector register
1316 * from the existing scalar FP context.
1318 _restore_fp(current);
1321 * The task has not formerly used MSA, so clear the upper 64b
1322 * of each vector register such that it cannot see data left
1323 * behind by another task.
1327 /* We need to restore the vector context. */
1328 restore_msa(current);
1330 /* Restore the scalar FP control & status register */
1332 write_32bit_cp1_register(CP1_STATUS,
1333 current->thread.fpu.fcr31);
1342 asmlinkage void do_cpu(struct pt_regs *regs)
1344 enum ctx_state prev_state;
1345 unsigned int __user *epc;
1346 unsigned long old_epc, old31;
1347 void __user *fault_addr;
1348 unsigned int opcode;
1349 unsigned long fcr31;
1352 unsigned long __maybe_unused flags;
1355 prev_state = exception_enter();
1356 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
1359 die_if_kernel("do_cpu invoked from kernel context!", regs);
1363 epc = (unsigned int __user *)exception_epc(regs);
1364 old_epc = regs->cp0_epc;
1365 old31 = regs->regs[31];
1369 if (unlikely(compute_return_epc(regs) < 0))
1372 if (!get_isa16_mode(regs->cp0_epc)) {
1373 if (unlikely(get_user(opcode, epc) < 0))
1376 if (!cpu_has_llsc && status < 0)
1377 status = simulate_llsc(regs, opcode);
1383 if (unlikely(status > 0)) {
1384 regs->cp0_epc = old_epc; /* Undo skip-over. */
1385 regs->regs[31] = old31;
1386 force_sig(status, current);
1393 * The COP3 opcode space and consequently the CP0.Status.CU3
1394 * bit and the CP0.Cause.CE=3 encoding have been removed as
1395 * of the MIPS III ISA. From the MIPS IV and MIPS32r2 ISAs
1396 * up the space has been reused for COP1X instructions, that
1397 * are enabled by the CP0.Status.CU1 bit and consequently
1398 * use the CP0.Cause.CE=1 encoding for Coprocessor Unusable
1399 * exceptions. Some FPU-less processors that implement one
1400 * of these ISAs however use this code erroneously for COP1X
1401 * instructions. Therefore we redirect this trap to the FP
1404 if (raw_cpu_has_fpu || !cpu_has_mips_4_5_64_r2_r6) {
1405 force_sig(SIGILL, current);
1411 err = enable_restore_fp_context(0);
1413 if (raw_cpu_has_fpu && !err)
1416 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 0,
1418 fcr31 = current->thread.fpu.fcr31;
1421 * We can't allow the emulated instruction to leave
1422 * any of the cause bits set in $fcr31.
1424 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
1426 /* Send a signal if required. */
1427 if (!process_fpemu_return(sig, fault_addr, fcr31) && !err)
1428 mt_ase_fp_affinity();
1433 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
1437 exception_exit(prev_state);
1440 asmlinkage void do_msa_fpe(struct pt_regs *regs, unsigned int msacsr)
1442 enum ctx_state prev_state;
1444 prev_state = exception_enter();
1445 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
1446 if (notify_die(DIE_MSAFP, "MSA FP exception", regs, 0,
1447 current->thread.trap_nr, SIGFPE) == NOTIFY_STOP)
1450 /* Clear MSACSR.Cause before enabling interrupts */
1451 write_msa_csr(msacsr & ~MSA_CSR_CAUSEF);
1454 die_if_kernel("do_msa_fpe invoked from kernel context!", regs);
1455 force_sig(SIGFPE, current);
1457 exception_exit(prev_state);
1460 asmlinkage void do_msa(struct pt_regs *regs)
1462 enum ctx_state prev_state;
1465 prev_state = exception_enter();
1467 if (!cpu_has_msa || test_thread_flag(TIF_32BIT_FPREGS)) {
1468 force_sig(SIGILL, current);
1472 die_if_kernel("do_msa invoked from kernel context!", regs);
1474 err = enable_restore_fp_context(1);
1476 force_sig(SIGILL, current);
1478 exception_exit(prev_state);
1481 asmlinkage void do_mdmx(struct pt_regs *regs)
1483 enum ctx_state prev_state;
1485 prev_state = exception_enter();
1486 force_sig(SIGILL, current);
1487 exception_exit(prev_state);
1491 * Called with interrupts disabled.
1493 asmlinkage void do_watch(struct pt_regs *regs)
1495 enum ctx_state prev_state;
1498 prev_state = exception_enter();
1500 * Clear WP (bit 22) bit of cause register so we don't loop
1503 cause = read_c0_cause();
1504 cause &= ~(1 << 22);
1505 write_c0_cause(cause);
1508 * If the current thread has the watch registers loaded, save
1509 * their values and send SIGTRAP. Otherwise another thread
1510 * left the registers set, clear them and continue.
1512 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
1513 mips_read_watch_registers();
1515 force_sig(SIGTRAP, current);
1517 mips_clear_watch_registers();
1520 exception_exit(prev_state);
1523 asmlinkage void do_mcheck(struct pt_regs *regs)
1525 int multi_match = regs->cp0_status & ST0_TS;
1526 enum ctx_state prev_state;
1527 mm_segment_t old_fs = get_fs();
1529 prev_state = exception_enter();
1538 if (!user_mode(regs))
1541 show_code((unsigned int __user *) regs->cp0_epc);
1546 * Some chips may have other causes of machine check (e.g. SB1
1549 panic("Caught Machine Check exception - %scaused by multiple "
1550 "matching entries in the TLB.",
1551 (multi_match) ? "" : "not ");
1554 asmlinkage void do_mt(struct pt_regs *regs)
1558 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
1559 >> VPECONTROL_EXCPT_SHIFT;
1562 printk(KERN_DEBUG "Thread Underflow\n");
1565 printk(KERN_DEBUG "Thread Overflow\n");
1568 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
1571 printk(KERN_DEBUG "Gating Storage Exception\n");
1574 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
1577 printk(KERN_DEBUG "Gating Storage Scheduler Exception\n");
1580 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
1584 die_if_kernel("MIPS MT Thread exception in kernel", regs);
1586 force_sig(SIGILL, current);
1590 asmlinkage void do_dsp(struct pt_regs *regs)
1593 panic("Unexpected DSP exception");
1595 force_sig(SIGILL, current);
1598 asmlinkage void do_reserved(struct pt_regs *regs)
1601 * Game over - no way to handle this if it ever occurs. Most probably
1602 * caused by a new unknown cpu type or after another deadly
1603 * hard/software error.
1606 panic("Caught reserved exception %ld - should not happen.",
1607 (regs->cp0_cause & 0x7f) >> 2);
1610 static int __initdata l1parity = 1;
1611 static int __init nol1parity(char *s)
1616 __setup("nol1par", nol1parity);
1617 static int __initdata l2parity = 1;
1618 static int __init nol2parity(char *s)
1623 __setup("nol2par", nol2parity);
1626 * Some MIPS CPUs can enable/disable for cache parity detection, but do
1627 * it different ways.
1629 static inline void parity_protection_init(void)
1631 switch (current_cpu_type()) {
1637 case CPU_INTERAPTIV:
1640 case CPU_QEMU_GENERIC:
1643 #define ERRCTL_PE 0x80000000
1644 #define ERRCTL_L2P 0x00800000
1645 unsigned long errctl;
1646 unsigned int l1parity_present, l2parity_present;
1648 errctl = read_c0_ecc();
1649 errctl &= ~(ERRCTL_PE|ERRCTL_L2P);
1651 /* probe L1 parity support */
1652 write_c0_ecc(errctl | ERRCTL_PE);
1653 back_to_back_c0_hazard();
1654 l1parity_present = (read_c0_ecc() & ERRCTL_PE);
1656 /* probe L2 parity support */
1657 write_c0_ecc(errctl|ERRCTL_L2P);
1658 back_to_back_c0_hazard();
1659 l2parity_present = (read_c0_ecc() & ERRCTL_L2P);
1661 if (l1parity_present && l2parity_present) {
1663 errctl |= ERRCTL_PE;
1664 if (l1parity ^ l2parity)
1665 errctl |= ERRCTL_L2P;
1666 } else if (l1parity_present) {
1668 errctl |= ERRCTL_PE;
1669 } else if (l2parity_present) {
1671 errctl |= ERRCTL_L2P;
1673 /* No parity available */
1676 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl);
1678 write_c0_ecc(errctl);
1679 back_to_back_c0_hazard();
1680 errctl = read_c0_ecc();
1681 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl);
1683 if (l1parity_present)
1684 printk(KERN_INFO "Cache parity protection %sabled\n",
1685 (errctl & ERRCTL_PE) ? "en" : "dis");
1687 if (l2parity_present) {
1688 if (l1parity_present && l1parity)
1689 errctl ^= ERRCTL_L2P;
1690 printk(KERN_INFO "L2 cache parity protection %sabled\n",
1691 (errctl & ERRCTL_L2P) ? "en" : "dis");
1699 write_c0_ecc(0x80000000);
1700 back_to_back_c0_hazard();
1701 /* Set the PE bit (bit 31) in the c0_errctl register. */
1702 printk(KERN_INFO "Cache parity protection %sabled\n",
1703 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
1707 /* Clear the DE bit (bit 16) in the c0_status register. */
1708 printk(KERN_INFO "Enable cache parity protection for "
1709 "MIPS 20KC/25KF CPUs.\n");
1710 clear_c0_status(ST0_DE);
1717 asmlinkage void cache_parity_error(void)
1719 const int field = 2 * sizeof(unsigned long);
1720 unsigned int reg_val;
1722 /* For the moment, report the problem and hang. */
1723 printk("Cache error exception:\n");
1724 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1725 reg_val = read_c0_cacheerr();
1726 printk("c0_cacheerr == %08x\n", reg_val);
1728 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1729 reg_val & (1<<30) ? "secondary" : "primary",
1730 reg_val & (1<<31) ? "data" : "insn");
1731 if ((cpu_has_mips_r2_r6) &&
1732 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) {
1733 pr_err("Error bits: %s%s%s%s%s%s%s%s\n",
1734 reg_val & (1<<29) ? "ED " : "",
1735 reg_val & (1<<28) ? "ET " : "",
1736 reg_val & (1<<27) ? "ES " : "",
1737 reg_val & (1<<26) ? "EE " : "",
1738 reg_val & (1<<25) ? "EB " : "",
1739 reg_val & (1<<24) ? "EI " : "",
1740 reg_val & (1<<23) ? "E1 " : "",
1741 reg_val & (1<<22) ? "E0 " : "");
1743 pr_err("Error bits: %s%s%s%s%s%s%s\n",
1744 reg_val & (1<<29) ? "ED " : "",
1745 reg_val & (1<<28) ? "ET " : "",
1746 reg_val & (1<<26) ? "EE " : "",
1747 reg_val & (1<<25) ? "EB " : "",
1748 reg_val & (1<<24) ? "EI " : "",
1749 reg_val & (1<<23) ? "E1 " : "",
1750 reg_val & (1<<22) ? "E0 " : "");
1752 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1754 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1755 if (reg_val & (1<<22))
1756 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1758 if (reg_val & (1<<23))
1759 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1762 panic("Can't handle the cache error!");
1765 asmlinkage void do_ftlb(void)
1767 const int field = 2 * sizeof(unsigned long);
1768 unsigned int reg_val;
1770 /* For the moment, report the problem and hang. */
1771 if ((cpu_has_mips_r2_r6) &&
1772 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) {
1773 pr_err("FTLB error exception, cp0_ecc=0x%08x:\n",
1775 pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1776 reg_val = read_c0_cacheerr();
1777 pr_err("c0_cacheerr == %08x\n", reg_val);
1779 if ((reg_val & 0xc0000000) == 0xc0000000) {
1780 pr_err("Decoded c0_cacheerr: FTLB parity error\n");
1782 pr_err("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1783 reg_val & (1<<30) ? "secondary" : "primary",
1784 reg_val & (1<<31) ? "data" : "insn");
1787 pr_err("FTLB error exception\n");
1789 /* Just print the cacheerr bits for now */
1790 cache_parity_error();
1794 * SDBBP EJTAG debug exception handler.
1795 * We skip the instruction and return to the next instruction.
1797 void ejtag_exception_handler(struct pt_regs *regs)
1799 const int field = 2 * sizeof(unsigned long);
1800 unsigned long depc, old_epc, old_ra;
1803 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1804 depc = read_c0_depc();
1805 debug = read_c0_debug();
1806 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
1807 if (debug & 0x80000000) {
1809 * In branch delay slot.
1810 * We cheat a little bit here and use EPC to calculate the
1811 * debug return address (DEPC). EPC is restored after the
1814 old_epc = regs->cp0_epc;
1815 old_ra = regs->regs[31];
1816 regs->cp0_epc = depc;
1817 compute_return_epc(regs);
1818 depc = regs->cp0_epc;
1819 regs->cp0_epc = old_epc;
1820 regs->regs[31] = old_ra;
1823 write_c0_depc(depc);
1826 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1827 write_c0_debug(debug | 0x100);
1832 * NMI exception handler.
1833 * No lock; only written during early bootup by CPU 0.
1835 static RAW_NOTIFIER_HEAD(nmi_chain);
1837 int register_nmi_notifier(struct notifier_block *nb)
1839 return raw_notifier_chain_register(&nmi_chain, nb);
1842 void __noreturn nmi_exception_handler(struct pt_regs *regs)
1847 raw_notifier_call_chain(&nmi_chain, 0, regs);
1849 snprintf(str, 100, "CPU%d NMI taken, CP0_EPC=%lx\n",
1850 smp_processor_id(), regs->cp0_epc);
1851 regs->cp0_epc = read_c0_errorepc();
1856 #define VECTORSPACING 0x100 /* for EI/VI mode */
1858 unsigned long ebase;
1859 unsigned long exception_handlers[32];
1860 unsigned long vi_handlers[64];
1862 void __init *set_except_vector(int n, void *addr)
1864 unsigned long handler = (unsigned long) addr;
1865 unsigned long old_handler;
1867 #ifdef CONFIG_CPU_MICROMIPS
1869 * Only the TLB handlers are cache aligned with an even
1870 * address. All other handlers are on an odd address and
1871 * require no modification. Otherwise, MIPS32 mode will
1872 * be entered when handling any TLB exceptions. That
1873 * would be bad...since we must stay in microMIPS mode.
1875 if (!(handler & 0x1))
1878 old_handler = xchg(&exception_handlers[n], handler);
1880 if (n == 0 && cpu_has_divec) {
1881 #ifdef CONFIG_CPU_MICROMIPS
1882 unsigned long jump_mask = ~((1 << 27) - 1);
1884 unsigned long jump_mask = ~((1 << 28) - 1);
1886 u32 *buf = (u32 *)(ebase + 0x200);
1887 unsigned int k0 = 26;
1888 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) {
1889 uasm_i_j(&buf, handler & ~jump_mask);
1892 UASM_i_LA(&buf, k0, handler);
1893 uasm_i_jr(&buf, k0);
1896 local_flush_icache_range(ebase + 0x200, (unsigned long)buf);
1898 return (void *)old_handler;
1901 static void do_default_vi(void)
1903 show_regs(get_irq_regs());
1904 panic("Caught unexpected vectored interrupt.");
1907 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1909 unsigned long handler;
1910 unsigned long old_handler = vi_handlers[n];
1911 int srssets = current_cpu_data.srsets;
1915 BUG_ON(!cpu_has_veic && !cpu_has_vint);
1918 handler = (unsigned long) do_default_vi;
1921 handler = (unsigned long) addr;
1922 vi_handlers[n] = handler;
1924 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1927 panic("Shadow register set %d not supported", srs);
1930 if (board_bind_eic_interrupt)
1931 board_bind_eic_interrupt(n, srs);
1932 } else if (cpu_has_vint) {
1933 /* SRSMap is only defined if shadow sets are implemented */
1935 change_c0_srsmap(0xf << n*4, srs << n*4);
1940 * If no shadow set is selected then use the default handler
1941 * that does normal register saving and standard interrupt exit
1943 extern char except_vec_vi, except_vec_vi_lui;
1944 extern char except_vec_vi_ori, except_vec_vi_end;
1945 extern char rollback_except_vec_vi;
1946 char *vec_start = using_rollback_handler() ?
1947 &rollback_except_vec_vi : &except_vec_vi;
1948 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
1949 const int lui_offset = &except_vec_vi_lui - vec_start + 2;
1950 const int ori_offset = &except_vec_vi_ori - vec_start + 2;
1952 const int lui_offset = &except_vec_vi_lui - vec_start;
1953 const int ori_offset = &except_vec_vi_ori - vec_start;
1955 const int handler_len = &except_vec_vi_end - vec_start;
1957 if (handler_len > VECTORSPACING) {
1959 * Sigh... panicing won't help as the console
1960 * is probably not configured :(
1962 panic("VECTORSPACING too small");
1965 set_handler(((unsigned long)b - ebase), vec_start,
1966 #ifdef CONFIG_CPU_MICROMIPS
1971 h = (u16 *)(b + lui_offset);
1972 *h = (handler >> 16) & 0xffff;
1973 h = (u16 *)(b + ori_offset);
1974 *h = (handler & 0xffff);
1975 local_flush_icache_range((unsigned long)b,
1976 (unsigned long)(b+handler_len));
1980 * In other cases jump directly to the interrupt handler. It
1981 * is the handler's responsibility to save registers if required
1982 * (eg hi/lo) and return from the exception using "eret".
1988 #ifdef CONFIG_CPU_MICROMIPS
1989 insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1);
1991 insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2);
1993 h[0] = (insn >> 16) & 0xffff;
1994 h[1] = insn & 0xffff;
1997 local_flush_icache_range((unsigned long)b,
1998 (unsigned long)(b+8));
2001 return (void *)old_handler;
2004 void *set_vi_handler(int n, vi_handler_t addr)
2006 return set_vi_srs_handler(n, addr, 0);
2009 extern void tlb_init(void);
2014 int cp0_compare_irq;
2015 EXPORT_SYMBOL_GPL(cp0_compare_irq);
2016 int cp0_compare_irq_shift;
2019 * Performance counter IRQ or -1 if shared with timer
2021 int cp0_perfcount_irq;
2022 EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
2025 * Fast debug channel IRQ or -1 if not present
2028 EXPORT_SYMBOL_GPL(cp0_fdc_irq);
2032 static int __init ulri_disable(char *s)
2034 pr_info("Disabling ulri\n");
2039 __setup("noulri", ulri_disable);
2041 /* configure STATUS register */
2042 static void configure_status(void)
2045 * Disable coprocessors and select 32-bit or 64-bit addressing
2046 * and the 16/32 or 32/32 FPR register model. Reset the BEV
2047 * flag that some firmware may have left set and the TS bit (for
2048 * IP27). Set XX for ISA IV code to work.
2050 unsigned int status_set = ST0_CU0;
2052 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
2054 if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV)
2055 status_set |= ST0_XX;
2057 status_set |= ST0_MX;
2059 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
2063 /* configure HWRENA register */
2064 static void configure_hwrena(void)
2066 unsigned int hwrena = cpu_hwrena_impl_bits;
2068 if (cpu_has_mips_r2_r6)
2069 hwrena |= 0x0000000f;
2071 if (!noulri && cpu_has_userlocal)
2072 hwrena |= (1 << 29);
2075 write_c0_hwrena(hwrena);
2078 static void configure_exception_vector(void)
2080 if (cpu_has_veic || cpu_has_vint) {
2081 unsigned long sr = set_c0_status(ST0_BEV);
2082 write_c0_ebase(ebase);
2083 write_c0_status(sr);
2084 /* Setting vector spacing enables EI/VI mode */
2085 change_c0_intctl(0x3e0, VECTORSPACING);
2087 if (cpu_has_divec) {
2088 if (cpu_has_mipsmt) {
2089 unsigned int vpflags = dvpe();
2090 set_c0_cause(CAUSEF_IV);
2093 set_c0_cause(CAUSEF_IV);
2097 void per_cpu_trap_init(bool is_boot_cpu)
2099 unsigned int cpu = smp_processor_id();
2104 configure_exception_vector();
2107 * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
2109 * o read IntCtl.IPTI to determine the timer interrupt
2110 * o read IntCtl.IPPCI to determine the performance counter interrupt
2111 * o read IntCtl.IPFDC to determine the fast debug channel interrupt
2113 if (cpu_has_mips_r2_r6) {
2114 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
2115 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
2116 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
2117 cp0_fdc_irq = (read_c0_intctl() >> INTCTLB_IPFDC) & 7;
2122 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
2123 cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ;
2124 cp0_perfcount_irq = -1;
2128 if (!cpu_data[cpu].asid_cache)
2129 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
2131 atomic_inc(&init_mm.mm_count);
2132 current->active_mm = &init_mm;
2133 BUG_ON(current->mm);
2134 enter_lazy_tlb(&init_mm, current);
2136 /* Boot CPU's cache setup in setup_arch(). */
2140 TLBMISS_HANDLER_SETUP();
2143 /* Install CPU exception handler */
2144 void set_handler(unsigned long offset, void *addr, unsigned long size)
2146 #ifdef CONFIG_CPU_MICROMIPS
2147 memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size);
2149 memcpy((void *)(ebase + offset), addr, size);
2151 local_flush_icache_range(ebase + offset, ebase + offset + size);
2154 static char panic_null_cerr[] =
2155 "Trying to set NULL cache error exception handler";
2158 * Install uncached CPU exception handler.
2159 * This is suitable only for the cache error exception which is the only
2160 * exception handler that is being run uncached.
2162 void set_uncached_handler(unsigned long offset, void *addr,
2165 unsigned long uncached_ebase = CKSEG1ADDR(ebase);
2168 panic(panic_null_cerr);
2170 memcpy((void *)(uncached_ebase + offset), addr, size);
2173 static int __initdata rdhwr_noopt;
2174 static int __init set_rdhwr_noopt(char *str)
2180 __setup("rdhwr_noopt", set_rdhwr_noopt);
2182 void __init trap_init(void)
2184 extern char except_vec3_generic;
2185 extern char except_vec4;
2186 extern char except_vec3_r4000;
2191 if (cpu_has_veic || cpu_has_vint) {
2192 unsigned long size = 0x200 + VECTORSPACING*64;
2193 ebase = (unsigned long)
2194 __alloc_bootmem(size, 1 << fls(size), 0);
2198 if (cpu_has_mips_r2_r6)
2199 ebase += (read_c0_ebase() & 0x3ffff000);
2202 if (cpu_has_mmips) {
2203 unsigned int config3 = read_c0_config3();
2205 if (IS_ENABLED(CONFIG_CPU_MICROMIPS))
2206 write_c0_config3(config3 | MIPS_CONF3_ISA_OE);
2208 write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE);
2211 if (board_ebase_setup)
2212 board_ebase_setup();
2213 per_cpu_trap_init(true);
2216 * Copy the generic exception handlers to their final destination.
2217 * This will be overriden later as suitable for a particular
2220 set_handler(0x180, &except_vec3_generic, 0x80);
2223 * Setup default vectors
2225 for (i = 0; i <= 31; i++)
2226 set_except_vector(i, handle_reserved);
2229 * Copy the EJTAG debug exception vector handler code to it's final
2232 if (cpu_has_ejtag && board_ejtag_handler_setup)
2233 board_ejtag_handler_setup();
2236 * Only some CPUs have the watch exceptions.
2239 set_except_vector(EXCCODE_WATCH, handle_watch);
2242 * Initialise interrupt handlers
2244 if (cpu_has_veic || cpu_has_vint) {
2245 int nvec = cpu_has_veic ? 64 : 8;
2246 for (i = 0; i < nvec; i++)
2247 set_vi_handler(i, NULL);
2249 else if (cpu_has_divec)
2250 set_handler(0x200, &except_vec4, 0x8);
2253 * Some CPUs can enable/disable for cache parity detection, but does
2254 * it different ways.
2256 parity_protection_init();
2259 * The Data Bus Errors / Instruction Bus Errors are signaled
2260 * by external hardware. Therefore these two exceptions
2261 * may have board specific handlers.
2266 set_except_vector(EXCCODE_INT, using_rollback_handler() ?
2267 rollback_handle_int : handle_int);
2268 set_except_vector(EXCCODE_MOD, handle_tlbm);
2269 set_except_vector(EXCCODE_TLBL, handle_tlbl);
2270 set_except_vector(EXCCODE_TLBS, handle_tlbs);
2272 set_except_vector(EXCCODE_ADEL, handle_adel);
2273 set_except_vector(EXCCODE_ADES, handle_ades);
2275 set_except_vector(EXCCODE_IBE, handle_ibe);
2276 set_except_vector(EXCCODE_DBE, handle_dbe);
2278 set_except_vector(EXCCODE_SYS, handle_sys);
2279 set_except_vector(EXCCODE_BP, handle_bp);
2280 set_except_vector(EXCCODE_RI, rdhwr_noopt ? handle_ri :
2281 (cpu_has_vtag_icache ?
2282 handle_ri_rdhwr_vivt : handle_ri_rdhwr));
2283 set_except_vector(EXCCODE_CPU, handle_cpu);
2284 set_except_vector(EXCCODE_OV, handle_ov);
2285 set_except_vector(EXCCODE_TR, handle_tr);
2286 set_except_vector(EXCCODE_MSAFPE, handle_msa_fpe);
2288 if (current_cpu_type() == CPU_R6000 ||
2289 current_cpu_type() == CPU_R6000A) {
2291 * The R6000 is the only R-series CPU that features a machine
2292 * check exception (similar to the R4000 cache error) and
2293 * unaligned ldc1/sdc1 exception. The handlers have not been
2294 * written yet. Well, anyway there is no R6000 machine on the
2295 * current list of targets for Linux/MIPS.
2296 * (Duh, crap, there is someone with a triple R6k machine)
2298 //set_except_vector(14, handle_mc);
2299 //set_except_vector(15, handle_ndc);
2303 if (board_nmi_handler_setup)
2304 board_nmi_handler_setup();
2306 if (cpu_has_fpu && !cpu_has_nofpuex)
2307 set_except_vector(EXCCODE_FPE, handle_fpe);
2309 set_except_vector(MIPS_EXCCODE_TLBPAR, handle_ftlb);
2311 if (cpu_has_rixiex) {
2312 set_except_vector(EXCCODE_TLBRI, tlb_do_page_fault_0);
2313 set_except_vector(EXCCODE_TLBXI, tlb_do_page_fault_0);
2316 set_except_vector(EXCCODE_MSADIS, handle_msa);
2317 set_except_vector(EXCCODE_MDMX, handle_mdmx);
2320 set_except_vector(EXCCODE_MCHECK, handle_mcheck);
2323 set_except_vector(EXCCODE_THREAD, handle_mt);
2325 set_except_vector(EXCCODE_DSPDIS, handle_dsp);
2327 if (board_cache_error_setup)
2328 board_cache_error_setup();
2331 /* Special exception: R4[04]00 uses also the divec space. */
2332 set_handler(0x180, &except_vec3_r4000, 0x100);
2333 else if (cpu_has_4kex)
2334 set_handler(0x180, &except_vec3_generic, 0x80);
2336 set_handler(0x080, &except_vec3_generic, 0x80);
2338 local_flush_icache_range(ebase, ebase + 0x400);
2340 sort_extable(__start___dbe_table, __stop___dbe_table);
2342 cu2_notifier(default_cu2_call, 0x80000000); /* Run last */
2345 static int trap_pm_notifier(struct notifier_block *self, unsigned long cmd,
2349 case CPU_PM_ENTER_FAILED:
2353 configure_exception_vector();
2355 /* Restore register with CPU number for TLB handlers */
2356 TLBMISS_HANDLER_RESTORE();
2364 static struct notifier_block trap_pm_notifier_block = {
2365 .notifier_call = trap_pm_notifier,
2368 static int __init trap_pm_init(void)
2370 return cpu_pm_register_notifier(&trap_pm_notifier_block);
2372 arch_initcall(trap_pm_init);