2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
12 * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved.
13 * Copyright (C) 2014, Imagination Technologies Ltd.
15 #include <linux/bitops.h>
16 #include <linux/bug.h>
17 #include <linux/compiler.h>
18 #include <linux/context_tracking.h>
19 #include <linux/cpu_pm.h>
20 #include <linux/kexec.h>
21 #include <linux/init.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/extable.h>
26 #include <linux/sched/mm.h>
27 #include <linux/sched/debug.h>
28 #include <linux/smp.h>
29 #include <linux/spinlock.h>
30 #include <linux/kallsyms.h>
31 #include <linux/bootmem.h>
32 #include <linux/memblock.h>
33 #include <linux/interrupt.h>
34 #include <linux/ptrace.h>
35 #include <linux/kgdb.h>
36 #include <linux/kdebug.h>
37 #include <linux/kprobes.h>
38 #include <linux/notifier.h>
39 #include <linux/kdb.h>
40 #include <linux/irq.h>
41 #include <linux/perf_event.h>
43 #include <asm/addrspace.h>
44 #include <asm/bootinfo.h>
45 #include <asm/branch.h>
46 #include <asm/break.h>
49 #include <asm/cpu-type.h>
52 #include <asm/fpu_emulator.h>
54 #include <asm/mips-cps.h>
55 #include <asm/mips-r2-to-r6-emul.h>
56 #include <asm/mipsregs.h>
57 #include <asm/mipsmtregs.h>
58 #include <asm/module.h>
60 #include <asm/pgtable.h>
61 #include <asm/ptrace.h>
62 #include <asm/sections.h>
63 #include <asm/siginfo.h>
64 #include <asm/tlbdebug.h>
65 #include <asm/traps.h>
66 #include <linux/uaccess.h>
67 #include <asm/watch.h>
68 #include <asm/mmu_context.h>
69 #include <asm/types.h>
70 #include <asm/stacktrace.h>
71 #include <asm/tlbex.h>
74 extern void check_wait(void);
75 extern asmlinkage void rollback_handle_int(void);
76 extern asmlinkage void handle_int(void);
77 extern asmlinkage void handle_adel(void);
78 extern asmlinkage void handle_ades(void);
79 extern asmlinkage void handle_ibe(void);
80 extern asmlinkage void handle_dbe(void);
81 extern asmlinkage void handle_sys(void);
82 extern asmlinkage void handle_bp(void);
83 extern asmlinkage void handle_ri(void);
84 extern asmlinkage void handle_ri_rdhwr_tlbp(void);
85 extern asmlinkage void handle_ri_rdhwr(void);
86 extern asmlinkage void handle_cpu(void);
87 extern asmlinkage void handle_ov(void);
88 extern asmlinkage void handle_tr(void);
89 extern asmlinkage void handle_msa_fpe(void);
90 extern asmlinkage void handle_fpe(void);
91 extern asmlinkage void handle_ftlb(void);
92 extern asmlinkage void handle_msa(void);
93 extern asmlinkage void handle_mdmx(void);
94 extern asmlinkage void handle_watch(void);
95 extern asmlinkage void handle_mt(void);
96 extern asmlinkage void handle_dsp(void);
97 extern asmlinkage void handle_mcheck(void);
98 extern asmlinkage void handle_reserved(void);
99 extern void tlb_do_page_fault_0(void);
101 void (*board_be_init)(void);
102 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
103 void (*board_nmi_handler_setup)(void);
104 void (*board_ejtag_handler_setup)(void);
105 void (*board_bind_eic_interrupt)(int irq, int regset);
106 void (*board_ebase_setup)(void);
107 void(*board_cache_error_setup)(void);
109 static void show_raw_backtrace(unsigned long reg29)
111 unsigned long *sp = (unsigned long *)(reg29 & ~3);
114 printk("Call Trace:");
115 #ifdef CONFIG_KALLSYMS
118 while (!kstack_end(sp)) {
119 unsigned long __user *p =
120 (unsigned long __user *)(unsigned long)sp++;
121 if (__get_user(addr, p)) {
122 printk(" (Bad stack address)");
125 if (__kernel_text_address(addr))
131 #ifdef CONFIG_KALLSYMS
133 static int __init set_raw_show_trace(char *str)
138 __setup("raw_show_trace", set_raw_show_trace);
141 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs)
143 unsigned long sp = regs->regs[29];
144 unsigned long ra = regs->regs[31];
145 unsigned long pc = regs->cp0_epc;
150 if (raw_show_trace || user_mode(regs) || !__kernel_text_address(pc)) {
151 show_raw_backtrace(sp);
154 printk("Call Trace:\n");
157 pc = unwind_stack(task, &sp, pc, &ra);
163 * This routine abuses get_user()/put_user() to reference pointers
164 * with at least a bit of error checking ...
166 static void show_stacktrace(struct task_struct *task,
167 const struct pt_regs *regs)
169 const int field = 2 * sizeof(unsigned long);
172 unsigned long __user *sp = (unsigned long __user *)regs->regs[29];
176 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
177 if (i && ((i % (64 / field)) == 0)) {
186 if (__get_user(stackdata, sp++)) {
187 pr_cont(" (Bad stack address)");
191 pr_cont(" %0*lx", field, stackdata);
195 show_backtrace(task, regs);
198 void show_stack(struct task_struct *task, unsigned long *sp)
201 mm_segment_t old_fs = get_fs();
203 regs.cp0_status = KSU_KERNEL;
205 regs.regs[29] = (unsigned long)sp;
209 if (task && task != current) {
210 regs.regs[29] = task->thread.reg29;
212 regs.cp0_epc = task->thread.reg31;
213 #ifdef CONFIG_KGDB_KDB
214 } else if (atomic_read(&kgdb_active) != -1 &&
216 memcpy(®s, kdb_current_regs, sizeof(regs));
217 #endif /* CONFIG_KGDB_KDB */
219 prepare_frametrace(®s);
223 * show_stack() deals exclusively with kernel mode, so be sure to access
224 * the stack in the kernel (not user) address space.
227 show_stacktrace(task, ®s);
231 static void show_code(unsigned int __user *pc)
234 unsigned short __user *pc16 = NULL;
238 if ((unsigned long)pc & 1)
239 pc16 = (unsigned short __user *)((unsigned long)pc & ~1);
240 for(i = -3 ; i < 6 ; i++) {
242 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) {
243 pr_cont(" (Bad address in epc)\n");
246 pr_cont("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>'));
251 static void __show_regs(const struct pt_regs *regs)
253 const int field = 2 * sizeof(unsigned long);
254 unsigned int cause = regs->cp0_cause;
255 unsigned int exccode;
258 show_regs_print_info(KERN_DEFAULT);
261 * Saved main processor registers
263 for (i = 0; i < 32; ) {
267 pr_cont(" %0*lx", field, 0UL);
268 else if (i == 26 || i == 27)
269 pr_cont(" %*s", field, "");
271 pr_cont(" %0*lx", field, regs->regs[i]);
278 #ifdef CONFIG_CPU_HAS_SMARTMIPS
279 printk("Acx : %0*lx\n", field, regs->acx);
281 printk("Hi : %0*lx\n", field, regs->hi);
282 printk("Lo : %0*lx\n", field, regs->lo);
285 * Saved cp0 registers
287 printk("epc : %0*lx %pS\n", field, regs->cp0_epc,
288 (void *) regs->cp0_epc);
289 printk("ra : %0*lx %pS\n", field, regs->regs[31],
290 (void *) regs->regs[31]);
292 printk("Status: %08x ", (uint32_t) regs->cp0_status);
295 if (regs->cp0_status & ST0_KUO)
297 if (regs->cp0_status & ST0_IEO)
299 if (regs->cp0_status & ST0_KUP)
301 if (regs->cp0_status & ST0_IEP)
303 if (regs->cp0_status & ST0_KUC)
305 if (regs->cp0_status & ST0_IEC)
307 } else if (cpu_has_4kex) {
308 if (regs->cp0_status & ST0_KX)
310 if (regs->cp0_status & ST0_SX)
312 if (regs->cp0_status & ST0_UX)
314 switch (regs->cp0_status & ST0_KSU) {
319 pr_cont("SUPERVISOR ");
325 pr_cont("BAD_MODE ");
328 if (regs->cp0_status & ST0_ERL)
330 if (regs->cp0_status & ST0_EXL)
332 if (regs->cp0_status & ST0_IE)
337 exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
338 printk("Cause : %08x (ExcCode %02x)\n", cause, exccode);
340 if (1 <= exccode && exccode <= 5)
341 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
343 printk("PrId : %08x (%s)\n", read_c0_prid(),
348 * FIXME: really the generic show_regs should take a const pointer argument.
350 void show_regs(struct pt_regs *regs)
356 void show_registers(struct pt_regs *regs)
358 const int field = 2 * sizeof(unsigned long);
359 mm_segment_t old_fs = get_fs();
363 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n",
364 current->comm, current->pid, current_thread_info(), current,
365 field, current_thread_info()->tp_value);
366 if (cpu_has_userlocal) {
369 tls = read_c0_userlocal();
370 if (tls != current_thread_info()->tp_value)
371 printk("*HwTLS: %0*lx\n", field, tls);
374 if (!user_mode(regs))
375 /* Necessary for getting the correct stack content */
377 show_stacktrace(current, regs);
378 show_code((unsigned int __user *) regs->cp0_epc);
383 static DEFINE_RAW_SPINLOCK(die_lock);
385 void __noreturn die(const char *str, struct pt_regs *regs)
387 static int die_counter;
392 if (notify_die(DIE_OOPS, str, regs, 0, current->thread.trap_nr,
393 SIGSEGV) == NOTIFY_STOP)
397 raw_spin_lock_irq(&die_lock);
400 printk("%s[#%d]:\n", str, ++die_counter);
401 show_registers(regs);
402 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
403 raw_spin_unlock_irq(&die_lock);
408 panic("Fatal exception in interrupt");
411 panic("Fatal exception");
413 if (regs && kexec_should_crash(current))
419 extern struct exception_table_entry __start___dbe_table[];
420 extern struct exception_table_entry __stop___dbe_table[];
423 " .section __dbe_table, \"a\"\n"
426 /* Given an address, look for it in the exception tables. */
427 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
429 const struct exception_table_entry *e;
431 e = search_extable(__start___dbe_table,
432 __stop___dbe_table - __start___dbe_table, addr);
434 e = search_module_dbetables(addr);
438 asmlinkage void do_be(struct pt_regs *regs)
440 const int field = 2 * sizeof(unsigned long);
441 const struct exception_table_entry *fixup = NULL;
442 int data = regs->cp0_cause & 4;
443 int action = MIPS_BE_FATAL;
444 enum ctx_state prev_state;
446 prev_state = exception_enter();
447 /* XXX For now. Fixme, this searches the wrong table ... */
448 if (data && !user_mode(regs))
449 fixup = search_dbe_tables(exception_epc(regs));
452 action = MIPS_BE_FIXUP;
454 if (board_be_handler)
455 action = board_be_handler(regs, fixup != NULL);
457 mips_cm_error_report();
460 case MIPS_BE_DISCARD:
464 regs->cp0_epc = fixup->nextinsn;
473 * Assume it would be too dangerous to continue ...
475 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
476 data ? "Data" : "Instruction",
477 field, regs->cp0_epc, field, regs->regs[31]);
478 if (notify_die(DIE_OOPS, "bus error", regs, 0, current->thread.trap_nr,
479 SIGBUS) == NOTIFY_STOP)
482 die_if_kernel("Oops", regs);
483 force_sig(SIGBUS, current);
486 exception_exit(prev_state);
490 * ll/sc, rdhwr, sync emulation
493 #define OPCODE 0xfc000000
494 #define BASE 0x03e00000
495 #define RT 0x001f0000
496 #define OFFSET 0x0000ffff
497 #define LL 0xc0000000
498 #define SC 0xe0000000
499 #define SPEC0 0x00000000
500 #define SPEC3 0x7c000000
501 #define RD 0x0000f800
502 #define FUNC 0x0000003f
503 #define SYNC 0x0000000f
504 #define RDHWR 0x0000003b
506 /* microMIPS definitions */
507 #define MM_POOL32A_FUNC 0xfc00ffff
508 #define MM_RDHWR 0x00006b3c
509 #define MM_RS 0x001f0000
510 #define MM_RT 0x03e00000
513 * The ll_bit is cleared by r*_switch.S
517 struct task_struct *ll_task;
519 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)
521 unsigned long value, __user *vaddr;
525 * analyse the ll instruction that just caused a ri exception
526 * and put the referenced address to addr.
529 /* sign extend offset */
530 offset = opcode & OFFSET;
534 vaddr = (unsigned long __user *)
535 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
537 if ((unsigned long)vaddr & 3)
539 if (get_user(value, vaddr))
544 if (ll_task == NULL || ll_task == current) {
553 regs->regs[(opcode & RT) >> 16] = value;
558 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
560 unsigned long __user *vaddr;
565 * analyse the sc instruction that just caused a ri exception
566 * and put the referenced address to addr.
569 /* sign extend offset */
570 offset = opcode & OFFSET;
574 vaddr = (unsigned long __user *)
575 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
576 reg = (opcode & RT) >> 16;
578 if ((unsigned long)vaddr & 3)
583 if (ll_bit == 0 || ll_task != current) {
591 if (put_user(regs->regs[reg], vaddr))
600 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
601 * opcodes are supposed to result in coprocessor unusable exceptions if
602 * executed on ll/sc-less processors. That's the theory. In practice a
603 * few processors such as NEC's VR4100 throw reserved instruction exceptions
604 * instead, so we're doing the emulation thing in both exception handlers.
606 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
608 if ((opcode & OPCODE) == LL) {
609 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
611 return simulate_ll(regs, opcode);
613 if ((opcode & OPCODE) == SC) {
614 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
616 return simulate_sc(regs, opcode);
619 return -1; /* Must be something else ... */
623 * Simulate trapping 'rdhwr' instructions to provide user accessible
624 * registers not implemented in hardware.
626 static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt)
628 struct thread_info *ti = task_thread_info(current);
630 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
633 case MIPS_HWR_CPUNUM: /* CPU number */
634 regs->regs[rt] = smp_processor_id();
636 case MIPS_HWR_SYNCISTEP: /* SYNCI length */
637 regs->regs[rt] = min(current_cpu_data.dcache.linesz,
638 current_cpu_data.icache.linesz);
640 case MIPS_HWR_CC: /* Read count register */
641 regs->regs[rt] = read_c0_count();
643 case MIPS_HWR_CCRES: /* Count register resolution */
644 switch (current_cpu_type()) {
653 case MIPS_HWR_ULR: /* Read UserLocal register */
654 regs->regs[rt] = ti->tp_value;
661 static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode)
663 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
664 int rd = (opcode & RD) >> 11;
665 int rt = (opcode & RT) >> 16;
667 simulate_rdhwr(regs, rd, rt);
675 static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned int opcode)
677 if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) {
678 int rd = (opcode & MM_RS) >> 16;
679 int rt = (opcode & MM_RT) >> 21;
680 simulate_rdhwr(regs, rd, rt);
688 static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
690 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) {
691 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
696 return -1; /* Must be something else ... */
699 asmlinkage void do_ov(struct pt_regs *regs)
701 enum ctx_state prev_state;
703 prev_state = exception_enter();
704 die_if_kernel("Integer overflow", regs);
706 force_sig_fault(SIGFPE, FPE_INTOVF, (void __user *)regs->cp0_epc, current);
707 exception_exit(prev_state);
711 * Send SIGFPE according to FCSR Cause bits, which must have already
712 * been masked against Enable bits. This is impotant as Inexact can
713 * happen together with Overflow or Underflow, and `ptrace' can set
716 void force_fcr31_sig(unsigned long fcr31, void __user *fault_addr,
717 struct task_struct *tsk)
719 int si_code = FPE_FLTUNK;
721 if (fcr31 & FPU_CSR_INV_X)
722 si_code = FPE_FLTINV;
723 else if (fcr31 & FPU_CSR_DIV_X)
724 si_code = FPE_FLTDIV;
725 else if (fcr31 & FPU_CSR_OVF_X)
726 si_code = FPE_FLTOVF;
727 else if (fcr31 & FPU_CSR_UDF_X)
728 si_code = FPE_FLTUND;
729 else if (fcr31 & FPU_CSR_INE_X)
730 si_code = FPE_FLTRES;
732 force_sig_fault(SIGFPE, si_code, fault_addr, tsk);
735 int process_fpemu_return(int sig, void __user *fault_addr, unsigned long fcr31)
738 struct vm_area_struct *vma;
745 force_fcr31_sig(fcr31, fault_addr, current);
749 force_sig_fault(SIGBUS, BUS_ADRERR, fault_addr, current);
753 down_read(¤t->mm->mmap_sem);
754 vma = find_vma(current->mm, (unsigned long)fault_addr);
755 if (vma && (vma->vm_start <= (unsigned long)fault_addr))
756 si_code = SEGV_ACCERR;
758 si_code = SEGV_MAPERR;
759 up_read(¤t->mm->mmap_sem);
760 force_sig_fault(SIGSEGV, si_code, fault_addr, current);
764 force_sig(sig, current);
769 static int simulate_fp(struct pt_regs *regs, unsigned int opcode,
770 unsigned long old_epc, unsigned long old_ra)
772 union mips_instruction inst = { .word = opcode };
773 void __user *fault_addr;
777 /* If it's obviously not an FP instruction, skip it */
778 switch (inst.i_format.opcode) {
792 * do_ri skipped over the instruction via compute_return_epc, undo
793 * that for the FPU emulator.
795 regs->cp0_epc = old_epc;
796 regs->regs[31] = old_ra;
798 /* Save the FP context to struct thread_struct */
801 /* Run the emulator */
802 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1,
806 * We can't allow the emulated instruction to leave any
807 * enabled Cause bits set in $fcr31.
809 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31);
810 current->thread.fpu.fcr31 &= ~fcr31;
812 /* Restore the hardware register state */
815 /* Send a signal if required. */
816 process_fpemu_return(sig, fault_addr, fcr31);
822 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
824 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
826 enum ctx_state prev_state;
827 void __user *fault_addr;
830 prev_state = exception_enter();
831 if (notify_die(DIE_FP, "FP exception", regs, 0, current->thread.trap_nr,
832 SIGFPE) == NOTIFY_STOP)
835 /* Clear FCSR.Cause before enabling interrupts */
836 write_32bit_cp1_register(CP1_STATUS, fcr31 & ~mask_fcr31_x(fcr31));
839 die_if_kernel("FP exception in kernel code", regs);
841 if (fcr31 & FPU_CSR_UNI_X) {
843 * Unimplemented operation exception. If we've got the full
844 * software emulator on-board, let's use it...
846 * Force FPU to dump state into task/thread context. We're
847 * moving a lot of data here for what is probably a single
848 * instruction, but the alternative is to pre-decode the FP
849 * register operands before invoking the emulator, which seems
850 * a bit extreme for what should be an infrequent event.
852 /* Ensure 'resume' not overwrite saved fp context again. */
855 /* Run the emulator */
856 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1,
860 * We can't allow the emulated instruction to leave any
861 * enabled Cause bits set in $fcr31.
863 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31);
864 current->thread.fpu.fcr31 &= ~fcr31;
866 /* Restore the hardware register state */
867 own_fpu(1); /* Using the FPU again. */
870 fault_addr = (void __user *) regs->cp0_epc;
873 /* Send a signal if required. */
874 process_fpemu_return(sig, fault_addr, fcr31);
877 exception_exit(prev_state);
880 void do_trap_or_bp(struct pt_regs *regs, unsigned int code, int si_code,
885 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
886 if (kgdb_ll_trap(DIE_TRAP, str, regs, code, current->thread.trap_nr,
887 SIGTRAP) == NOTIFY_STOP)
889 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
891 if (notify_die(DIE_TRAP, str, regs, code, current->thread.trap_nr,
892 SIGTRAP) == NOTIFY_STOP)
896 * A short test says that IRIX 5.3 sends SIGTRAP for all trap
897 * insns, even for trap and break codes that indicate arithmetic
898 * failures. Weird ...
899 * But should we continue the brokenness??? --macro
904 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
905 die_if_kernel(b, regs);
906 force_sig_fault(SIGFPE,
907 code == BRK_DIVZERO ? FPE_INTDIV : FPE_INTOVF,
908 (void __user *) regs->cp0_epc, current);
911 die_if_kernel("Kernel bug detected", regs);
912 force_sig(SIGTRAP, current);
916 * This breakpoint code is used by the FPU emulator to retake
917 * control of the CPU after executing the instruction from the
918 * delay slot of an emulated branch.
920 * Terminate if exception was recognized as a delay slot return
921 * otherwise handle as normal.
923 if (do_dsemulret(regs))
926 die_if_kernel("Math emu break/trap", regs);
927 force_sig(SIGTRAP, current);
930 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
931 die_if_kernel(b, regs);
933 force_sig_fault(SIGTRAP, si_code, NULL, current);
935 force_sig(SIGTRAP, current);
940 asmlinkage void do_bp(struct pt_regs *regs)
942 unsigned long epc = msk_isa16_mode(exception_epc(regs));
943 unsigned int opcode, bcode;
944 enum ctx_state prev_state;
948 if (!user_mode(regs))
951 prev_state = exception_enter();
952 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
953 if (get_isa16_mode(regs->cp0_epc)) {
956 if (__get_user(instr[0], (u16 __user *)epc))
959 if (!cpu_has_mmips) {
961 bcode = (instr[0] >> 5) & 0x3f;
962 } else if (mm_insn_16bit(instr[0])) {
963 /* 16-bit microMIPS BREAK */
964 bcode = instr[0] & 0xf;
966 /* 32-bit microMIPS BREAK */
967 if (__get_user(instr[1], (u16 __user *)(epc + 2)))
969 opcode = (instr[0] << 16) | instr[1];
970 bcode = (opcode >> 6) & ((1 << 20) - 1);
973 if (__get_user(opcode, (unsigned int __user *)epc))
975 bcode = (opcode >> 6) & ((1 << 20) - 1);
979 * There is the ancient bug in the MIPS assemblers that the break
980 * code starts left to bit 16 instead to bit 6 in the opcode.
981 * Gas is bug-compatible, but not always, grrr...
982 * We handle both cases with a simple heuristics. --macro
984 if (bcode >= (1 << 10))
985 bcode = ((bcode & ((1 << 10) - 1)) << 10) | (bcode >> 10);
988 * notify the kprobe handlers, if instruction is likely to
993 if (notify_die(DIE_UPROBE, "uprobe", regs, bcode,
994 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
999 if (notify_die(DIE_UPROBE_XOL, "uprobe_xol", regs, bcode,
1000 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1005 if (notify_die(DIE_BREAK, "debug", regs, bcode,
1006 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1010 case BRK_KPROBE_SSTEPBP:
1011 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode,
1012 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1020 do_trap_or_bp(regs, bcode, TRAP_BRKPT, "Break");
1024 exception_exit(prev_state);
1028 force_sig(SIGSEGV, current);
1032 asmlinkage void do_tr(struct pt_regs *regs)
1034 u32 opcode, tcode = 0;
1035 enum ctx_state prev_state;
1038 unsigned long epc = msk_isa16_mode(exception_epc(regs));
1041 if (!user_mode(regs))
1044 prev_state = exception_enter();
1045 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
1046 if (get_isa16_mode(regs->cp0_epc)) {
1047 if (__get_user(instr[0], (u16 __user *)(epc + 0)) ||
1048 __get_user(instr[1], (u16 __user *)(epc + 2)))
1050 opcode = (instr[0] << 16) | instr[1];
1051 /* Immediate versions don't provide a code. */
1052 if (!(opcode & OPCODE))
1053 tcode = (opcode >> 12) & ((1 << 4) - 1);
1055 if (__get_user(opcode, (u32 __user *)epc))
1057 /* Immediate versions don't provide a code. */
1058 if (!(opcode & OPCODE))
1059 tcode = (opcode >> 6) & ((1 << 10) - 1);
1062 do_trap_or_bp(regs, tcode, 0, "Trap");
1066 exception_exit(prev_state);
1070 force_sig(SIGSEGV, current);
1074 asmlinkage void do_ri(struct pt_regs *regs)
1076 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs);
1077 unsigned long old_epc = regs->cp0_epc;
1078 unsigned long old31 = regs->regs[31];
1079 enum ctx_state prev_state;
1080 unsigned int opcode = 0;
1084 * Avoid any kernel code. Just emulate the R2 instruction
1085 * as quickly as possible.
1087 if (mipsr2_emulation && cpu_has_mips_r6 &&
1088 likely(user_mode(regs)) &&
1089 likely(get_user(opcode, epc) >= 0)) {
1090 unsigned long fcr31 = 0;
1092 status = mipsr2_decoder(regs, opcode, &fcr31);
1100 process_fpemu_return(status,
1101 ¤t->thread.cp0_baduaddr,
1109 prev_state = exception_enter();
1110 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
1112 if (notify_die(DIE_RI, "RI Fault", regs, 0, current->thread.trap_nr,
1113 SIGILL) == NOTIFY_STOP)
1116 die_if_kernel("Reserved instruction in kernel code", regs);
1118 if (unlikely(compute_return_epc(regs) < 0))
1121 if (!get_isa16_mode(regs->cp0_epc)) {
1122 if (unlikely(get_user(opcode, epc) < 0))
1125 if (!cpu_has_llsc && status < 0)
1126 status = simulate_llsc(regs, opcode);
1129 status = simulate_rdhwr_normal(regs, opcode);
1132 status = simulate_sync(regs, opcode);
1135 status = simulate_fp(regs, opcode, old_epc, old31);
1136 } else if (cpu_has_mmips) {
1137 unsigned short mmop[2] = { 0 };
1139 if (unlikely(get_user(mmop[0], (u16 __user *)epc + 0) < 0))
1141 if (unlikely(get_user(mmop[1], (u16 __user *)epc + 1) < 0))
1144 opcode = (opcode << 16) | mmop[1];
1147 status = simulate_rdhwr_mm(regs, opcode);
1153 if (unlikely(status > 0)) {
1154 regs->cp0_epc = old_epc; /* Undo skip-over. */
1155 regs->regs[31] = old31;
1156 force_sig(status, current);
1160 exception_exit(prev_state);
1164 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
1165 * emulated more than some threshold number of instructions, force migration to
1166 * a "CPU" that has FP support.
1168 static void mt_ase_fp_affinity(void)
1170 #ifdef CONFIG_MIPS_MT_FPAFF
1171 if (mt_fpemul_threshold > 0 &&
1172 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) {
1174 * If there's no FPU present, or if the application has already
1175 * restricted the allowed set to exclude any CPUs with FPUs,
1176 * we'll skip the procedure.
1178 if (cpumask_intersects(¤t->cpus_allowed, &mt_fpu_cpumask)) {
1181 current->thread.user_cpus_allowed
1182 = current->cpus_allowed;
1183 cpumask_and(&tmask, ¤t->cpus_allowed,
1185 set_cpus_allowed_ptr(current, &tmask);
1186 set_thread_flag(TIF_FPUBOUND);
1189 #endif /* CONFIG_MIPS_MT_FPAFF */
1193 * No lock; only written during early bootup by CPU 0.
1195 static RAW_NOTIFIER_HEAD(cu2_chain);
1197 int __ref register_cu2_notifier(struct notifier_block *nb)
1199 return raw_notifier_chain_register(&cu2_chain, nb);
1202 int cu2_notifier_call_chain(unsigned long val, void *v)
1204 return raw_notifier_call_chain(&cu2_chain, val, v);
1207 static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
1210 struct pt_regs *regs = data;
1212 die_if_kernel("COP2: Unhandled kernel unaligned access or invalid "
1213 "instruction", regs);
1214 force_sig(SIGILL, current);
1219 static int enable_restore_fp_context(int msa)
1221 int err, was_fpu_owner, prior_msa;
1224 /* First time FP context user. */
1230 set_thread_flag(TIF_USEDMSA);
1231 set_thread_flag(TIF_MSA_CTX_LIVE);
1240 * This task has formerly used the FP context.
1242 * If this thread has no live MSA vector context then we can simply
1243 * restore the scalar FP context. If it has live MSA vector context
1244 * (that is, it has or may have used MSA since last performing a
1245 * function call) then we'll need to restore the vector context. This
1246 * applies even if we're currently only executing a scalar FP
1247 * instruction. This is because if we were to later execute an MSA
1248 * instruction then we'd either have to:
1250 * - Restore the vector context & clobber any registers modified by
1251 * scalar FP instructions between now & then.
1255 * - Not restore the vector context & lose the most significant bits
1256 * of all vector registers.
1258 * Neither of those options is acceptable. We cannot restore the least
1259 * significant bits of the registers now & only restore the most
1260 * significant bits later because the most significant bits of any
1261 * vector registers whose aliased FP register is modified now will have
1262 * been zeroed. We'd have no way to know that when restoring the vector
1263 * context & thus may load an outdated value for the most significant
1264 * bits of a vector register.
1266 if (!msa && !thread_msa_context_live())
1270 * This task is using or has previously used MSA. Thus we require
1271 * that Status.FR == 1.
1274 was_fpu_owner = is_fpu_owner();
1275 err = own_fpu_inatomic(0);
1280 write_msa_csr(current->thread.fpu.msacsr);
1281 set_thread_flag(TIF_USEDMSA);
1284 * If this is the first time that the task is using MSA and it has
1285 * previously used scalar FP in this time slice then we already nave
1286 * FP context which we shouldn't clobber. We do however need to clear
1287 * the upper 64b of each vector register so that this task has no
1288 * opportunity to see data left behind by another.
1290 prior_msa = test_and_set_thread_flag(TIF_MSA_CTX_LIVE);
1291 if (!prior_msa && was_fpu_owner) {
1299 * Restore the least significant 64b of each vector register
1300 * from the existing scalar FP context.
1302 _restore_fp(current);
1305 * The task has not formerly used MSA, so clear the upper 64b
1306 * of each vector register such that it cannot see data left
1307 * behind by another task.
1311 /* We need to restore the vector context. */
1312 restore_msa(current);
1314 /* Restore the scalar FP control & status register */
1316 write_32bit_cp1_register(CP1_STATUS,
1317 current->thread.fpu.fcr31);
1326 asmlinkage void do_cpu(struct pt_regs *regs)
1328 enum ctx_state prev_state;
1329 unsigned int __user *epc;
1330 unsigned long old_epc, old31;
1331 void __user *fault_addr;
1332 unsigned int opcode;
1333 unsigned long fcr31;
1338 prev_state = exception_enter();
1339 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
1342 die_if_kernel("do_cpu invoked from kernel context!", regs);
1346 epc = (unsigned int __user *)exception_epc(regs);
1347 old_epc = regs->cp0_epc;
1348 old31 = regs->regs[31];
1352 if (unlikely(compute_return_epc(regs) < 0))
1355 if (!get_isa16_mode(regs->cp0_epc)) {
1356 if (unlikely(get_user(opcode, epc) < 0))
1359 if (!cpu_has_llsc && status < 0)
1360 status = simulate_llsc(regs, opcode);
1366 if (unlikely(status > 0)) {
1367 regs->cp0_epc = old_epc; /* Undo skip-over. */
1368 regs->regs[31] = old31;
1369 force_sig(status, current);
1376 * The COP3 opcode space and consequently the CP0.Status.CU3
1377 * bit and the CP0.Cause.CE=3 encoding have been removed as
1378 * of the MIPS III ISA. From the MIPS IV and MIPS32r2 ISAs
1379 * up the space has been reused for COP1X instructions, that
1380 * are enabled by the CP0.Status.CU1 bit and consequently
1381 * use the CP0.Cause.CE=1 encoding for Coprocessor Unusable
1382 * exceptions. Some FPU-less processors that implement one
1383 * of these ISAs however use this code erroneously for COP1X
1384 * instructions. Therefore we redirect this trap to the FP
1387 if (raw_cpu_has_fpu || !cpu_has_mips_4_5_64_r2_r6) {
1388 force_sig(SIGILL, current);
1394 err = enable_restore_fp_context(0);
1396 if (raw_cpu_has_fpu && !err)
1399 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 0,
1403 * We can't allow the emulated instruction to leave
1404 * any enabled Cause bits set in $fcr31.
1406 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31);
1407 current->thread.fpu.fcr31 &= ~fcr31;
1409 /* Send a signal if required. */
1410 if (!process_fpemu_return(sig, fault_addr, fcr31) && !err)
1411 mt_ase_fp_affinity();
1416 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
1420 exception_exit(prev_state);
1423 asmlinkage void do_msa_fpe(struct pt_regs *regs, unsigned int msacsr)
1425 enum ctx_state prev_state;
1427 prev_state = exception_enter();
1428 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
1429 if (notify_die(DIE_MSAFP, "MSA FP exception", regs, 0,
1430 current->thread.trap_nr, SIGFPE) == NOTIFY_STOP)
1433 /* Clear MSACSR.Cause before enabling interrupts */
1434 write_msa_csr(msacsr & ~MSA_CSR_CAUSEF);
1437 die_if_kernel("do_msa_fpe invoked from kernel context!", regs);
1438 force_sig(SIGFPE, current);
1440 exception_exit(prev_state);
1443 asmlinkage void do_msa(struct pt_regs *regs)
1445 enum ctx_state prev_state;
1448 prev_state = exception_enter();
1450 if (!cpu_has_msa || test_thread_flag(TIF_32BIT_FPREGS)) {
1451 force_sig(SIGILL, current);
1455 die_if_kernel("do_msa invoked from kernel context!", regs);
1457 err = enable_restore_fp_context(1);
1459 force_sig(SIGILL, current);
1461 exception_exit(prev_state);
1464 asmlinkage void do_mdmx(struct pt_regs *regs)
1466 enum ctx_state prev_state;
1468 prev_state = exception_enter();
1469 force_sig(SIGILL, current);
1470 exception_exit(prev_state);
1474 * Called with interrupts disabled.
1476 asmlinkage void do_watch(struct pt_regs *regs)
1478 enum ctx_state prev_state;
1480 prev_state = exception_enter();
1482 * Clear WP (bit 22) bit of cause register so we don't loop
1485 clear_c0_cause(CAUSEF_WP);
1488 * If the current thread has the watch registers loaded, save
1489 * their values and send SIGTRAP. Otherwise another thread
1490 * left the registers set, clear them and continue.
1492 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
1493 mips_read_watch_registers();
1495 force_sig_fault(SIGTRAP, TRAP_HWBKPT, NULL, current);
1497 mips_clear_watch_registers();
1500 exception_exit(prev_state);
1503 asmlinkage void do_mcheck(struct pt_regs *regs)
1505 int multi_match = regs->cp0_status & ST0_TS;
1506 enum ctx_state prev_state;
1507 mm_segment_t old_fs = get_fs();
1509 prev_state = exception_enter();
1518 if (!user_mode(regs))
1521 show_code((unsigned int __user *) regs->cp0_epc);
1526 * Some chips may have other causes of machine check (e.g. SB1
1529 panic("Caught Machine Check exception - %scaused by multiple "
1530 "matching entries in the TLB.",
1531 (multi_match) ? "" : "not ");
1534 asmlinkage void do_mt(struct pt_regs *regs)
1538 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
1539 >> VPECONTROL_EXCPT_SHIFT;
1542 printk(KERN_DEBUG "Thread Underflow\n");
1545 printk(KERN_DEBUG "Thread Overflow\n");
1548 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
1551 printk(KERN_DEBUG "Gating Storage Exception\n");
1554 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
1557 printk(KERN_DEBUG "Gating Storage Scheduler Exception\n");
1560 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
1564 die_if_kernel("MIPS MT Thread exception in kernel", regs);
1566 force_sig(SIGILL, current);
1570 asmlinkage void do_dsp(struct pt_regs *regs)
1573 panic("Unexpected DSP exception");
1575 force_sig(SIGILL, current);
1578 asmlinkage void do_reserved(struct pt_regs *regs)
1581 * Game over - no way to handle this if it ever occurs. Most probably
1582 * caused by a new unknown cpu type or after another deadly
1583 * hard/software error.
1586 panic("Caught reserved exception %ld - should not happen.",
1587 (regs->cp0_cause & 0x7f) >> 2);
1590 static int __initdata l1parity = 1;
1591 static int __init nol1parity(char *s)
1596 __setup("nol1par", nol1parity);
1597 static int __initdata l2parity = 1;
1598 static int __init nol2parity(char *s)
1603 __setup("nol2par", nol2parity);
1606 * Some MIPS CPUs can enable/disable for cache parity detection, but do
1607 * it different ways.
1609 static inline void parity_protection_init(void)
1611 #define ERRCTL_PE 0x80000000
1612 #define ERRCTL_L2P 0x00800000
1614 if (mips_cm_revision() >= CM_REV_CM3) {
1615 ulong gcr_ectl, cp0_ectl;
1618 * With CM3 systems we need to ensure that the L1 & L2
1619 * parity enables are set to the same value, since this
1620 * is presumed by the hardware engineers.
1622 * If the user disabled either of L1 or L2 ECC checking,
1625 l1parity &= l2parity;
1626 l2parity &= l1parity;
1628 /* Probe L1 ECC support */
1629 cp0_ectl = read_c0_ecc();
1630 write_c0_ecc(cp0_ectl | ERRCTL_PE);
1631 back_to_back_c0_hazard();
1632 cp0_ectl = read_c0_ecc();
1634 /* Probe L2 ECC support */
1635 gcr_ectl = read_gcr_err_control();
1637 if (!(gcr_ectl & CM_GCR_ERR_CONTROL_L2_ECC_SUPPORT) ||
1638 !(cp0_ectl & ERRCTL_PE)) {
1640 * One of L1 or L2 ECC checking isn't supported,
1641 * so we cannot enable either.
1643 l1parity = l2parity = 0;
1646 /* Configure L1 ECC checking */
1648 cp0_ectl |= ERRCTL_PE;
1650 cp0_ectl &= ~ERRCTL_PE;
1651 write_c0_ecc(cp0_ectl);
1652 back_to_back_c0_hazard();
1653 WARN_ON(!!(read_c0_ecc() & ERRCTL_PE) != l1parity);
1655 /* Configure L2 ECC checking */
1657 gcr_ectl |= CM_GCR_ERR_CONTROL_L2_ECC_EN;
1659 gcr_ectl &= ~CM_GCR_ERR_CONTROL_L2_ECC_EN;
1660 write_gcr_err_control(gcr_ectl);
1661 gcr_ectl = read_gcr_err_control();
1662 gcr_ectl &= CM_GCR_ERR_CONTROL_L2_ECC_EN;
1663 WARN_ON(!!gcr_ectl != l2parity);
1665 pr_info("Cache parity protection %sabled\n",
1666 l1parity ? "en" : "dis");
1670 switch (current_cpu_type()) {
1676 case CPU_INTERAPTIV:
1679 case CPU_QEMU_GENERIC:
1682 unsigned long errctl;
1683 unsigned int l1parity_present, l2parity_present;
1685 errctl = read_c0_ecc();
1686 errctl &= ~(ERRCTL_PE|ERRCTL_L2P);
1688 /* probe L1 parity support */
1689 write_c0_ecc(errctl | ERRCTL_PE);
1690 back_to_back_c0_hazard();
1691 l1parity_present = (read_c0_ecc() & ERRCTL_PE);
1693 /* probe L2 parity support */
1694 write_c0_ecc(errctl|ERRCTL_L2P);
1695 back_to_back_c0_hazard();
1696 l2parity_present = (read_c0_ecc() & ERRCTL_L2P);
1698 if (l1parity_present && l2parity_present) {
1700 errctl |= ERRCTL_PE;
1701 if (l1parity ^ l2parity)
1702 errctl |= ERRCTL_L2P;
1703 } else if (l1parity_present) {
1705 errctl |= ERRCTL_PE;
1706 } else if (l2parity_present) {
1708 errctl |= ERRCTL_L2P;
1710 /* No parity available */
1713 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl);
1715 write_c0_ecc(errctl);
1716 back_to_back_c0_hazard();
1717 errctl = read_c0_ecc();
1718 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl);
1720 if (l1parity_present)
1721 printk(KERN_INFO "Cache parity protection %sabled\n",
1722 (errctl & ERRCTL_PE) ? "en" : "dis");
1724 if (l2parity_present) {
1725 if (l1parity_present && l1parity)
1726 errctl ^= ERRCTL_L2P;
1727 printk(KERN_INFO "L2 cache parity protection %sabled\n",
1728 (errctl & ERRCTL_L2P) ? "en" : "dis");
1736 write_c0_ecc(0x80000000);
1737 back_to_back_c0_hazard();
1738 /* Set the PE bit (bit 31) in the c0_errctl register. */
1739 printk(KERN_INFO "Cache parity protection %sabled\n",
1740 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
1744 /* Clear the DE bit (bit 16) in the c0_status register. */
1745 printk(KERN_INFO "Enable cache parity protection for "
1746 "MIPS 20KC/25KF CPUs.\n");
1747 clear_c0_status(ST0_DE);
1754 asmlinkage void cache_parity_error(void)
1756 const int field = 2 * sizeof(unsigned long);
1757 unsigned int reg_val;
1759 /* For the moment, report the problem and hang. */
1760 printk("Cache error exception:\n");
1761 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1762 reg_val = read_c0_cacheerr();
1763 printk("c0_cacheerr == %08x\n", reg_val);
1765 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1766 reg_val & (1<<30) ? "secondary" : "primary",
1767 reg_val & (1<<31) ? "data" : "insn");
1768 if ((cpu_has_mips_r2_r6) &&
1769 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) {
1770 pr_err("Error bits: %s%s%s%s%s%s%s%s\n",
1771 reg_val & (1<<29) ? "ED " : "",
1772 reg_val & (1<<28) ? "ET " : "",
1773 reg_val & (1<<27) ? "ES " : "",
1774 reg_val & (1<<26) ? "EE " : "",
1775 reg_val & (1<<25) ? "EB " : "",
1776 reg_val & (1<<24) ? "EI " : "",
1777 reg_val & (1<<23) ? "E1 " : "",
1778 reg_val & (1<<22) ? "E0 " : "");
1780 pr_err("Error bits: %s%s%s%s%s%s%s\n",
1781 reg_val & (1<<29) ? "ED " : "",
1782 reg_val & (1<<28) ? "ET " : "",
1783 reg_val & (1<<26) ? "EE " : "",
1784 reg_val & (1<<25) ? "EB " : "",
1785 reg_val & (1<<24) ? "EI " : "",
1786 reg_val & (1<<23) ? "E1 " : "",
1787 reg_val & (1<<22) ? "E0 " : "");
1789 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1791 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1792 if (reg_val & (1<<22))
1793 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1795 if (reg_val & (1<<23))
1796 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1799 panic("Can't handle the cache error!");
1802 asmlinkage void do_ftlb(void)
1804 const int field = 2 * sizeof(unsigned long);
1805 unsigned int reg_val;
1807 /* For the moment, report the problem and hang. */
1808 if ((cpu_has_mips_r2_r6) &&
1809 (((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS) ||
1810 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_LOONGSON))) {
1811 pr_err("FTLB error exception, cp0_ecc=0x%08x:\n",
1813 pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1814 reg_val = read_c0_cacheerr();
1815 pr_err("c0_cacheerr == %08x\n", reg_val);
1817 if ((reg_val & 0xc0000000) == 0xc0000000) {
1818 pr_err("Decoded c0_cacheerr: FTLB parity error\n");
1820 pr_err("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1821 reg_val & (1<<30) ? "secondary" : "primary",
1822 reg_val & (1<<31) ? "data" : "insn");
1825 pr_err("FTLB error exception\n");
1827 /* Just print the cacheerr bits for now */
1828 cache_parity_error();
1832 * SDBBP EJTAG debug exception handler.
1833 * We skip the instruction and return to the next instruction.
1835 void ejtag_exception_handler(struct pt_regs *regs)
1837 const int field = 2 * sizeof(unsigned long);
1838 unsigned long depc, old_epc, old_ra;
1841 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1842 depc = read_c0_depc();
1843 debug = read_c0_debug();
1844 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
1845 if (debug & 0x80000000) {
1847 * In branch delay slot.
1848 * We cheat a little bit here and use EPC to calculate the
1849 * debug return address (DEPC). EPC is restored after the
1852 old_epc = regs->cp0_epc;
1853 old_ra = regs->regs[31];
1854 regs->cp0_epc = depc;
1855 compute_return_epc(regs);
1856 depc = regs->cp0_epc;
1857 regs->cp0_epc = old_epc;
1858 regs->regs[31] = old_ra;
1861 write_c0_depc(depc);
1864 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1865 write_c0_debug(debug | 0x100);
1870 * NMI exception handler.
1871 * No lock; only written during early bootup by CPU 0.
1873 static RAW_NOTIFIER_HEAD(nmi_chain);
1875 int register_nmi_notifier(struct notifier_block *nb)
1877 return raw_notifier_chain_register(&nmi_chain, nb);
1880 void __noreturn nmi_exception_handler(struct pt_regs *regs)
1885 raw_notifier_call_chain(&nmi_chain, 0, regs);
1887 snprintf(str, 100, "CPU%d NMI taken, CP0_EPC=%lx\n",
1888 smp_processor_id(), regs->cp0_epc);
1889 regs->cp0_epc = read_c0_errorepc();
1894 #define VECTORSPACING 0x100 /* for EI/VI mode */
1896 unsigned long ebase;
1897 EXPORT_SYMBOL_GPL(ebase);
1898 unsigned long exception_handlers[32];
1899 unsigned long vi_handlers[64];
1901 void __init *set_except_vector(int n, void *addr)
1903 unsigned long handler = (unsigned long) addr;
1904 unsigned long old_handler;
1906 #ifdef CONFIG_CPU_MICROMIPS
1908 * Only the TLB handlers are cache aligned with an even
1909 * address. All other handlers are on an odd address and
1910 * require no modification. Otherwise, MIPS32 mode will
1911 * be entered when handling any TLB exceptions. That
1912 * would be bad...since we must stay in microMIPS mode.
1914 if (!(handler & 0x1))
1917 old_handler = xchg(&exception_handlers[n], handler);
1919 if (n == 0 && cpu_has_divec) {
1920 #ifdef CONFIG_CPU_MICROMIPS
1921 unsigned long jump_mask = ~((1 << 27) - 1);
1923 unsigned long jump_mask = ~((1 << 28) - 1);
1925 u32 *buf = (u32 *)(ebase + 0x200);
1926 unsigned int k0 = 26;
1927 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) {
1928 uasm_i_j(&buf, handler & ~jump_mask);
1931 UASM_i_LA(&buf, k0, handler);
1932 uasm_i_jr(&buf, k0);
1935 local_flush_icache_range(ebase + 0x200, (unsigned long)buf);
1937 return (void *)old_handler;
1940 static void do_default_vi(void)
1942 show_regs(get_irq_regs());
1943 panic("Caught unexpected vectored interrupt.");
1946 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1948 unsigned long handler;
1949 unsigned long old_handler = vi_handlers[n];
1950 int srssets = current_cpu_data.srsets;
1954 BUG_ON(!cpu_has_veic && !cpu_has_vint);
1957 handler = (unsigned long) do_default_vi;
1960 handler = (unsigned long) addr;
1961 vi_handlers[n] = handler;
1963 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1966 panic("Shadow register set %d not supported", srs);
1969 if (board_bind_eic_interrupt)
1970 board_bind_eic_interrupt(n, srs);
1971 } else if (cpu_has_vint) {
1972 /* SRSMap is only defined if shadow sets are implemented */
1974 change_c0_srsmap(0xf << n*4, srs << n*4);
1979 * If no shadow set is selected then use the default handler
1980 * that does normal register saving and standard interrupt exit
1982 extern char except_vec_vi, except_vec_vi_lui;
1983 extern char except_vec_vi_ori, except_vec_vi_end;
1984 extern char rollback_except_vec_vi;
1985 char *vec_start = using_rollback_handler() ?
1986 &rollback_except_vec_vi : &except_vec_vi;
1987 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
1988 const int lui_offset = &except_vec_vi_lui - vec_start + 2;
1989 const int ori_offset = &except_vec_vi_ori - vec_start + 2;
1991 const int lui_offset = &except_vec_vi_lui - vec_start;
1992 const int ori_offset = &except_vec_vi_ori - vec_start;
1994 const int handler_len = &except_vec_vi_end - vec_start;
1996 if (handler_len > VECTORSPACING) {
1998 * Sigh... panicing won't help as the console
1999 * is probably not configured :(
2001 panic("VECTORSPACING too small");
2004 set_handler(((unsigned long)b - ebase), vec_start,
2005 #ifdef CONFIG_CPU_MICROMIPS
2010 h = (u16 *)(b + lui_offset);
2011 *h = (handler >> 16) & 0xffff;
2012 h = (u16 *)(b + ori_offset);
2013 *h = (handler & 0xffff);
2014 local_flush_icache_range((unsigned long)b,
2015 (unsigned long)(b+handler_len));
2019 * In other cases jump directly to the interrupt handler. It
2020 * is the handler's responsibility to save registers if required
2021 * (eg hi/lo) and return from the exception using "eret".
2027 #ifdef CONFIG_CPU_MICROMIPS
2028 insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1);
2030 insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2);
2032 h[0] = (insn >> 16) & 0xffff;
2033 h[1] = insn & 0xffff;
2036 local_flush_icache_range((unsigned long)b,
2037 (unsigned long)(b+8));
2040 return (void *)old_handler;
2043 void *set_vi_handler(int n, vi_handler_t addr)
2045 return set_vi_srs_handler(n, addr, 0);
2048 extern void tlb_init(void);
2053 int cp0_compare_irq;
2054 EXPORT_SYMBOL_GPL(cp0_compare_irq);
2055 int cp0_compare_irq_shift;
2058 * Performance counter IRQ or -1 if shared with timer
2060 int cp0_perfcount_irq;
2061 EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
2064 * Fast debug channel IRQ or -1 if not present
2067 EXPORT_SYMBOL_GPL(cp0_fdc_irq);
2071 static int __init ulri_disable(char *s)
2073 pr_info("Disabling ulri\n");
2078 __setup("noulri", ulri_disable);
2080 /* configure STATUS register */
2081 static void configure_status(void)
2084 * Disable coprocessors and select 32-bit or 64-bit addressing
2085 * and the 16/32 or 32/32 FPR register model. Reset the BEV
2086 * flag that some firmware may have left set and the TS bit (for
2087 * IP27). Set XX for ISA IV code to work.
2089 unsigned int status_set = ST0_CU0;
2091 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
2093 if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV)
2094 status_set |= ST0_XX;
2096 status_set |= ST0_MX;
2098 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
2102 unsigned int hwrena;
2103 EXPORT_SYMBOL_GPL(hwrena);
2105 /* configure HWRENA register */
2106 static void configure_hwrena(void)
2108 hwrena = cpu_hwrena_impl_bits;
2110 if (cpu_has_mips_r2_r6)
2111 hwrena |= MIPS_HWRENA_CPUNUM |
2112 MIPS_HWRENA_SYNCISTEP |
2116 if (!noulri && cpu_has_userlocal)
2117 hwrena |= MIPS_HWRENA_ULR;
2120 write_c0_hwrena(hwrena);
2123 static void configure_exception_vector(void)
2125 if (cpu_has_veic || cpu_has_vint) {
2126 unsigned long sr = set_c0_status(ST0_BEV);
2127 /* If available, use WG to set top bits of EBASE */
2128 if (cpu_has_ebase_wg) {
2130 write_c0_ebase_64(ebase | MIPS_EBASE_WG);
2132 write_c0_ebase(ebase | MIPS_EBASE_WG);
2135 write_c0_ebase(ebase);
2136 write_c0_status(sr);
2137 /* Setting vector spacing enables EI/VI mode */
2138 change_c0_intctl(0x3e0, VECTORSPACING);
2140 if (cpu_has_divec) {
2141 if (cpu_has_mipsmt) {
2142 unsigned int vpflags = dvpe();
2143 set_c0_cause(CAUSEF_IV);
2146 set_c0_cause(CAUSEF_IV);
2150 void per_cpu_trap_init(bool is_boot_cpu)
2152 unsigned int cpu = smp_processor_id();
2157 configure_exception_vector();
2160 * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
2162 * o read IntCtl.IPTI to determine the timer interrupt
2163 * o read IntCtl.IPPCI to determine the performance counter interrupt
2164 * o read IntCtl.IPFDC to determine the fast debug channel interrupt
2166 if (cpu_has_mips_r2_r6) {
2168 * We shouldn't trust a secondary core has a sane EBASE register
2169 * so use the one calculated by the boot CPU.
2172 /* If available, use WG to set top bits of EBASE */
2173 if (cpu_has_ebase_wg) {
2175 write_c0_ebase_64(ebase | MIPS_EBASE_WG);
2177 write_c0_ebase(ebase | MIPS_EBASE_WG);
2180 write_c0_ebase(ebase);
2183 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
2184 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
2185 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
2186 cp0_fdc_irq = (read_c0_intctl() >> INTCTLB_IPFDC) & 7;
2191 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
2192 cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ;
2193 cp0_perfcount_irq = -1;
2197 if (!cpu_data[cpu].asid_cache)
2198 cpu_data[cpu].asid_cache = asid_first_version(cpu);
2201 current->active_mm = &init_mm;
2202 BUG_ON(current->mm);
2203 enter_lazy_tlb(&init_mm, current);
2205 /* Boot CPU's cache setup in setup_arch(). */
2209 TLBMISS_HANDLER_SETUP();
2212 /* Install CPU exception handler */
2213 void set_handler(unsigned long offset, void *addr, unsigned long size)
2215 #ifdef CONFIG_CPU_MICROMIPS
2216 memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size);
2218 memcpy((void *)(ebase + offset), addr, size);
2220 local_flush_icache_range(ebase + offset, ebase + offset + size);
2223 static const char panic_null_cerr[] =
2224 "Trying to set NULL cache error exception handler\n";
2227 * Install uncached CPU exception handler.
2228 * This is suitable only for the cache error exception which is the only
2229 * exception handler that is being run uncached.
2231 void set_uncached_handler(unsigned long offset, void *addr,
2234 unsigned long uncached_ebase = CKSEG1ADDR(ebase);
2237 panic(panic_null_cerr);
2239 memcpy((void *)(uncached_ebase + offset), addr, size);
2242 static int __initdata rdhwr_noopt;
2243 static int __init set_rdhwr_noopt(char *str)
2249 __setup("rdhwr_noopt", set_rdhwr_noopt);
2251 void __init trap_init(void)
2253 extern char except_vec3_generic;
2254 extern char except_vec4;
2255 extern char except_vec3_r4000;
2260 if (cpu_has_veic || cpu_has_vint) {
2261 unsigned long size = 0x200 + VECTORSPACING*64;
2262 phys_addr_t ebase_pa;
2264 memblock_set_bottom_up(true);
2265 ebase = (unsigned long)
2266 __alloc_bootmem(size, 1 << fls(size), 0);
2267 memblock_set_bottom_up(false);
2270 * Try to ensure ebase resides in KSeg0 if possible.
2272 * It shouldn't generally be in XKPhys on MIPS64 to avoid
2273 * hitting a poorly defined exception base for Cache Errors.
2274 * The allocation is likely to be in the low 512MB of physical,
2275 * in which case we should be able to convert to KSeg0.
2277 * EVA is special though as it allows segments to be rearranged
2278 * and to become uncached during cache error handling.
2280 ebase_pa = __pa(ebase);
2281 if (!IS_ENABLED(CONFIG_EVA) && !WARN_ON(ebase_pa >= 0x20000000))
2282 ebase = CKSEG0ADDR(ebase_pa);
2286 if (cpu_has_mips_r2_r6) {
2287 if (cpu_has_ebase_wg) {
2289 ebase = (read_c0_ebase_64() & ~0xfff);
2291 ebase = (read_c0_ebase() & ~0xfff);
2294 ebase += (read_c0_ebase() & 0x3ffff000);
2299 if (cpu_has_mmips) {
2300 unsigned int config3 = read_c0_config3();
2302 if (IS_ENABLED(CONFIG_CPU_MICROMIPS))
2303 write_c0_config3(config3 | MIPS_CONF3_ISA_OE);
2305 write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE);
2308 if (board_ebase_setup)
2309 board_ebase_setup();
2310 per_cpu_trap_init(true);
2313 * Copy the generic exception handlers to their final destination.
2314 * This will be overridden later as suitable for a particular
2317 set_handler(0x180, &except_vec3_generic, 0x80);
2320 * Setup default vectors
2322 for (i = 0; i <= 31; i++)
2323 set_except_vector(i, handle_reserved);
2326 * Copy the EJTAG debug exception vector handler code to it's final
2329 if (cpu_has_ejtag && board_ejtag_handler_setup)
2330 board_ejtag_handler_setup();
2333 * Only some CPUs have the watch exceptions.
2336 set_except_vector(EXCCODE_WATCH, handle_watch);
2339 * Initialise interrupt handlers
2341 if (cpu_has_veic || cpu_has_vint) {
2342 int nvec = cpu_has_veic ? 64 : 8;
2343 for (i = 0; i < nvec; i++)
2344 set_vi_handler(i, NULL);
2346 else if (cpu_has_divec)
2347 set_handler(0x200, &except_vec4, 0x8);
2350 * Some CPUs can enable/disable for cache parity detection, but does
2351 * it different ways.
2353 parity_protection_init();
2356 * The Data Bus Errors / Instruction Bus Errors are signaled
2357 * by external hardware. Therefore these two exceptions
2358 * may have board specific handlers.
2363 set_except_vector(EXCCODE_INT, using_rollback_handler() ?
2364 rollback_handle_int : handle_int);
2365 set_except_vector(EXCCODE_MOD, handle_tlbm);
2366 set_except_vector(EXCCODE_TLBL, handle_tlbl);
2367 set_except_vector(EXCCODE_TLBS, handle_tlbs);
2369 set_except_vector(EXCCODE_ADEL, handle_adel);
2370 set_except_vector(EXCCODE_ADES, handle_ades);
2372 set_except_vector(EXCCODE_IBE, handle_ibe);
2373 set_except_vector(EXCCODE_DBE, handle_dbe);
2375 set_except_vector(EXCCODE_SYS, handle_sys);
2376 set_except_vector(EXCCODE_BP, handle_bp);
2379 set_except_vector(EXCCODE_RI, handle_ri);
2381 if (cpu_has_vtag_icache)
2382 set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp);
2383 else if (current_cpu_type() == CPU_LOONGSON3)
2384 set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp);
2386 set_except_vector(EXCCODE_RI, handle_ri_rdhwr);
2389 set_except_vector(EXCCODE_CPU, handle_cpu);
2390 set_except_vector(EXCCODE_OV, handle_ov);
2391 set_except_vector(EXCCODE_TR, handle_tr);
2392 set_except_vector(EXCCODE_MSAFPE, handle_msa_fpe);
2394 if (board_nmi_handler_setup)
2395 board_nmi_handler_setup();
2397 if (cpu_has_fpu && !cpu_has_nofpuex)
2398 set_except_vector(EXCCODE_FPE, handle_fpe);
2400 set_except_vector(MIPS_EXCCODE_TLBPAR, handle_ftlb);
2402 if (cpu_has_rixiex) {
2403 set_except_vector(EXCCODE_TLBRI, tlb_do_page_fault_0);
2404 set_except_vector(EXCCODE_TLBXI, tlb_do_page_fault_0);
2407 set_except_vector(EXCCODE_MSADIS, handle_msa);
2408 set_except_vector(EXCCODE_MDMX, handle_mdmx);
2411 set_except_vector(EXCCODE_MCHECK, handle_mcheck);
2414 set_except_vector(EXCCODE_THREAD, handle_mt);
2416 set_except_vector(EXCCODE_DSPDIS, handle_dsp);
2418 if (board_cache_error_setup)
2419 board_cache_error_setup();
2422 /* Special exception: R4[04]00 uses also the divec space. */
2423 set_handler(0x180, &except_vec3_r4000, 0x100);
2424 else if (cpu_has_4kex)
2425 set_handler(0x180, &except_vec3_generic, 0x80);
2427 set_handler(0x080, &except_vec3_generic, 0x80);
2429 local_flush_icache_range(ebase, ebase + 0x400);
2431 sort_extable(__start___dbe_table, __stop___dbe_table);
2433 cu2_notifier(default_cu2_call, 0x80000000); /* Run last */
2436 static int trap_pm_notifier(struct notifier_block *self, unsigned long cmd,
2440 case CPU_PM_ENTER_FAILED:
2444 configure_exception_vector();
2446 /* Restore register with CPU number for TLB handlers */
2447 TLBMISS_HANDLER_RESTORE();
2455 static struct notifier_block trap_pm_notifier_block = {
2456 .notifier_call = trap_pm_notifier,
2459 static int __init trap_pm_init(void)
2461 return cpu_pm_register_notifier(&trap_pm_notifier_block);
2463 arch_initcall(trap_pm_init);