2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
12 * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved.
13 * Copyright (C) 2014, Imagination Technologies Ltd.
15 #include <linux/bitops.h>
16 #include <linux/bug.h>
17 #include <linux/compiler.h>
18 #include <linux/context_tracking.h>
19 #include <linux/cpu_pm.h>
20 #include <linux/kexec.h>
21 #include <linux/init.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/extable.h>
26 #include <linux/sched.h>
27 #include <linux/smp.h>
28 #include <linux/spinlock.h>
29 #include <linux/kallsyms.h>
30 #include <linux/bootmem.h>
31 #include <linux/interrupt.h>
32 #include <linux/ptrace.h>
33 #include <linux/kgdb.h>
34 #include <linux/kdebug.h>
35 #include <linux/kprobes.h>
36 #include <linux/notifier.h>
37 #include <linux/kdb.h>
38 #include <linux/irq.h>
39 #include <linux/perf_event.h>
41 #include <asm/addrspace.h>
42 #include <asm/bootinfo.h>
43 #include <asm/branch.h>
44 #include <asm/break.h>
47 #include <asm/cpu-type.h>
50 #include <asm/fpu_emulator.h>
52 #include <asm/mips-cm.h>
53 #include <asm/mips-r2-to-r6-emul.h>
54 #include <asm/mipsregs.h>
55 #include <asm/mipsmtregs.h>
56 #include <asm/module.h>
58 #include <asm/pgtable.h>
59 #include <asm/ptrace.h>
60 #include <asm/sections.h>
61 #include <asm/siginfo.h>
62 #include <asm/tlbdebug.h>
63 #include <asm/traps.h>
64 #include <asm/uaccess.h>
65 #include <asm/watch.h>
66 #include <asm/mmu_context.h>
67 #include <asm/types.h>
68 #include <asm/stacktrace.h>
71 extern void check_wait(void);
72 extern asmlinkage void rollback_handle_int(void);
73 extern asmlinkage void handle_int(void);
74 extern u32 handle_tlbl[];
75 extern u32 handle_tlbs[];
76 extern u32 handle_tlbm[];
77 extern asmlinkage void handle_adel(void);
78 extern asmlinkage void handle_ades(void);
79 extern asmlinkage void handle_ibe(void);
80 extern asmlinkage void handle_dbe(void);
81 extern asmlinkage void handle_sys(void);
82 extern asmlinkage void handle_bp(void);
83 extern asmlinkage void handle_ri(void);
84 extern asmlinkage void handle_ri_rdhwr_vivt(void);
85 extern asmlinkage void handle_ri_rdhwr(void);
86 extern asmlinkage void handle_cpu(void);
87 extern asmlinkage void handle_ov(void);
88 extern asmlinkage void handle_tr(void);
89 extern asmlinkage void handle_msa_fpe(void);
90 extern asmlinkage void handle_fpe(void);
91 extern asmlinkage void handle_ftlb(void);
92 extern asmlinkage void handle_msa(void);
93 extern asmlinkage void handle_mdmx(void);
94 extern asmlinkage void handle_watch(void);
95 extern asmlinkage void handle_mt(void);
96 extern asmlinkage void handle_dsp(void);
97 extern asmlinkage void handle_mcheck(void);
98 extern asmlinkage void handle_reserved(void);
99 extern void tlb_do_page_fault_0(void);
101 void (*board_be_init)(void);
102 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
103 void (*board_nmi_handler_setup)(void);
104 void (*board_ejtag_handler_setup)(void);
105 void (*board_bind_eic_interrupt)(int irq, int regset);
106 void (*board_ebase_setup)(void);
107 void(*board_cache_error_setup)(void);
109 static void show_raw_backtrace(unsigned long reg29)
111 unsigned long *sp = (unsigned long *)(reg29 & ~3);
114 printk("Call Trace:");
115 #ifdef CONFIG_KALLSYMS
118 while (!kstack_end(sp)) {
119 unsigned long __user *p =
120 (unsigned long __user *)(unsigned long)sp++;
121 if (__get_user(addr, p)) {
122 printk(" (Bad stack address)");
125 if (__kernel_text_address(addr))
131 #ifdef CONFIG_KALLSYMS
133 static int __init set_raw_show_trace(char *str)
138 __setup("raw_show_trace", set_raw_show_trace);
141 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs)
143 unsigned long sp = regs->regs[29];
144 unsigned long ra = regs->regs[31];
145 unsigned long pc = regs->cp0_epc;
150 if (raw_show_trace || user_mode(regs) || !__kernel_text_address(pc)) {
151 show_raw_backtrace(sp);
154 printk("Call Trace:\n");
157 pc = unwind_stack(task, &sp, pc, &ra);
163 * This routine abuses get_user()/put_user() to reference pointers
164 * with at least a bit of error checking ...
166 static void show_stacktrace(struct task_struct *task,
167 const struct pt_regs *regs)
169 const int field = 2 * sizeof(unsigned long);
172 unsigned long __user *sp = (unsigned long __user *)regs->regs[29];
176 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
177 if (i && ((i % (64 / field)) == 0))
184 if (__get_user(stackdata, sp++)) {
185 printk(" (Bad stack address)");
189 printk(" %0*lx", field, stackdata);
193 show_backtrace(task, regs);
196 void show_stack(struct task_struct *task, unsigned long *sp)
199 mm_segment_t old_fs = get_fs();
201 regs.regs[29] = (unsigned long)sp;
205 if (task && task != current) {
206 regs.regs[29] = task->thread.reg29;
208 regs.cp0_epc = task->thread.reg31;
209 #ifdef CONFIG_KGDB_KDB
210 } else if (atomic_read(&kgdb_active) != -1 &&
212 memcpy(®s, kdb_current_regs, sizeof(regs));
213 #endif /* CONFIG_KGDB_KDB */
215 prepare_frametrace(®s);
219 * show_stack() deals exclusively with kernel mode, so be sure to access
220 * the stack in the kernel (not user) address space.
223 show_stacktrace(task, ®s);
227 static void show_code(unsigned int __user *pc)
230 unsigned short __user *pc16 = NULL;
234 if ((unsigned long)pc & 1)
235 pc16 = (unsigned short __user *)((unsigned long)pc & ~1);
236 for(i = -3 ; i < 6 ; i++) {
238 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) {
239 printk(" (Bad address in epc)\n");
242 printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>'));
246 static void __show_regs(const struct pt_regs *regs)
248 const int field = 2 * sizeof(unsigned long);
249 unsigned int cause = regs->cp0_cause;
250 unsigned int exccode;
253 show_regs_print_info(KERN_DEFAULT);
256 * Saved main processor registers
258 for (i = 0; i < 32; ) {
262 printk(" %0*lx", field, 0UL);
263 else if (i == 26 || i == 27)
264 printk(" %*s", field, "");
266 printk(" %0*lx", field, regs->regs[i]);
273 #ifdef CONFIG_CPU_HAS_SMARTMIPS
274 printk("Acx : %0*lx\n", field, regs->acx);
276 printk("Hi : %0*lx\n", field, regs->hi);
277 printk("Lo : %0*lx\n", field, regs->lo);
280 * Saved cp0 registers
282 printk("epc : %0*lx %pS\n", field, regs->cp0_epc,
283 (void *) regs->cp0_epc);
284 printk("ra : %0*lx %pS\n", field, regs->regs[31],
285 (void *) regs->regs[31]);
287 printk("Status: %08x ", (uint32_t) regs->cp0_status);
290 if (regs->cp0_status & ST0_KUO)
292 if (regs->cp0_status & ST0_IEO)
294 if (regs->cp0_status & ST0_KUP)
296 if (regs->cp0_status & ST0_IEP)
298 if (regs->cp0_status & ST0_KUC)
300 if (regs->cp0_status & ST0_IEC)
302 } else if (cpu_has_4kex) {
303 if (regs->cp0_status & ST0_KX)
305 if (regs->cp0_status & ST0_SX)
307 if (regs->cp0_status & ST0_UX)
309 switch (regs->cp0_status & ST0_KSU) {
314 printk("SUPERVISOR ");
323 if (regs->cp0_status & ST0_ERL)
325 if (regs->cp0_status & ST0_EXL)
327 if (regs->cp0_status & ST0_IE)
332 exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
333 printk("Cause : %08x (ExcCode %02x)\n", cause, exccode);
335 if (1 <= exccode && exccode <= 5)
336 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
338 printk("PrId : %08x (%s)\n", read_c0_prid(),
343 * FIXME: really the generic show_regs should take a const pointer argument.
345 void show_regs(struct pt_regs *regs)
347 __show_regs((struct pt_regs *)regs);
350 void show_registers(struct pt_regs *regs)
352 const int field = 2 * sizeof(unsigned long);
353 mm_segment_t old_fs = get_fs();
357 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n",
358 current->comm, current->pid, current_thread_info(), current,
359 field, current_thread_info()->tp_value);
360 if (cpu_has_userlocal) {
363 tls = read_c0_userlocal();
364 if (tls != current_thread_info()->tp_value)
365 printk("*HwTLS: %0*lx\n", field, tls);
368 if (!user_mode(regs))
369 /* Necessary for getting the correct stack content */
371 show_stacktrace(current, regs);
372 show_code((unsigned int __user *) regs->cp0_epc);
377 static DEFINE_RAW_SPINLOCK(die_lock);
379 void __noreturn die(const char *str, struct pt_regs *regs)
381 static int die_counter;
386 if (notify_die(DIE_OOPS, str, regs, 0, current->thread.trap_nr,
387 SIGSEGV) == NOTIFY_STOP)
391 raw_spin_lock_irq(&die_lock);
394 printk("%s[#%d]:\n", str, ++die_counter);
395 show_registers(regs);
396 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
397 raw_spin_unlock_irq(&die_lock);
402 panic("Fatal exception in interrupt");
405 panic("Fatal exception");
407 if (regs && kexec_should_crash(current))
413 extern struct exception_table_entry __start___dbe_table[];
414 extern struct exception_table_entry __stop___dbe_table[];
417 " .section __dbe_table, \"a\"\n"
420 /* Given an address, look for it in the exception tables. */
421 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
423 const struct exception_table_entry *e;
425 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
427 e = search_module_dbetables(addr);
431 asmlinkage void do_be(struct pt_regs *regs)
433 const int field = 2 * sizeof(unsigned long);
434 const struct exception_table_entry *fixup = NULL;
435 int data = regs->cp0_cause & 4;
436 int action = MIPS_BE_FATAL;
437 enum ctx_state prev_state;
439 prev_state = exception_enter();
440 /* XXX For now. Fixme, this searches the wrong table ... */
441 if (data && !user_mode(regs))
442 fixup = search_dbe_tables(exception_epc(regs));
445 action = MIPS_BE_FIXUP;
447 if (board_be_handler)
448 action = board_be_handler(regs, fixup != NULL);
450 mips_cm_error_report();
453 case MIPS_BE_DISCARD:
457 regs->cp0_epc = fixup->nextinsn;
466 * Assume it would be too dangerous to continue ...
468 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
469 data ? "Data" : "Instruction",
470 field, regs->cp0_epc, field, regs->regs[31]);
471 if (notify_die(DIE_OOPS, "bus error", regs, 0, current->thread.trap_nr,
472 SIGBUS) == NOTIFY_STOP)
475 die_if_kernel("Oops", regs);
476 force_sig(SIGBUS, current);
479 exception_exit(prev_state);
483 * ll/sc, rdhwr, sync emulation
486 #define OPCODE 0xfc000000
487 #define BASE 0x03e00000
488 #define RT 0x001f0000
489 #define OFFSET 0x0000ffff
490 #define LL 0xc0000000
491 #define SC 0xe0000000
492 #define SPEC0 0x00000000
493 #define SPEC3 0x7c000000
494 #define RD 0x0000f800
495 #define FUNC 0x0000003f
496 #define SYNC 0x0000000f
497 #define RDHWR 0x0000003b
499 /* microMIPS definitions */
500 #define MM_POOL32A_FUNC 0xfc00ffff
501 #define MM_RDHWR 0x00006b3c
502 #define MM_RS 0x001f0000
503 #define MM_RT 0x03e00000
506 * The ll_bit is cleared by r*_switch.S
510 struct task_struct *ll_task;
512 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)
514 unsigned long value, __user *vaddr;
518 * analyse the ll instruction that just caused a ri exception
519 * and put the referenced address to addr.
522 /* sign extend offset */
523 offset = opcode & OFFSET;
527 vaddr = (unsigned long __user *)
528 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
530 if ((unsigned long)vaddr & 3)
532 if (get_user(value, vaddr))
537 if (ll_task == NULL || ll_task == current) {
546 regs->regs[(opcode & RT) >> 16] = value;
551 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
553 unsigned long __user *vaddr;
558 * analyse the sc instruction that just caused a ri exception
559 * and put the referenced address to addr.
562 /* sign extend offset */
563 offset = opcode & OFFSET;
567 vaddr = (unsigned long __user *)
568 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
569 reg = (opcode & RT) >> 16;
571 if ((unsigned long)vaddr & 3)
576 if (ll_bit == 0 || ll_task != current) {
584 if (put_user(regs->regs[reg], vaddr))
593 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
594 * opcodes are supposed to result in coprocessor unusable exceptions if
595 * executed on ll/sc-less processors. That's the theory. In practice a
596 * few processors such as NEC's VR4100 throw reserved instruction exceptions
597 * instead, so we're doing the emulation thing in both exception handlers.
599 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
601 if ((opcode & OPCODE) == LL) {
602 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
604 return simulate_ll(regs, opcode);
606 if ((opcode & OPCODE) == SC) {
607 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
609 return simulate_sc(regs, opcode);
612 return -1; /* Must be something else ... */
616 * Simulate trapping 'rdhwr' instructions to provide user accessible
617 * registers not implemented in hardware.
619 static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt)
621 struct thread_info *ti = task_thread_info(current);
623 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
626 case MIPS_HWR_CPUNUM: /* CPU number */
627 regs->regs[rt] = smp_processor_id();
629 case MIPS_HWR_SYNCISTEP: /* SYNCI length */
630 regs->regs[rt] = min(current_cpu_data.dcache.linesz,
631 current_cpu_data.icache.linesz);
633 case MIPS_HWR_CC: /* Read count register */
634 regs->regs[rt] = read_c0_count();
636 case MIPS_HWR_CCRES: /* Count register resolution */
637 switch (current_cpu_type()) {
646 case MIPS_HWR_ULR: /* Read UserLocal register */
647 regs->regs[rt] = ti->tp_value;
654 static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode)
656 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
657 int rd = (opcode & RD) >> 11;
658 int rt = (opcode & RT) >> 16;
660 simulate_rdhwr(regs, rd, rt);
668 static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned int opcode)
670 if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) {
671 int rd = (opcode & MM_RS) >> 16;
672 int rt = (opcode & MM_RT) >> 21;
673 simulate_rdhwr(regs, rd, rt);
681 static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
683 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) {
684 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
689 return -1; /* Must be something else ... */
692 asmlinkage void do_ov(struct pt_regs *regs)
694 enum ctx_state prev_state;
697 .si_code = FPE_INTOVF,
698 .si_addr = (void __user *)regs->cp0_epc,
701 prev_state = exception_enter();
702 die_if_kernel("Integer overflow", regs);
704 force_sig_info(SIGFPE, &info, current);
705 exception_exit(prev_state);
708 int process_fpemu_return(int sig, void __user *fault_addr, unsigned long fcr31)
710 struct siginfo si = { 0 };
711 struct vm_area_struct *vma;
718 si.si_addr = fault_addr;
721 * Inexact can happen together with Overflow or Underflow.
722 * Respect the mask to deliver the correct exception.
724 fcr31 &= (fcr31 & FPU_CSR_ALL_E) <<
725 (ffs(FPU_CSR_ALL_X) - ffs(FPU_CSR_ALL_E));
726 if (fcr31 & FPU_CSR_INV_X)
727 si.si_code = FPE_FLTINV;
728 else if (fcr31 & FPU_CSR_DIV_X)
729 si.si_code = FPE_FLTDIV;
730 else if (fcr31 & FPU_CSR_OVF_X)
731 si.si_code = FPE_FLTOVF;
732 else if (fcr31 & FPU_CSR_UDF_X)
733 si.si_code = FPE_FLTUND;
734 else if (fcr31 & FPU_CSR_INE_X)
735 si.si_code = FPE_FLTRES;
737 si.si_code = __SI_FAULT;
738 force_sig_info(sig, &si, current);
742 si.si_addr = fault_addr;
744 si.si_code = BUS_ADRERR;
745 force_sig_info(sig, &si, current);
749 si.si_addr = fault_addr;
751 down_read(¤t->mm->mmap_sem);
752 vma = find_vma(current->mm, (unsigned long)fault_addr);
753 if (vma && (vma->vm_start <= (unsigned long)fault_addr))
754 si.si_code = SEGV_ACCERR;
756 si.si_code = SEGV_MAPERR;
757 up_read(¤t->mm->mmap_sem);
758 force_sig_info(sig, &si, current);
762 force_sig(sig, current);
767 static int simulate_fp(struct pt_regs *regs, unsigned int opcode,
768 unsigned long old_epc, unsigned long old_ra)
770 union mips_instruction inst = { .word = opcode };
771 void __user *fault_addr;
775 /* If it's obviously not an FP instruction, skip it */
776 switch (inst.i_format.opcode) {
790 * do_ri skipped over the instruction via compute_return_epc, undo
791 * that for the FPU emulator.
793 regs->cp0_epc = old_epc;
794 regs->regs[31] = old_ra;
796 /* Save the FP context to struct thread_struct */
799 /* Run the emulator */
800 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1,
802 fcr31 = current->thread.fpu.fcr31;
805 * We can't allow the emulated instruction to leave any of
806 * the cause bits set in $fcr31.
808 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
810 /* Restore the hardware register state */
813 /* Send a signal if required. */
814 process_fpemu_return(sig, fault_addr, fcr31);
820 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
822 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
824 enum ctx_state prev_state;
825 void __user *fault_addr;
828 prev_state = exception_enter();
829 if (notify_die(DIE_FP, "FP exception", regs, 0, current->thread.trap_nr,
830 SIGFPE) == NOTIFY_STOP)
833 /* Clear FCSR.Cause before enabling interrupts */
834 write_32bit_cp1_register(CP1_STATUS, fcr31 & ~FPU_CSR_ALL_X);
837 die_if_kernel("FP exception in kernel code", regs);
839 if (fcr31 & FPU_CSR_UNI_X) {
841 * Unimplemented operation exception. If we've got the full
842 * software emulator on-board, let's use it...
844 * Force FPU to dump state into task/thread context. We're
845 * moving a lot of data here for what is probably a single
846 * instruction, but the alternative is to pre-decode the FP
847 * register operands before invoking the emulator, which seems
848 * a bit extreme for what should be an infrequent event.
850 /* Ensure 'resume' not overwrite saved fp context again. */
853 /* Run the emulator */
854 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1,
856 fcr31 = current->thread.fpu.fcr31;
859 * We can't allow the emulated instruction to leave any of
860 * the cause bits set in $fcr31.
862 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
864 /* Restore the hardware register state */
865 own_fpu(1); /* Using the FPU again. */
868 fault_addr = (void __user *) regs->cp0_epc;
871 /* Send a signal if required. */
872 process_fpemu_return(sig, fault_addr, fcr31);
875 exception_exit(prev_state);
878 void do_trap_or_bp(struct pt_regs *regs, unsigned int code, int si_code,
881 siginfo_t info = { 0 };
884 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
885 if (kgdb_ll_trap(DIE_TRAP, str, regs, code, current->thread.trap_nr,
886 SIGTRAP) == NOTIFY_STOP)
888 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
890 if (notify_die(DIE_TRAP, str, regs, code, current->thread.trap_nr,
891 SIGTRAP) == NOTIFY_STOP)
895 * A short test says that IRIX 5.3 sends SIGTRAP for all trap
896 * insns, even for trap and break codes that indicate arithmetic
897 * failures. Weird ...
898 * But should we continue the brokenness??? --macro
903 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
904 die_if_kernel(b, regs);
905 if (code == BRK_DIVZERO)
906 info.si_code = FPE_INTDIV;
908 info.si_code = FPE_INTOVF;
909 info.si_signo = SIGFPE;
910 info.si_addr = (void __user *) regs->cp0_epc;
911 force_sig_info(SIGFPE, &info, current);
914 die_if_kernel("Kernel bug detected", regs);
915 force_sig(SIGTRAP, current);
919 * This breakpoint code is used by the FPU emulator to retake
920 * control of the CPU after executing the instruction from the
921 * delay slot of an emulated branch.
923 * Terminate if exception was recognized as a delay slot return
924 * otherwise handle as normal.
926 if (do_dsemulret(regs))
929 die_if_kernel("Math emu break/trap", regs);
930 force_sig(SIGTRAP, current);
933 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
934 die_if_kernel(b, regs);
936 info.si_signo = SIGTRAP;
937 info.si_code = si_code;
938 force_sig_info(SIGTRAP, &info, current);
940 force_sig(SIGTRAP, current);
945 asmlinkage void do_bp(struct pt_regs *regs)
947 unsigned long epc = msk_isa16_mode(exception_epc(regs));
948 unsigned int opcode, bcode;
949 enum ctx_state prev_state;
953 if (!user_mode(regs))
956 prev_state = exception_enter();
957 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
958 if (get_isa16_mode(regs->cp0_epc)) {
961 if (__get_user(instr[0], (u16 __user *)epc))
964 if (!cpu_has_mmips) {
966 bcode = (instr[0] >> 5) & 0x3f;
967 } else if (mm_insn_16bit(instr[0])) {
968 /* 16-bit microMIPS BREAK */
969 bcode = instr[0] & 0xf;
971 /* 32-bit microMIPS BREAK */
972 if (__get_user(instr[1], (u16 __user *)(epc + 2)))
974 opcode = (instr[0] << 16) | instr[1];
975 bcode = (opcode >> 6) & ((1 << 20) - 1);
978 if (__get_user(opcode, (unsigned int __user *)epc))
980 bcode = (opcode >> 6) & ((1 << 20) - 1);
984 * There is the ancient bug in the MIPS assemblers that the break
985 * code starts left to bit 16 instead to bit 6 in the opcode.
986 * Gas is bug-compatible, but not always, grrr...
987 * We handle both cases with a simple heuristics. --macro
989 if (bcode >= (1 << 10))
990 bcode = ((bcode & ((1 << 10) - 1)) << 10) | (bcode >> 10);
993 * notify the kprobe handlers, if instruction is likely to
998 if (notify_die(DIE_UPROBE, "uprobe", regs, bcode,
999 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1003 case BRK_UPROBE_XOL:
1004 if (notify_die(DIE_UPROBE_XOL, "uprobe_xol", regs, bcode,
1005 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1010 if (notify_die(DIE_BREAK, "debug", regs, bcode,
1011 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1015 case BRK_KPROBE_SSTEPBP:
1016 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode,
1017 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1025 do_trap_or_bp(regs, bcode, TRAP_BRKPT, "Break");
1029 exception_exit(prev_state);
1033 force_sig(SIGSEGV, current);
1037 asmlinkage void do_tr(struct pt_regs *regs)
1039 u32 opcode, tcode = 0;
1040 enum ctx_state prev_state;
1043 unsigned long epc = msk_isa16_mode(exception_epc(regs));
1046 if (!user_mode(regs))
1049 prev_state = exception_enter();
1050 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
1051 if (get_isa16_mode(regs->cp0_epc)) {
1052 if (__get_user(instr[0], (u16 __user *)(epc + 0)) ||
1053 __get_user(instr[1], (u16 __user *)(epc + 2)))
1055 opcode = (instr[0] << 16) | instr[1];
1056 /* Immediate versions don't provide a code. */
1057 if (!(opcode & OPCODE))
1058 tcode = (opcode >> 12) & ((1 << 4) - 1);
1060 if (__get_user(opcode, (u32 __user *)epc))
1062 /* Immediate versions don't provide a code. */
1063 if (!(opcode & OPCODE))
1064 tcode = (opcode >> 6) & ((1 << 10) - 1);
1067 do_trap_or_bp(regs, tcode, 0, "Trap");
1071 exception_exit(prev_state);
1075 force_sig(SIGSEGV, current);
1079 asmlinkage void do_ri(struct pt_regs *regs)
1081 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs);
1082 unsigned long old_epc = regs->cp0_epc;
1083 unsigned long old31 = regs->regs[31];
1084 enum ctx_state prev_state;
1085 unsigned int opcode = 0;
1089 * Avoid any kernel code. Just emulate the R2 instruction
1090 * as quickly as possible.
1092 if (mipsr2_emulation && cpu_has_mips_r6 &&
1093 likely(user_mode(regs)) &&
1094 likely(get_user(opcode, epc) >= 0)) {
1095 unsigned long fcr31 = 0;
1097 status = mipsr2_decoder(regs, opcode, &fcr31);
1101 task_thread_info(current)->r2_emul_return = 1;
1106 process_fpemu_return(status,
1107 ¤t->thread.cp0_baduaddr,
1109 task_thread_info(current)->r2_emul_return = 1;
1116 prev_state = exception_enter();
1117 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
1119 if (notify_die(DIE_RI, "RI Fault", regs, 0, current->thread.trap_nr,
1120 SIGILL) == NOTIFY_STOP)
1123 die_if_kernel("Reserved instruction in kernel code", regs);
1125 if (unlikely(compute_return_epc(regs) < 0))
1128 if (!get_isa16_mode(regs->cp0_epc)) {
1129 if (unlikely(get_user(opcode, epc) < 0))
1132 if (!cpu_has_llsc && status < 0)
1133 status = simulate_llsc(regs, opcode);
1136 status = simulate_rdhwr_normal(regs, opcode);
1139 status = simulate_sync(regs, opcode);
1142 status = simulate_fp(regs, opcode, old_epc, old31);
1143 } else if (cpu_has_mmips) {
1144 unsigned short mmop[2] = { 0 };
1146 if (unlikely(get_user(mmop[0], (u16 __user *)epc + 0) < 0))
1148 if (unlikely(get_user(mmop[1], (u16 __user *)epc + 1) < 0))
1151 opcode = (opcode << 16) | mmop[1];
1154 status = simulate_rdhwr_mm(regs, opcode);
1160 if (unlikely(status > 0)) {
1161 regs->cp0_epc = old_epc; /* Undo skip-over. */
1162 regs->regs[31] = old31;
1163 force_sig(status, current);
1167 exception_exit(prev_state);
1171 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
1172 * emulated more than some threshold number of instructions, force migration to
1173 * a "CPU" that has FP support.
1175 static void mt_ase_fp_affinity(void)
1177 #ifdef CONFIG_MIPS_MT_FPAFF
1178 if (mt_fpemul_threshold > 0 &&
1179 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) {
1181 * If there's no FPU present, or if the application has already
1182 * restricted the allowed set to exclude any CPUs with FPUs,
1183 * we'll skip the procedure.
1185 if (cpumask_intersects(¤t->cpus_allowed, &mt_fpu_cpumask)) {
1188 current->thread.user_cpus_allowed
1189 = current->cpus_allowed;
1190 cpumask_and(&tmask, ¤t->cpus_allowed,
1192 set_cpus_allowed_ptr(current, &tmask);
1193 set_thread_flag(TIF_FPUBOUND);
1196 #endif /* CONFIG_MIPS_MT_FPAFF */
1200 * No lock; only written during early bootup by CPU 0.
1202 static RAW_NOTIFIER_HEAD(cu2_chain);
1204 int __ref register_cu2_notifier(struct notifier_block *nb)
1206 return raw_notifier_chain_register(&cu2_chain, nb);
1209 int cu2_notifier_call_chain(unsigned long val, void *v)
1211 return raw_notifier_call_chain(&cu2_chain, val, v);
1214 static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
1217 struct pt_regs *regs = data;
1219 die_if_kernel("COP2: Unhandled kernel unaligned access or invalid "
1220 "instruction", regs);
1221 force_sig(SIGILL, current);
1226 static int wait_on_fp_mode_switch(atomic_t *p)
1229 * The FP mode for this task is currently being switched. That may
1230 * involve modifications to the format of this tasks FP context which
1231 * make it unsafe to proceed with execution for the moment. Instead,
1232 * schedule some other task.
1238 static int enable_restore_fp_context(int msa)
1240 int err, was_fpu_owner, prior_msa;
1243 * If an FP mode switch is currently underway, wait for it to
1244 * complete before proceeding.
1246 wait_on_atomic_t(¤t->mm->context.fp_mode_switching,
1247 wait_on_fp_mode_switch, TASK_KILLABLE);
1250 /* First time FP context user. */
1256 set_thread_flag(TIF_USEDMSA);
1257 set_thread_flag(TIF_MSA_CTX_LIVE);
1266 * This task has formerly used the FP context.
1268 * If this thread has no live MSA vector context then we can simply
1269 * restore the scalar FP context. If it has live MSA vector context
1270 * (that is, it has or may have used MSA since last performing a
1271 * function call) then we'll need to restore the vector context. This
1272 * applies even if we're currently only executing a scalar FP
1273 * instruction. This is because if we were to later execute an MSA
1274 * instruction then we'd either have to:
1276 * - Restore the vector context & clobber any registers modified by
1277 * scalar FP instructions between now & then.
1281 * - Not restore the vector context & lose the most significant bits
1282 * of all vector registers.
1284 * Neither of those options is acceptable. We cannot restore the least
1285 * significant bits of the registers now & only restore the most
1286 * significant bits later because the most significant bits of any
1287 * vector registers whose aliased FP register is modified now will have
1288 * been zeroed. We'd have no way to know that when restoring the vector
1289 * context & thus may load an outdated value for the most significant
1290 * bits of a vector register.
1292 if (!msa && !thread_msa_context_live())
1296 * This task is using or has previously used MSA. Thus we require
1297 * that Status.FR == 1.
1300 was_fpu_owner = is_fpu_owner();
1301 err = own_fpu_inatomic(0);
1306 write_msa_csr(current->thread.fpu.msacsr);
1307 set_thread_flag(TIF_USEDMSA);
1310 * If this is the first time that the task is using MSA and it has
1311 * previously used scalar FP in this time slice then we already nave
1312 * FP context which we shouldn't clobber. We do however need to clear
1313 * the upper 64b of each vector register so that this task has no
1314 * opportunity to see data left behind by another.
1316 prior_msa = test_and_set_thread_flag(TIF_MSA_CTX_LIVE);
1317 if (!prior_msa && was_fpu_owner) {
1325 * Restore the least significant 64b of each vector register
1326 * from the existing scalar FP context.
1328 _restore_fp(current);
1331 * The task has not formerly used MSA, so clear the upper 64b
1332 * of each vector register such that it cannot see data left
1333 * behind by another task.
1337 /* We need to restore the vector context. */
1338 restore_msa(current);
1340 /* Restore the scalar FP control & status register */
1342 write_32bit_cp1_register(CP1_STATUS,
1343 current->thread.fpu.fcr31);
1352 asmlinkage void do_cpu(struct pt_regs *regs)
1354 enum ctx_state prev_state;
1355 unsigned int __user *epc;
1356 unsigned long old_epc, old31;
1357 void __user *fault_addr;
1358 unsigned int opcode;
1359 unsigned long fcr31;
1364 prev_state = exception_enter();
1365 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
1368 die_if_kernel("do_cpu invoked from kernel context!", regs);
1372 epc = (unsigned int __user *)exception_epc(regs);
1373 old_epc = regs->cp0_epc;
1374 old31 = regs->regs[31];
1378 if (unlikely(compute_return_epc(regs) < 0))
1381 if (!get_isa16_mode(regs->cp0_epc)) {
1382 if (unlikely(get_user(opcode, epc) < 0))
1385 if (!cpu_has_llsc && status < 0)
1386 status = simulate_llsc(regs, opcode);
1392 if (unlikely(status > 0)) {
1393 regs->cp0_epc = old_epc; /* Undo skip-over. */
1394 regs->regs[31] = old31;
1395 force_sig(status, current);
1402 * The COP3 opcode space and consequently the CP0.Status.CU3
1403 * bit and the CP0.Cause.CE=3 encoding have been removed as
1404 * of the MIPS III ISA. From the MIPS IV and MIPS32r2 ISAs
1405 * up the space has been reused for COP1X instructions, that
1406 * are enabled by the CP0.Status.CU1 bit and consequently
1407 * use the CP0.Cause.CE=1 encoding for Coprocessor Unusable
1408 * exceptions. Some FPU-less processors that implement one
1409 * of these ISAs however use this code erroneously for COP1X
1410 * instructions. Therefore we redirect this trap to the FP
1413 if (raw_cpu_has_fpu || !cpu_has_mips_4_5_64_r2_r6) {
1414 force_sig(SIGILL, current);
1420 err = enable_restore_fp_context(0);
1422 if (raw_cpu_has_fpu && !err)
1425 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 0,
1427 fcr31 = current->thread.fpu.fcr31;
1430 * We can't allow the emulated instruction to leave
1431 * any of the cause bits set in $fcr31.
1433 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
1435 /* Send a signal if required. */
1436 if (!process_fpemu_return(sig, fault_addr, fcr31) && !err)
1437 mt_ase_fp_affinity();
1442 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
1446 exception_exit(prev_state);
1449 asmlinkage void do_msa_fpe(struct pt_regs *regs, unsigned int msacsr)
1451 enum ctx_state prev_state;
1453 prev_state = exception_enter();
1454 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
1455 if (notify_die(DIE_MSAFP, "MSA FP exception", regs, 0,
1456 current->thread.trap_nr, SIGFPE) == NOTIFY_STOP)
1459 /* Clear MSACSR.Cause before enabling interrupts */
1460 write_msa_csr(msacsr & ~MSA_CSR_CAUSEF);
1463 die_if_kernel("do_msa_fpe invoked from kernel context!", regs);
1464 force_sig(SIGFPE, current);
1466 exception_exit(prev_state);
1469 asmlinkage void do_msa(struct pt_regs *regs)
1471 enum ctx_state prev_state;
1474 prev_state = exception_enter();
1476 if (!cpu_has_msa || test_thread_flag(TIF_32BIT_FPREGS)) {
1477 force_sig(SIGILL, current);
1481 die_if_kernel("do_msa invoked from kernel context!", regs);
1483 err = enable_restore_fp_context(1);
1485 force_sig(SIGILL, current);
1487 exception_exit(prev_state);
1490 asmlinkage void do_mdmx(struct pt_regs *regs)
1492 enum ctx_state prev_state;
1494 prev_state = exception_enter();
1495 force_sig(SIGILL, current);
1496 exception_exit(prev_state);
1500 * Called with interrupts disabled.
1502 asmlinkage void do_watch(struct pt_regs *regs)
1504 siginfo_t info = { .si_signo = SIGTRAP, .si_code = TRAP_HWBKPT };
1505 enum ctx_state prev_state;
1507 prev_state = exception_enter();
1509 * Clear WP (bit 22) bit of cause register so we don't loop
1512 clear_c0_cause(CAUSEF_WP);
1515 * If the current thread has the watch registers loaded, save
1516 * their values and send SIGTRAP. Otherwise another thread
1517 * left the registers set, clear them and continue.
1519 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
1520 mips_read_watch_registers();
1522 force_sig_info(SIGTRAP, &info, current);
1524 mips_clear_watch_registers();
1527 exception_exit(prev_state);
1530 asmlinkage void do_mcheck(struct pt_regs *regs)
1532 int multi_match = regs->cp0_status & ST0_TS;
1533 enum ctx_state prev_state;
1534 mm_segment_t old_fs = get_fs();
1536 prev_state = exception_enter();
1545 if (!user_mode(regs))
1548 show_code((unsigned int __user *) regs->cp0_epc);
1553 * Some chips may have other causes of machine check (e.g. SB1
1556 panic("Caught Machine Check exception - %scaused by multiple "
1557 "matching entries in the TLB.",
1558 (multi_match) ? "" : "not ");
1561 asmlinkage void do_mt(struct pt_regs *regs)
1565 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
1566 >> VPECONTROL_EXCPT_SHIFT;
1569 printk(KERN_DEBUG "Thread Underflow\n");
1572 printk(KERN_DEBUG "Thread Overflow\n");
1575 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
1578 printk(KERN_DEBUG "Gating Storage Exception\n");
1581 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
1584 printk(KERN_DEBUG "Gating Storage Scheduler Exception\n");
1587 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
1591 die_if_kernel("MIPS MT Thread exception in kernel", regs);
1593 force_sig(SIGILL, current);
1597 asmlinkage void do_dsp(struct pt_regs *regs)
1600 panic("Unexpected DSP exception");
1602 force_sig(SIGILL, current);
1605 asmlinkage void do_reserved(struct pt_regs *regs)
1608 * Game over - no way to handle this if it ever occurs. Most probably
1609 * caused by a new unknown cpu type or after another deadly
1610 * hard/software error.
1613 panic("Caught reserved exception %ld - should not happen.",
1614 (regs->cp0_cause & 0x7f) >> 2);
1617 static int __initdata l1parity = 1;
1618 static int __init nol1parity(char *s)
1623 __setup("nol1par", nol1parity);
1624 static int __initdata l2parity = 1;
1625 static int __init nol2parity(char *s)
1630 __setup("nol2par", nol2parity);
1633 * Some MIPS CPUs can enable/disable for cache parity detection, but do
1634 * it different ways.
1636 static inline void parity_protection_init(void)
1638 switch (current_cpu_type()) {
1644 case CPU_INTERAPTIV:
1647 case CPU_QEMU_GENERIC:
1651 #define ERRCTL_PE 0x80000000
1652 #define ERRCTL_L2P 0x00800000
1653 unsigned long errctl;
1654 unsigned int l1parity_present, l2parity_present;
1656 errctl = read_c0_ecc();
1657 errctl &= ~(ERRCTL_PE|ERRCTL_L2P);
1659 /* probe L1 parity support */
1660 write_c0_ecc(errctl | ERRCTL_PE);
1661 back_to_back_c0_hazard();
1662 l1parity_present = (read_c0_ecc() & ERRCTL_PE);
1664 /* probe L2 parity support */
1665 write_c0_ecc(errctl|ERRCTL_L2P);
1666 back_to_back_c0_hazard();
1667 l2parity_present = (read_c0_ecc() & ERRCTL_L2P);
1669 if (l1parity_present && l2parity_present) {
1671 errctl |= ERRCTL_PE;
1672 if (l1parity ^ l2parity)
1673 errctl |= ERRCTL_L2P;
1674 } else if (l1parity_present) {
1676 errctl |= ERRCTL_PE;
1677 } else if (l2parity_present) {
1679 errctl |= ERRCTL_L2P;
1681 /* No parity available */
1684 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl);
1686 write_c0_ecc(errctl);
1687 back_to_back_c0_hazard();
1688 errctl = read_c0_ecc();
1689 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl);
1691 if (l1parity_present)
1692 printk(KERN_INFO "Cache parity protection %sabled\n",
1693 (errctl & ERRCTL_PE) ? "en" : "dis");
1695 if (l2parity_present) {
1696 if (l1parity_present && l1parity)
1697 errctl ^= ERRCTL_L2P;
1698 printk(KERN_INFO "L2 cache parity protection %sabled\n",
1699 (errctl & ERRCTL_L2P) ? "en" : "dis");
1707 write_c0_ecc(0x80000000);
1708 back_to_back_c0_hazard();
1709 /* Set the PE bit (bit 31) in the c0_errctl register. */
1710 printk(KERN_INFO "Cache parity protection %sabled\n",
1711 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
1715 /* Clear the DE bit (bit 16) in the c0_status register. */
1716 printk(KERN_INFO "Enable cache parity protection for "
1717 "MIPS 20KC/25KF CPUs.\n");
1718 clear_c0_status(ST0_DE);
1725 asmlinkage void cache_parity_error(void)
1727 const int field = 2 * sizeof(unsigned long);
1728 unsigned int reg_val;
1730 /* For the moment, report the problem and hang. */
1731 printk("Cache error exception:\n");
1732 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1733 reg_val = read_c0_cacheerr();
1734 printk("c0_cacheerr == %08x\n", reg_val);
1736 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1737 reg_val & (1<<30) ? "secondary" : "primary",
1738 reg_val & (1<<31) ? "data" : "insn");
1739 if ((cpu_has_mips_r2_r6) &&
1740 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) {
1741 pr_err("Error bits: %s%s%s%s%s%s%s%s\n",
1742 reg_val & (1<<29) ? "ED " : "",
1743 reg_val & (1<<28) ? "ET " : "",
1744 reg_val & (1<<27) ? "ES " : "",
1745 reg_val & (1<<26) ? "EE " : "",
1746 reg_val & (1<<25) ? "EB " : "",
1747 reg_val & (1<<24) ? "EI " : "",
1748 reg_val & (1<<23) ? "E1 " : "",
1749 reg_val & (1<<22) ? "E0 " : "");
1751 pr_err("Error bits: %s%s%s%s%s%s%s\n",
1752 reg_val & (1<<29) ? "ED " : "",
1753 reg_val & (1<<28) ? "ET " : "",
1754 reg_val & (1<<26) ? "EE " : "",
1755 reg_val & (1<<25) ? "EB " : "",
1756 reg_val & (1<<24) ? "EI " : "",
1757 reg_val & (1<<23) ? "E1 " : "",
1758 reg_val & (1<<22) ? "E0 " : "");
1760 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1762 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1763 if (reg_val & (1<<22))
1764 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1766 if (reg_val & (1<<23))
1767 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1770 panic("Can't handle the cache error!");
1773 asmlinkage void do_ftlb(void)
1775 const int field = 2 * sizeof(unsigned long);
1776 unsigned int reg_val;
1778 /* For the moment, report the problem and hang. */
1779 if ((cpu_has_mips_r2_r6) &&
1780 (((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS) ||
1781 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_LOONGSON))) {
1782 pr_err("FTLB error exception, cp0_ecc=0x%08x:\n",
1784 pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1785 reg_val = read_c0_cacheerr();
1786 pr_err("c0_cacheerr == %08x\n", reg_val);
1788 if ((reg_val & 0xc0000000) == 0xc0000000) {
1789 pr_err("Decoded c0_cacheerr: FTLB parity error\n");
1791 pr_err("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1792 reg_val & (1<<30) ? "secondary" : "primary",
1793 reg_val & (1<<31) ? "data" : "insn");
1796 pr_err("FTLB error exception\n");
1798 /* Just print the cacheerr bits for now */
1799 cache_parity_error();
1803 * SDBBP EJTAG debug exception handler.
1804 * We skip the instruction and return to the next instruction.
1806 void ejtag_exception_handler(struct pt_regs *regs)
1808 const int field = 2 * sizeof(unsigned long);
1809 unsigned long depc, old_epc, old_ra;
1812 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1813 depc = read_c0_depc();
1814 debug = read_c0_debug();
1815 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
1816 if (debug & 0x80000000) {
1818 * In branch delay slot.
1819 * We cheat a little bit here and use EPC to calculate the
1820 * debug return address (DEPC). EPC is restored after the
1823 old_epc = regs->cp0_epc;
1824 old_ra = regs->regs[31];
1825 regs->cp0_epc = depc;
1826 compute_return_epc(regs);
1827 depc = regs->cp0_epc;
1828 regs->cp0_epc = old_epc;
1829 regs->regs[31] = old_ra;
1832 write_c0_depc(depc);
1835 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1836 write_c0_debug(debug | 0x100);
1841 * NMI exception handler.
1842 * No lock; only written during early bootup by CPU 0.
1844 static RAW_NOTIFIER_HEAD(nmi_chain);
1846 int register_nmi_notifier(struct notifier_block *nb)
1848 return raw_notifier_chain_register(&nmi_chain, nb);
1851 void __noreturn nmi_exception_handler(struct pt_regs *regs)
1856 raw_notifier_call_chain(&nmi_chain, 0, regs);
1858 snprintf(str, 100, "CPU%d NMI taken, CP0_EPC=%lx\n",
1859 smp_processor_id(), regs->cp0_epc);
1860 regs->cp0_epc = read_c0_errorepc();
1865 #define VECTORSPACING 0x100 /* for EI/VI mode */
1867 unsigned long ebase;
1868 EXPORT_SYMBOL_GPL(ebase);
1869 unsigned long exception_handlers[32];
1870 unsigned long vi_handlers[64];
1872 void __init *set_except_vector(int n, void *addr)
1874 unsigned long handler = (unsigned long) addr;
1875 unsigned long old_handler;
1877 #ifdef CONFIG_CPU_MICROMIPS
1879 * Only the TLB handlers are cache aligned with an even
1880 * address. All other handlers are on an odd address and
1881 * require no modification. Otherwise, MIPS32 mode will
1882 * be entered when handling any TLB exceptions. That
1883 * would be bad...since we must stay in microMIPS mode.
1885 if (!(handler & 0x1))
1888 old_handler = xchg(&exception_handlers[n], handler);
1890 if (n == 0 && cpu_has_divec) {
1891 #ifdef CONFIG_CPU_MICROMIPS
1892 unsigned long jump_mask = ~((1 << 27) - 1);
1894 unsigned long jump_mask = ~((1 << 28) - 1);
1896 u32 *buf = (u32 *)(ebase + 0x200);
1897 unsigned int k0 = 26;
1898 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) {
1899 uasm_i_j(&buf, handler & ~jump_mask);
1902 UASM_i_LA(&buf, k0, handler);
1903 uasm_i_jr(&buf, k0);
1906 local_flush_icache_range(ebase + 0x200, (unsigned long)buf);
1908 return (void *)old_handler;
1911 static void do_default_vi(void)
1913 show_regs(get_irq_regs());
1914 panic("Caught unexpected vectored interrupt.");
1917 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1919 unsigned long handler;
1920 unsigned long old_handler = vi_handlers[n];
1921 int srssets = current_cpu_data.srsets;
1925 BUG_ON(!cpu_has_veic && !cpu_has_vint);
1928 handler = (unsigned long) do_default_vi;
1931 handler = (unsigned long) addr;
1932 vi_handlers[n] = handler;
1934 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1937 panic("Shadow register set %d not supported", srs);
1940 if (board_bind_eic_interrupt)
1941 board_bind_eic_interrupt(n, srs);
1942 } else if (cpu_has_vint) {
1943 /* SRSMap is only defined if shadow sets are implemented */
1945 change_c0_srsmap(0xf << n*4, srs << n*4);
1950 * If no shadow set is selected then use the default handler
1951 * that does normal register saving and standard interrupt exit
1953 extern char except_vec_vi, except_vec_vi_lui;
1954 extern char except_vec_vi_ori, except_vec_vi_end;
1955 extern char rollback_except_vec_vi;
1956 char *vec_start = using_rollback_handler() ?
1957 &rollback_except_vec_vi : &except_vec_vi;
1958 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
1959 const int lui_offset = &except_vec_vi_lui - vec_start + 2;
1960 const int ori_offset = &except_vec_vi_ori - vec_start + 2;
1962 const int lui_offset = &except_vec_vi_lui - vec_start;
1963 const int ori_offset = &except_vec_vi_ori - vec_start;
1965 const int handler_len = &except_vec_vi_end - vec_start;
1967 if (handler_len > VECTORSPACING) {
1969 * Sigh... panicing won't help as the console
1970 * is probably not configured :(
1972 panic("VECTORSPACING too small");
1975 set_handler(((unsigned long)b - ebase), vec_start,
1976 #ifdef CONFIG_CPU_MICROMIPS
1981 h = (u16 *)(b + lui_offset);
1982 *h = (handler >> 16) & 0xffff;
1983 h = (u16 *)(b + ori_offset);
1984 *h = (handler & 0xffff);
1985 local_flush_icache_range((unsigned long)b,
1986 (unsigned long)(b+handler_len));
1990 * In other cases jump directly to the interrupt handler. It
1991 * is the handler's responsibility to save registers if required
1992 * (eg hi/lo) and return from the exception using "eret".
1998 #ifdef CONFIG_CPU_MICROMIPS
1999 insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1);
2001 insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2);
2003 h[0] = (insn >> 16) & 0xffff;
2004 h[1] = insn & 0xffff;
2007 local_flush_icache_range((unsigned long)b,
2008 (unsigned long)(b+8));
2011 return (void *)old_handler;
2014 void *set_vi_handler(int n, vi_handler_t addr)
2016 return set_vi_srs_handler(n, addr, 0);
2019 extern void tlb_init(void);
2024 int cp0_compare_irq;
2025 EXPORT_SYMBOL_GPL(cp0_compare_irq);
2026 int cp0_compare_irq_shift;
2029 * Performance counter IRQ or -1 if shared with timer
2031 int cp0_perfcount_irq;
2032 EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
2035 * Fast debug channel IRQ or -1 if not present
2038 EXPORT_SYMBOL_GPL(cp0_fdc_irq);
2042 static int __init ulri_disable(char *s)
2044 pr_info("Disabling ulri\n");
2049 __setup("noulri", ulri_disable);
2051 /* configure STATUS register */
2052 static void configure_status(void)
2055 * Disable coprocessors and select 32-bit or 64-bit addressing
2056 * and the 16/32 or 32/32 FPR register model. Reset the BEV
2057 * flag that some firmware may have left set and the TS bit (for
2058 * IP27). Set XX for ISA IV code to work.
2060 unsigned int status_set = ST0_CU0;
2062 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
2064 if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV)
2065 status_set |= ST0_XX;
2067 status_set |= ST0_MX;
2069 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
2073 unsigned int hwrena;
2074 EXPORT_SYMBOL_GPL(hwrena);
2076 /* configure HWRENA register */
2077 static void configure_hwrena(void)
2079 hwrena = cpu_hwrena_impl_bits;
2081 if (cpu_has_mips_r2_r6)
2082 hwrena |= MIPS_HWRENA_CPUNUM |
2083 MIPS_HWRENA_SYNCISTEP |
2087 if (!noulri && cpu_has_userlocal)
2088 hwrena |= MIPS_HWRENA_ULR;
2091 write_c0_hwrena(hwrena);
2094 static void configure_exception_vector(void)
2096 if (cpu_has_veic || cpu_has_vint) {
2097 unsigned long sr = set_c0_status(ST0_BEV);
2098 /* If available, use WG to set top bits of EBASE */
2099 if (cpu_has_ebase_wg) {
2101 write_c0_ebase_64(ebase | MIPS_EBASE_WG);
2103 write_c0_ebase(ebase | MIPS_EBASE_WG);
2106 write_c0_ebase(ebase);
2107 write_c0_status(sr);
2108 /* Setting vector spacing enables EI/VI mode */
2109 change_c0_intctl(0x3e0, VECTORSPACING);
2111 if (cpu_has_divec) {
2112 if (cpu_has_mipsmt) {
2113 unsigned int vpflags = dvpe();
2114 set_c0_cause(CAUSEF_IV);
2117 set_c0_cause(CAUSEF_IV);
2121 void per_cpu_trap_init(bool is_boot_cpu)
2123 unsigned int cpu = smp_processor_id();
2128 configure_exception_vector();
2131 * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
2133 * o read IntCtl.IPTI to determine the timer interrupt
2134 * o read IntCtl.IPPCI to determine the performance counter interrupt
2135 * o read IntCtl.IPFDC to determine the fast debug channel interrupt
2137 if (cpu_has_mips_r2_r6) {
2139 * We shouldn't trust a secondary core has a sane EBASE register
2140 * so use the one calculated by the boot CPU.
2143 /* If available, use WG to set top bits of EBASE */
2144 if (cpu_has_ebase_wg) {
2146 write_c0_ebase_64(ebase | MIPS_EBASE_WG);
2148 write_c0_ebase(ebase | MIPS_EBASE_WG);
2151 write_c0_ebase(ebase);
2154 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
2155 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
2156 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
2157 cp0_fdc_irq = (read_c0_intctl() >> INTCTLB_IPFDC) & 7;
2162 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
2163 cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ;
2164 cp0_perfcount_irq = -1;
2168 if (!cpu_data[cpu].asid_cache)
2169 cpu_data[cpu].asid_cache = asid_first_version(cpu);
2171 atomic_inc(&init_mm.mm_count);
2172 current->active_mm = &init_mm;
2173 BUG_ON(current->mm);
2174 enter_lazy_tlb(&init_mm, current);
2176 /* Boot CPU's cache setup in setup_arch(). */
2180 TLBMISS_HANDLER_SETUP();
2183 /* Install CPU exception handler */
2184 void set_handler(unsigned long offset, void *addr, unsigned long size)
2186 #ifdef CONFIG_CPU_MICROMIPS
2187 memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size);
2189 memcpy((void *)(ebase + offset), addr, size);
2191 local_flush_icache_range(ebase + offset, ebase + offset + size);
2194 static char panic_null_cerr[] =
2195 "Trying to set NULL cache error exception handler";
2198 * Install uncached CPU exception handler.
2199 * This is suitable only for the cache error exception which is the only
2200 * exception handler that is being run uncached.
2202 void set_uncached_handler(unsigned long offset, void *addr,
2205 unsigned long uncached_ebase = CKSEG1ADDR(ebase);
2208 panic(panic_null_cerr);
2210 memcpy((void *)(uncached_ebase + offset), addr, size);
2213 static int __initdata rdhwr_noopt;
2214 static int __init set_rdhwr_noopt(char *str)
2220 __setup("rdhwr_noopt", set_rdhwr_noopt);
2222 void __init trap_init(void)
2224 extern char except_vec3_generic;
2225 extern char except_vec4;
2226 extern char except_vec3_r4000;
2231 if (cpu_has_veic || cpu_has_vint) {
2232 unsigned long size = 0x200 + VECTORSPACING*64;
2233 phys_addr_t ebase_pa;
2235 ebase = (unsigned long)
2236 __alloc_bootmem(size, 1 << fls(size), 0);
2239 * Try to ensure ebase resides in KSeg0 if possible.
2241 * It shouldn't generally be in XKPhys on MIPS64 to avoid
2242 * hitting a poorly defined exception base for Cache Errors.
2243 * The allocation is likely to be in the low 512MB of physical,
2244 * in which case we should be able to convert to KSeg0.
2246 * EVA is special though as it allows segments to be rearranged
2247 * and to become uncached during cache error handling.
2249 ebase_pa = __pa(ebase);
2250 if (!IS_ENABLED(CONFIG_EVA) && !WARN_ON(ebase_pa >= 0x20000000))
2251 ebase = CKSEG0ADDR(ebase_pa);
2255 if (cpu_has_mips_r2_r6) {
2256 if (cpu_has_ebase_wg) {
2258 ebase = (read_c0_ebase_64() & ~0xfff);
2260 ebase = (read_c0_ebase() & ~0xfff);
2263 ebase += (read_c0_ebase() & 0x3ffff000);
2268 if (cpu_has_mmips) {
2269 unsigned int config3 = read_c0_config3();
2271 if (IS_ENABLED(CONFIG_CPU_MICROMIPS))
2272 write_c0_config3(config3 | MIPS_CONF3_ISA_OE);
2274 write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE);
2277 if (board_ebase_setup)
2278 board_ebase_setup();
2279 per_cpu_trap_init(true);
2282 * Copy the generic exception handlers to their final destination.
2283 * This will be overridden later as suitable for a particular
2286 set_handler(0x180, &except_vec3_generic, 0x80);
2289 * Setup default vectors
2291 for (i = 0; i <= 31; i++)
2292 set_except_vector(i, handle_reserved);
2295 * Copy the EJTAG debug exception vector handler code to it's final
2298 if (cpu_has_ejtag && board_ejtag_handler_setup)
2299 board_ejtag_handler_setup();
2302 * Only some CPUs have the watch exceptions.
2305 set_except_vector(EXCCODE_WATCH, handle_watch);
2308 * Initialise interrupt handlers
2310 if (cpu_has_veic || cpu_has_vint) {
2311 int nvec = cpu_has_veic ? 64 : 8;
2312 for (i = 0; i < nvec; i++)
2313 set_vi_handler(i, NULL);
2315 else if (cpu_has_divec)
2316 set_handler(0x200, &except_vec4, 0x8);
2319 * Some CPUs can enable/disable for cache parity detection, but does
2320 * it different ways.
2322 parity_protection_init();
2325 * The Data Bus Errors / Instruction Bus Errors are signaled
2326 * by external hardware. Therefore these two exceptions
2327 * may have board specific handlers.
2332 set_except_vector(EXCCODE_INT, using_rollback_handler() ?
2333 rollback_handle_int : handle_int);
2334 set_except_vector(EXCCODE_MOD, handle_tlbm);
2335 set_except_vector(EXCCODE_TLBL, handle_tlbl);
2336 set_except_vector(EXCCODE_TLBS, handle_tlbs);
2338 set_except_vector(EXCCODE_ADEL, handle_adel);
2339 set_except_vector(EXCCODE_ADES, handle_ades);
2341 set_except_vector(EXCCODE_IBE, handle_ibe);
2342 set_except_vector(EXCCODE_DBE, handle_dbe);
2344 set_except_vector(EXCCODE_SYS, handle_sys);
2345 set_except_vector(EXCCODE_BP, handle_bp);
2346 set_except_vector(EXCCODE_RI, rdhwr_noopt ? handle_ri :
2347 (cpu_has_vtag_icache ?
2348 handle_ri_rdhwr_vivt : handle_ri_rdhwr));
2349 set_except_vector(EXCCODE_CPU, handle_cpu);
2350 set_except_vector(EXCCODE_OV, handle_ov);
2351 set_except_vector(EXCCODE_TR, handle_tr);
2352 set_except_vector(EXCCODE_MSAFPE, handle_msa_fpe);
2354 if (current_cpu_type() == CPU_R6000 ||
2355 current_cpu_type() == CPU_R6000A) {
2357 * The R6000 is the only R-series CPU that features a machine
2358 * check exception (similar to the R4000 cache error) and
2359 * unaligned ldc1/sdc1 exception. The handlers have not been
2360 * written yet. Well, anyway there is no R6000 machine on the
2361 * current list of targets for Linux/MIPS.
2362 * (Duh, crap, there is someone with a triple R6k machine)
2364 //set_except_vector(14, handle_mc);
2365 //set_except_vector(15, handle_ndc);
2369 if (board_nmi_handler_setup)
2370 board_nmi_handler_setup();
2372 if (cpu_has_fpu && !cpu_has_nofpuex)
2373 set_except_vector(EXCCODE_FPE, handle_fpe);
2375 set_except_vector(MIPS_EXCCODE_TLBPAR, handle_ftlb);
2377 if (cpu_has_rixiex) {
2378 set_except_vector(EXCCODE_TLBRI, tlb_do_page_fault_0);
2379 set_except_vector(EXCCODE_TLBXI, tlb_do_page_fault_0);
2382 set_except_vector(EXCCODE_MSADIS, handle_msa);
2383 set_except_vector(EXCCODE_MDMX, handle_mdmx);
2386 set_except_vector(EXCCODE_MCHECK, handle_mcheck);
2389 set_except_vector(EXCCODE_THREAD, handle_mt);
2391 set_except_vector(EXCCODE_DSPDIS, handle_dsp);
2393 if (board_cache_error_setup)
2394 board_cache_error_setup();
2397 /* Special exception: R4[04]00 uses also the divec space. */
2398 set_handler(0x180, &except_vec3_r4000, 0x100);
2399 else if (cpu_has_4kex)
2400 set_handler(0x180, &except_vec3_generic, 0x80);
2402 set_handler(0x080, &except_vec3_generic, 0x80);
2404 local_flush_icache_range(ebase, ebase + 0x400);
2406 sort_extable(__start___dbe_table, __stop___dbe_table);
2408 cu2_notifier(default_cu2_call, 0x80000000); /* Run last */
2411 static int trap_pm_notifier(struct notifier_block *self, unsigned long cmd,
2415 case CPU_PM_ENTER_FAILED:
2419 configure_exception_vector();
2421 /* Restore register with CPU number for TLB handlers */
2422 TLBMISS_HANDLER_RESTORE();
2430 static struct notifier_block trap_pm_notifier_block = {
2431 .notifier_call = trap_pm_notifier,
2434 static int __init trap_pm_init(void)
2436 return cpu_pm_register_notifier(&trap_pm_notifier_block);
2438 arch_initcall(trap_pm_init);