2 * Copyright (C) 2013 Imagination Technologies
3 * Author: Paul Burton <paul.burton@imgtec.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
11 #include <linux/delay.h>
13 #include <linux/irqchip/mips-gic.h>
14 #include <linux/sched.h>
15 #include <linux/slab.h>
16 #include <linux/smp.h>
17 #include <linux/types.h>
19 #include <asm/bcache.h>
20 #include <asm/mips-cm.h>
21 #include <asm/mips-cpc.h>
22 #include <asm/mips_mt.h>
23 #include <asm/mipsregs.h>
24 #include <asm/pm-cps.h>
25 #include <asm/r4kcache.h>
26 #include <asm/smp-cps.h>
30 static DECLARE_BITMAP(core_power, NR_CPUS);
32 struct core_boot_config *mips_cps_core_bootcfg;
34 static unsigned core_vpe_count(unsigned core)
38 if (!config_enabled(CONFIG_MIPS_MT_SMP) || !cpu_has_mipsmt)
41 mips_cm_lock_other(core, 0);
42 cfg = read_gcr_co_config() & CM_GCR_Cx_CONFIG_PVPE_MSK;
43 mips_cm_unlock_other();
44 return (cfg >> CM_GCR_Cx_CONFIG_PVPE_SHF) + 1;
47 static void __init cps_smp_setup(void)
49 unsigned int ncores, nvpes, core_vpes;
52 /* Detect & record VPE topology */
53 ncores = mips_cm_numcores();
54 pr_info("VPE topology ");
55 for (c = nvpes = 0; c < ncores; c++) {
56 core_vpes = core_vpe_count(c);
57 pr_cont("%c%u", c ? ',' : '{', core_vpes);
59 /* Use the number of VPEs in core 0 for smp_num_siblings */
61 smp_num_siblings = core_vpes;
63 for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) {
64 cpu_data[nvpes + v].core = c;
65 #ifdef CONFIG_MIPS_MT_SMP
66 cpu_data[nvpes + v].vpe_id = v;
72 pr_cont("} total %u\n", nvpes);
74 /* Indicate present CPUs (CPU being synonymous with VPE) */
75 for (v = 0; v < min_t(unsigned, nvpes, NR_CPUS); v++) {
76 set_cpu_possible(v, true);
77 set_cpu_present(v, true);
78 __cpu_number_map[v] = v;
79 __cpu_logical_map[v] = v;
82 /* Set a coherent default CCA (CWB) */
83 change_c0_config(CONF_CM_CMASK, 0x5);
85 /* Core 0 is powered up (we're running on it) */
86 bitmap_set(core_power, 0, 1);
88 /* Initialise core 0 */
91 /* Make core 0 coherent with everything */
92 write_gcr_cl_coherence(0xff);
94 #ifdef CONFIG_MIPS_MT_FPAFF
95 /* If we have an FPU, enroll ourselves in the FPU-full mask */
97 cpumask_set_cpu(0, &mt_fpu_cpumask);
98 #endif /* CONFIG_MIPS_MT_FPAFF */
101 static void __init cps_prepare_cpus(unsigned int max_cpus)
103 unsigned ncores, core_vpes, c, cca;
107 mips_mt_set_cpuoptions();
109 /* Detect whether the CCA is unsuited to multi-core SMP */
110 cca = read_c0_config() & CONF_CM_CMASK;
114 /* The CCA is coherent, multi-core is fine */
115 cca_unsuitable = false;
119 /* CCA is not coherent, multi-core is not usable */
120 cca_unsuitable = true;
123 /* Warn the user if the CCA prevents multi-core */
124 ncores = mips_cm_numcores();
125 if (cca_unsuitable && ncores > 1) {
126 pr_warn("Using only one core due to unsuitable CCA 0x%x\n",
129 for_each_present_cpu(c) {
130 if (cpu_data[c].core)
131 set_cpu_present(c, false);
136 * Patch the start of mips_cps_core_entry to provide:
140 entry_code = (u32 *)&mips_cps_core_entry;
141 uasm_i_addiu(&entry_code, 16, 0, cca);
142 blast_dcache_range((unsigned long)&mips_cps_core_entry,
143 (unsigned long)entry_code);
144 bc_wback_inv((unsigned long)&mips_cps_core_entry,
145 (void *)entry_code - (void *)&mips_cps_core_entry);
148 /* Allocate core boot configuration structs */
149 mips_cps_core_bootcfg = kcalloc(ncores, sizeof(*mips_cps_core_bootcfg),
151 if (!mips_cps_core_bootcfg) {
152 pr_err("Failed to allocate boot config for %u cores\n", ncores);
156 /* Allocate VPE boot configuration structs */
157 for (c = 0; c < ncores; c++) {
158 core_vpes = core_vpe_count(c);
159 mips_cps_core_bootcfg[c].vpe_config = kcalloc(core_vpes,
160 sizeof(*mips_cps_core_bootcfg[c].vpe_config),
162 if (!mips_cps_core_bootcfg[c].vpe_config) {
163 pr_err("Failed to allocate %u VPE boot configs\n",
169 /* Mark this CPU as booted */
170 atomic_set(&mips_cps_core_bootcfg[current_cpu_data.core].vpe_mask,
171 1 << cpu_vpe_id(¤t_cpu_data));
175 /* Clean up allocations */
176 if (mips_cps_core_bootcfg) {
177 for (c = 0; c < ncores; c++)
178 kfree(mips_cps_core_bootcfg[c].vpe_config);
179 kfree(mips_cps_core_bootcfg);
180 mips_cps_core_bootcfg = NULL;
183 /* Effectively disable SMP by declaring CPUs not present */
184 for_each_possible_cpu(c) {
187 set_cpu_present(c, false);
191 static void boot_core(unsigned core)
193 u32 access, stat, seq_state;
196 /* Select the appropriate core */
197 mips_cm_lock_other(core, 0);
199 /* Set its reset vector */
200 write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry));
202 /* Ensure its coherency is disabled */
203 write_gcr_co_coherence(0);
205 /* Start it with the legacy memory map and exception base */
206 write_gcr_co_reset_ext_base(CM_GCR_RESET_EXT_BASE_UEB);
208 /* Ensure the core can access the GCRs */
209 access = read_gcr_access();
210 access |= 1 << (CM_GCR_ACCESS_ACCESSEN_SHF + core);
211 write_gcr_access(access);
213 if (mips_cpc_present()) {
215 mips_cpc_lock_other(core);
216 write_cpc_co_cmd(CPC_Cx_CMD_RESET);
220 stat = read_cpc_co_stat_conf();
221 seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE_MSK;
223 /* U6 == coherent execution, ie. the core is up */
224 if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U6)
227 /* Delay a little while before we start warning */
234 pr_warn("Waiting for core %u to start... STAT_CONF=0x%x\n",
239 mips_cpc_unlock_other();
241 /* Take the core out of reset */
242 write_gcr_co_reset_release(0);
245 mips_cm_unlock_other();
247 /* The core is now powered up */
248 bitmap_set(core_power, core, 1);
251 static void remote_vpe_boot(void *dummy)
253 mips_cps_boot_vpes();
256 static void cps_boot_secondary(int cpu, struct task_struct *idle)
258 unsigned core = cpu_data[cpu].core;
259 unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
260 struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
261 struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id];
265 vpe_cfg->pc = (unsigned long)&smp_bootstrap;
266 vpe_cfg->sp = __KSTK_TOS(idle);
267 vpe_cfg->gp = (unsigned long)task_thread_info(idle);
269 atomic_or(1 << cpu_vpe_id(&cpu_data[cpu]), &core_cfg->vpe_mask);
273 if (!test_bit(core, core_power)) {
274 /* Boot a VPE on a powered down core */
279 if (core != current_cpu_data.core) {
280 /* Boot a VPE on another powered up core */
281 for (remote = 0; remote < NR_CPUS; remote++) {
282 if (cpu_data[remote].core != core)
284 if (cpu_online(remote))
287 BUG_ON(remote >= NR_CPUS);
289 err = smp_call_function_single(remote, remote_vpe_boot,
292 panic("Failed to call remote CPU\n");
296 BUG_ON(!cpu_has_mipsmt);
298 /* Boot a VPE on this core */
299 mips_cps_boot_vpes();
304 static void cps_init_secondary(void)
306 /* Disable MT - we only want to run 1 TC per VPE */
310 change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP4 |
311 STATUSF_IP5 | STATUSF_IP6 | STATUSF_IP7);
314 static void cps_smp_finish(void)
316 write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ));
318 #ifdef CONFIG_MIPS_MT_FPAFF
319 /* If we have an FPU, enroll ourselves in the FPU-full mask */
321 cpumask_set_cpu(smp_processor_id(), &mt_fpu_cpumask);
322 #endif /* CONFIG_MIPS_MT_FPAFF */
327 #ifdef CONFIG_HOTPLUG_CPU
329 static int cps_cpu_disable(void)
331 unsigned cpu = smp_processor_id();
332 struct core_boot_config *core_cfg;
337 if (!cps_pm_support_state(CPS_PM_POWER_GATED))
340 core_cfg = &mips_cps_core_bootcfg[current_cpu_data.core];
341 atomic_sub(1 << cpu_vpe_id(¤t_cpu_data), &core_cfg->vpe_mask);
342 smp_mb__after_atomic();
343 set_cpu_online(cpu, false);
344 cpumask_clear_cpu(cpu, &cpu_callin_map);
349 static DECLARE_COMPLETION(cpu_death_chosen);
350 static unsigned cpu_death_sibling;
362 cpu = smp_processor_id();
363 cpu_death = CPU_DEATH_POWER;
365 if (cpu_has_mipsmt) {
366 core = cpu_data[cpu].core;
368 /* Look for another online VPE within the core */
369 for_each_online_cpu(cpu_death_sibling) {
370 if (cpu_data[cpu_death_sibling].core != core)
374 * There is an online VPE within the core. Just halt
375 * this TC and leave the core alone.
377 cpu_death = CPU_DEATH_HALT;
382 /* This CPU has chosen its way out */
383 complete(&cpu_death_chosen);
385 if (cpu_death == CPU_DEATH_HALT) {
387 write_c0_tchalt(TCHALT_H);
388 instruction_hazard();
390 /* Power down the core */
391 cps_pm_enter_state(CPS_PM_POWER_GATED);
394 /* This should never be reached */
395 panic("Failed to offline CPU %u", cpu);
398 static void wait_for_sibling_halt(void *ptr_cpu)
400 unsigned cpu = (unsigned long)ptr_cpu;
401 unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
406 local_irq_save(flags);
408 halted = read_tc_c0_tchalt();
409 local_irq_restore(flags);
410 } while (!(halted & TCHALT_H));
413 static void cps_cpu_die(unsigned int cpu)
415 unsigned core = cpu_data[cpu].core;
419 /* Wait for the cpu to choose its way out */
420 if (!wait_for_completion_timeout(&cpu_death_chosen,
421 msecs_to_jiffies(5000))) {
422 pr_err("CPU%u: didn't offline\n", cpu);
427 * Now wait for the CPU to actually offline. Without doing this that
428 * offlining may race with one or more of:
430 * - Onlining the CPU again.
431 * - Powering down the core if another VPE within it is offlined.
432 * - A sibling VPE entering a non-coherent state.
434 * In the non-MT halt case (ie. infinite loop) the CPU is doing nothing
435 * with which we could race, so do nothing.
437 if (cpu_death == CPU_DEATH_POWER) {
439 * Wait for the core to enter a powered down or clock gated
440 * state, the latter happening when a JTAG probe is connected
441 * in which case the CPC will refuse to power down the core.
444 mips_cpc_lock_other(core);
445 stat = read_cpc_co_stat_conf();
446 stat &= CPC_Cx_STAT_CONF_SEQSTATE_MSK;
447 mips_cpc_unlock_other();
448 } while (stat != CPC_Cx_STAT_CONF_SEQSTATE_D0 &&
449 stat != CPC_Cx_STAT_CONF_SEQSTATE_D2 &&
450 stat != CPC_Cx_STAT_CONF_SEQSTATE_U2);
452 /* Indicate the core is powered off */
453 bitmap_clear(core_power, core, 1);
454 } else if (cpu_has_mipsmt) {
456 * Have a CPU with access to the offlined CPUs registers wait
457 * for its TC to halt.
459 err = smp_call_function_single(cpu_death_sibling,
460 wait_for_sibling_halt,
461 (void *)(unsigned long)cpu, 1);
463 panic("Failed to call remote sibling CPU\n");
467 #endif /* CONFIG_HOTPLUG_CPU */
469 static struct plat_smp_ops cps_smp_ops = {
470 .smp_setup = cps_smp_setup,
471 .prepare_cpus = cps_prepare_cpus,
472 .boot_secondary = cps_boot_secondary,
473 .init_secondary = cps_init_secondary,
474 .smp_finish = cps_smp_finish,
475 .send_ipi_single = mips_smp_send_ipi_single,
476 .send_ipi_mask = mips_smp_send_ipi_mask,
477 #ifdef CONFIG_HOTPLUG_CPU
478 .cpu_disable = cps_cpu_disable,
479 .cpu_die = cps_cpu_die,
483 bool mips_cps_smp_in_use(void)
485 extern struct plat_smp_ops *mp_ops;
486 return mp_ops == &cps_smp_ops;
489 int register_cps_smp_ops(void)
491 if (!mips_cm_present()) {
492 pr_warn("MIPS CPS SMP unable to proceed without a CM\n");
496 /* check we have a GIC - we need one for IPIs */
497 if (!(read_gcr_gic_status() & CM_GCR_GIC_STATUS_EX_MSK)) {
498 pr_warn("MIPS CPS SMP unable to proceed without a GIC\n");
502 register_smp_ops(&cps_smp_ops);