arch/mips/kernel/cpu-probe.c

   1 /*
   2  * Processor capabilities determination functions.
   3  *
   4  * Copyright (C) xxxx  the Anonymous
   5  * Copyright (C) 1994 - 2006 Ralf Baechle
   6  * Copyright (C) 2003, 2004  Maciej W. Rozycki
   7  * Copyright (C) 2001, 2004, 2011, 2012  MIPS Technologies, Inc.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  */
  14 #include <linux/init.h>
  15 #include <linux/kernel.h>
  16 #include <linux/ptrace.h>
  17 #include <linux/smp.h>
  18 #include <linux/stddef.h>
  19 #include <linux/export.h>
  20
  21 #include <asm/bugs.h>
  22 #include <asm/cpu.h>
  23 #include <asm/cpu-features.h>
  24 #include <asm/cpu-type.h>
  25 #include <asm/fpu.h>
  26 #include <asm/mipsregs.h>
  27 #include <asm/mipsmtregs.h>
  28 #include <asm/msa.h>
  29 #include <asm/watch.h>
  30 #include <asm/elf.h>
  31 #include <asm/pgtable-bits.h>
  32 #include <asm/spram.h>
  33 #include <asm/uaccess.h>
  34
  35 /*
  36  * Get the FPU Implementation/Revision.
  37  */
  38 static inline unsigned long cpu_get_fpu_id(void)
  39 {
  40         unsigned long tmp, fpu_id;
  41
  42         tmp = read_c0_status();
  43         __enable_fpu(FPU_AS_IS);
  44         fpu_id = read_32bit_cp1_register(CP1_REVISION);
  45         write_c0_status(tmp);
  46         return fpu_id;
  47 }
  48
  49 /*
  50  * Check if the CPU has an external FPU.
  51  */
  52 static inline int __cpu_has_fpu(void)
  53 {
  54         return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
  55 }
  56
  57 static inline unsigned long cpu_get_msa_id(void)
  58 {
  59         unsigned long status, msa_id;
  60
  61         status = read_c0_status();
  62         __enable_fpu(FPU_64BIT);
  63         enable_msa();
  64         msa_id = read_msa_ir();
  65         disable_msa();
  66         write_c0_status(status);
  67         return msa_id;
  68 }
  69
  70 /*
  71  * Determine the FCSR mask for FPU hardware.
  72  */
  73 static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c)
  74 {
  75         unsigned long sr, mask, fcsr, fcsr0, fcsr1;
  76
  77         fcsr = c->fpu_csr31;
  78         mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
  79
  80         sr = read_c0_status();
  81         __enable_fpu(FPU_AS_IS);
  82
  83         fcsr0 = fcsr & mask;
  84         write_32bit_cp1_register(CP1_STATUS, fcsr0);
  85         fcsr0 = read_32bit_cp1_register(CP1_STATUS);
  86
  87         fcsr1 = fcsr | ~mask;
  88         write_32bit_cp1_register(CP1_STATUS, fcsr1);
  89         fcsr1 = read_32bit_cp1_register(CP1_STATUS);
  90
  91         write_32bit_cp1_register(CP1_STATUS, fcsr);
  92
  93         write_c0_status(sr);
  94
  95         c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask;
  96 }
  97
  98 /*
  99  * Set the FIR feature flags for the FPU emulator.
 100  */
 101 static void cpu_set_nofpu_id(struct cpuinfo_mips *c)
 102 {
 103         u32 value;
 104
 105         value = 0;
 106         if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
 107                             MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
 108                             MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
 109                 value |= MIPS_FPIR_D | MIPS_FPIR_S;
 110         if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
 111                             MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
 112                 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W;
 113         c->fpu_id = value;
 114 }
 115
 116 /* Determined FPU emulator mask to use for the boot CPU with "nofpu".  */
 117 static unsigned int mips_nofpu_msk31;
 118
 119 /*
 120  * Set options for FPU hardware.
 121  */
 122 static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
 123 {
 124         c->fpu_id = cpu_get_fpu_id();
 125         mips_nofpu_msk31 = c->fpu_msk31;
 126
 127         if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
 128                             MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
 129                             MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
 130                 if (c->fpu_id & MIPS_FPIR_3D)
 131                         c->ases |= MIPS_ASE_MIPS3D;
 132                 if (c->fpu_id & MIPS_FPIR_FREP)
 133                         c->options |= MIPS_CPU_FRE;
 134         }
 135
 136         cpu_set_fpu_fcsr_mask(c);
 137 }
 138
 139 /*
 140  * Set options for the FPU emulator.
 141  */
 142 static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
 143 {
 144         c->options &= ~MIPS_CPU_FPU;
 145         c->fpu_msk31 = mips_nofpu_msk31;
 146
 147         cpu_set_nofpu_id(c);
 148 }
 149
 150 static int mips_fpu_disabled;
 151
 152 static int __init fpu_disable(char *s)
 153 {
 154         cpu_set_nofpu_opts(&boot_cpu_data);
 155         mips_fpu_disabled = 1;
 156
 157         return 1;
 158 }
 159
 160 __setup("nofpu", fpu_disable);
 161
 162 int mips_dsp_disabled;
 163
 164 static int __init dsp_disable(char *s)
 165 {
 166         cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
 167         mips_dsp_disabled = 1;
 168
 169         return 1;
 170 }
 171
 172 __setup("nodsp", dsp_disable);
 173
 174 static int mips_htw_disabled;
 175
 176 static int __init htw_disable(char *s)
 177 {
 178         mips_htw_disabled = 1;
 179         cpu_data[0].options &= ~MIPS_CPU_HTW;
 180         write_c0_pwctl(read_c0_pwctl() &
 181                        ~(1 << MIPS_PWCTL_PWEN_SHIFT));
 182
 183         return 1;
 184 }
 185
 186 __setup("nohtw", htw_disable);
 187
 188 static int mips_ftlb_disabled;
 189 static int mips_has_ftlb_configured;
 190
 191 static int set_ftlb_enable(struct cpuinfo_mips *c, int enable);
 192
 193 static int __init ftlb_disable(char *s)
 194 {
 195         unsigned int config4, mmuextdef;
 196
 197         /*
 198          * If the core hasn't done any FTLB configuration, there is nothing
 199          * for us to do here.
 200          */
 201         if (!mips_has_ftlb_configured)
 202                 return 1;
 203
 204         /* Disable it in the boot cpu */
 205         if (set_ftlb_enable(&cpu_data[0], 0)) {
 206                 pr_warn("Can't turn FTLB off\n");
 207                 return 1;
 208         }
 209
 210         back_to_back_c0_hazard();
 211
 212         config4 = read_c0_config4();
 213
 214         /* Check that FTLB has been disabled */
 215         mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
 216         /* MMUSIZEEXT == VTLB ON, FTLB OFF */
 217         if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
 218                 /* This should never happen */
 219                 pr_warn("FTLB could not be disabled!\n");
 220                 return 1;
 221         }
 222
 223         mips_ftlb_disabled = 1;
 224         mips_has_ftlb_configured = 0;
 225
 226         /*
 227          * noftlb is mainly used for debug purposes so print
 228          * an informative message instead of using pr_debug()
 229          */
 230         pr_info("FTLB has been disabled\n");
 231
 232         /*
 233          * Some of these bits are duplicated in the decode_config4.
 234          * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
 235          * once FTLB has been disabled so undo what decode_config4 did.
 236          */
 237         cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
 238                                cpu_data[0].tlbsizeftlbsets;
 239         cpu_data[0].tlbsizeftlbsets = 0;
 240         cpu_data[0].tlbsizeftlbways = 0;
 241
 242         return 1;
 243 }
 244
 245 __setup("noftlb", ftlb_disable);
 246
 247
 248 static inline void check_errata(void)
 249 {
 250         struct cpuinfo_mips *c = &current_cpu_data;
 251
 252         switch (current_cpu_type()) {
 253         case CPU_34K:
 254                 /*
 255                  * Erratum "RPS May Cause Incorrect Instruction Execution"
 256                  * This code only handles VPE0, any SMP/RTOS code
 257                  * making use of VPE1 will be responsable for that VPE.
 258                  */
 259                 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
 260                         write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
 261                 break;
 262         default:
 263                 break;
 264         }
 265 }
 266
 267 void __init check_bugs32(void)
 268 {
 269         check_errata();
 270 }
 271
 272 /*
 273  * Probe whether cpu has config register by trying to play with
 274  * alternate cache bit and see whether it matters.
 275  * It's used by cpu_probe to distinguish between R3000A and R3081.
 276  */
 277 static inline int cpu_has_confreg(void)
 278 {
 279 #ifdef CONFIG_CPU_R3000
 280         extern unsigned long r3k_cache_size(unsigned long);
 281         unsigned long size1, size2;
 282         unsigned long cfg = read_c0_conf();
 283
 284         size1 = r3k_cache_size(ST0_ISC);
 285         write_c0_conf(cfg ^ R30XX_CONF_AC);
 286         size2 = r3k_cache_size(ST0_ISC);
 287         write_c0_conf(cfg);
 288         return size1 != size2;
 289 #else
 290         return 0;
 291 #endif
 292 }
 293
 294 static inline void set_elf_platform(int cpu, const char *plat)
 295 {
 296         if (cpu == 0)
 297                 __elf_platform = plat;
 298 }
 299
 300 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
 301 {
 302 #ifdef __NEED_VMBITS_PROBE
 303         write_c0_entryhi(0x3fffffffffffe000ULL);
 304         back_to_back_c0_hazard();
 305         c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
 306 #endif
 307 }
 308
 309 static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
 310 {
 311         switch (isa) {
 312         case MIPS_CPU_ISA_M64R2:
 313                 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
 314         case MIPS_CPU_ISA_M64R1:
 315                 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
 316         case MIPS_CPU_ISA_V:
 317                 c->isa_level |= MIPS_CPU_ISA_V;
 318         case MIPS_CPU_ISA_IV:
 319                 c->isa_level |= MIPS_CPU_ISA_IV;
 320         case MIPS_CPU_ISA_III:
 321                 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
 322                 break;
 323
 324         /* R6 incompatible with everything else */
 325         case MIPS_CPU_ISA_M64R6:
 326                 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
 327         case MIPS_CPU_ISA_M32R6:
 328                 c->isa_level |= MIPS_CPU_ISA_M32R6;
 329                 /* Break here so we don't add incompatible ISAs */
 330                 break;
 331         case MIPS_CPU_ISA_M32R2:
 332                 c->isa_level |= MIPS_CPU_ISA_M32R2;
 333         case MIPS_CPU_ISA_M32R1:
 334                 c->isa_level |= MIPS_CPU_ISA_M32R1;
 335         case MIPS_CPU_ISA_II:
 336                 c->isa_level |= MIPS_CPU_ISA_II;
 337                 break;
 338         }
 339 }
 340
 341 static char unknown_isa[] = KERN_ERR \
 342         "Unsupported ISA type, c0.config0: %d.";
 343
 344 static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
 345 {
 346
 347         unsigned int probability = c->tlbsize / c->tlbsizevtlb;
 348
 349         /*
 350          * 0 = All TLBWR instructions go to FTLB
 351          * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
 352          * FTLB and 1 goes to the VTLB.
 353          * 2 = 7:1: As above with 7:1 ratio.
 354          * 3 = 3:1: As above with 3:1 ratio.
 355          *
 356          * Use the linear midpoint as the probability threshold.
 357          */
 358         if (probability >= 12)
 359                 return 1;
 360         else if (probability >= 6)
 361                 return 2;
 362         else
 363                 /*
 364                  * So FTLB is less than 4 times bigger than VTLB.
 365                  * A 3:1 ratio can still be useful though.
 366                  */
 367                 return 3;
 368 }
 369
 370 static int set_ftlb_enable(struct cpuinfo_mips *c, int enable)
 371 {
 372         unsigned int config;
 373
 374         /* It's implementation dependent how the FTLB can be enabled */
 375         switch (c->cputype) {
 376         case CPU_PROAPTIV:
 377         case CPU_P5600:
 378                 /* proAptiv & related cores use Config6 to enable the FTLB */
 379                 config = read_c0_config6();
 380                 /* Clear the old probability value */
 381                 config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
 382                 if (enable)
 383                         /* Enable FTLB */
 384                         write_c0_config6(config |
 385                                          (calculate_ftlb_probability(c)
 386                                           << MIPS_CONF6_FTLBP_SHIFT)
 387                                          | MIPS_CONF6_FTLBEN);
 388                 else
 389                         /* Disable FTLB */
 390                         write_c0_config6(config &  ~MIPS_CONF6_FTLBEN);
 391                 break;
 392         case CPU_I6400:
 393                 /* I6400 & related cores use Config7 to configure FTLB */
 394                 config = read_c0_config7();
 395                 /* Clear the old probability value */
 396                 config &= ~(3 << MIPS_CONF7_FTLBP_SHIFT);
 397                 write_c0_config7(config | (calculate_ftlb_probability(c)
 398                                            << MIPS_CONF7_FTLBP_SHIFT));
 399                 break;
 400         default:
 401                 return 1;
 402         }
 403
 404         return 0;
 405 }
 406
 407 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
 408 {
 409         unsigned int config0;
 410         int isa;
 411
 412         config0 = read_c0_config();
 413
 414         /*
 415          * Look for Standard TLB or Dual VTLB and FTLB
 416          */
 417         if ((((config0 & MIPS_CONF_MT) >> 7) == 1) ||
 418             (((config0 & MIPS_CONF_MT) >> 7) == 4))
 419                 c->options |= MIPS_CPU_TLB;
 420
 421         isa = (config0 & MIPS_CONF_AT) >> 13;
 422         switch (isa) {
 423         case 0:
 424                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 425                 case 0:
 426                         set_isa(c, MIPS_CPU_ISA_M32R1);
 427                         break;
 428                 case 1:
 429                         set_isa(c, MIPS_CPU_ISA_M32R2);
 430                         break;
 431                 case 2:
 432                         set_isa(c, MIPS_CPU_ISA_M32R6);
 433                         break;
 434                 default:
 435                         goto unknown;
 436                 }
 437                 break;
 438         case 2:
 439                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 440                 case 0:
 441                         set_isa(c, MIPS_CPU_ISA_M64R1);
 442                         break;
 443                 case 1:
 444                         set_isa(c, MIPS_CPU_ISA_M64R2);
 445                         break;
 446                 case 2:
 447                         set_isa(c, MIPS_CPU_ISA_M64R6);
 448                         break;
 449                 default:
 450                         goto unknown;
 451                 }
 452                 break;
 453         default:
 454                 goto unknown;
 455         }
 456
 457         return config0 & MIPS_CONF_M;
 458
 459 unknown:
 460         panic(unknown_isa, config0);
 461 }
 462
 463 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
 464 {
 465         unsigned int config1;
 466
 467         config1 = read_c0_config1();
 468
 469         if (config1 & MIPS_CONF1_MD)
 470                 c->ases |= MIPS_ASE_MDMX;
 471         if (config1 & MIPS_CONF1_WR)
 472                 c->options |= MIPS_CPU_WATCH;
 473         if (config1 & MIPS_CONF1_CA)
 474                 c->ases |= MIPS_ASE_MIPS16;
 475         if (config1 & MIPS_CONF1_EP)
 476                 c->options |= MIPS_CPU_EJTAG;
 477         if (config1 & MIPS_CONF1_FP) {
 478                 c->options |= MIPS_CPU_FPU;
 479                 c->options |= MIPS_CPU_32FPR;
 480         }
 481         if (cpu_has_tlb) {
 482                 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
 483                 c->tlbsizevtlb = c->tlbsize;
 484                 c->tlbsizeftlbsets = 0;
 485         }
 486
 487         return config1 & MIPS_CONF_M;
 488 }
 489
 490 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
 491 {
 492         unsigned int config2;
 493
 494         config2 = read_c0_config2();
 495
 496         if (config2 & MIPS_CONF2_SL)
 497                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
 498
 499         return config2 & MIPS_CONF_M;
 500 }
 501
 502 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
 503 {
 504         unsigned int config3;
 505
 506         config3 = read_c0_config3();
 507
 508         if (config3 & MIPS_CONF3_SM) {
 509                 c->ases |= MIPS_ASE_SMARTMIPS;
 510                 c->options |= MIPS_CPU_RIXI;
 511         }
 512         if (config3 & MIPS_CONF3_RXI)
 513                 c->options |= MIPS_CPU_RIXI;
 514         if (config3 & MIPS_CONF3_DSP)
 515                 c->ases |= MIPS_ASE_DSP;
 516         if (config3 & MIPS_CONF3_DSP2P)
 517                 c->ases |= MIPS_ASE_DSP2P;
 518         if (config3 & MIPS_CONF3_VINT)
 519                 c->options |= MIPS_CPU_VINT;
 520         if (config3 & MIPS_CONF3_VEIC)
 521                 c->options |= MIPS_CPU_VEIC;
 522         if (config3 & MIPS_CONF3_MT)
 523                 c->ases |= MIPS_ASE_MIPSMT;
 524         if (config3 & MIPS_CONF3_ULRI)
 525                 c->options |= MIPS_CPU_ULRI;
 526         if (config3 & MIPS_CONF3_ISA)
 527                 c->options |= MIPS_CPU_MICROMIPS;
 528         if (config3 & MIPS_CONF3_VZ)
 529                 c->ases |= MIPS_ASE_VZ;
 530         if (config3 & MIPS_CONF3_SC)
 531                 c->options |= MIPS_CPU_SEGMENTS;
 532         if (config3 & MIPS_CONF3_MSA)
 533                 c->ases |= MIPS_ASE_MSA;
 534         /* Only tested on 32-bit cores */
 535         if ((config3 & MIPS_CONF3_PW) && config_enabled(CONFIG_32BIT)) {
 536                 c->htw_seq = 0;
 537                 c->options |= MIPS_CPU_HTW;
 538         }
 539         if (config3 & MIPS_CONF3_CDMM)
 540                 c->options |= MIPS_CPU_CDMM;
 541
 542         return config3 & MIPS_CONF_M;
 543 }
 544
 545 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
 546 {
 547         unsigned int config4;
 548         unsigned int newcf4;
 549         unsigned int mmuextdef;
 550         unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
 551
 552         config4 = read_c0_config4();
 553
 554         if (cpu_has_tlb) {
 555                 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
 556                         c->options |= MIPS_CPU_TLBINV;
 557                 /*
 558                  * This is a bit ugly. R6 has dropped that field from
 559                  * config4 and the only valid configuration is VTLB+FTLB so
 560                  * set a good value for mmuextdef for that case.
 561                  */
 562                 if (cpu_has_mips_r6)
 563                         mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT;
 564                 else
 565                         mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
 566
 567                 switch (mmuextdef) {
 568                 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
 569                         c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
 570                         c->tlbsizevtlb = c->tlbsize;
 571                         break;
 572                 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
 573                         c->tlbsizevtlb +=
 574                                 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
 575                                   MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
 576                         c->tlbsize = c->tlbsizevtlb;
 577                         ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
 578                         /* fall through */
 579                 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
 580                         if (mips_ftlb_disabled)
 581                                 break;
 582                         newcf4 = (config4 & ~ftlb_page) |
 583                                 (page_size_ftlb(mmuextdef) <<
 584                                  MIPS_CONF4_FTLBPAGESIZE_SHIFT);
 585                         write_c0_config4(newcf4);
 586                         back_to_back_c0_hazard();
 587                         config4 = read_c0_config4();
 588                         if (config4 != newcf4) {
 589                                 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
 590                                        PAGE_SIZE, config4);
 591                                 /* Switch FTLB off */
 592                                 set_ftlb_enable(c, 0);
 593                                 break;
 594                         }
 595                         c->tlbsizeftlbsets = 1 <<
 596                                 ((config4 & MIPS_CONF4_FTLBSETS) >>
 597                                  MIPS_CONF4_FTLBSETS_SHIFT);
 598                         c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
 599                                               MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
 600                         c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
 601                         mips_has_ftlb_configured = 1;
 602                         break;
 603                 }
 604         }
 605
 606         c->kscratch_mask = (config4 >> 16) & 0xff;
 607
 608         return config4 & MIPS_CONF_M;
 609 }
 610
 611 static inline unsigned int decode_config5(struct cpuinfo_mips *c)
 612 {
 613         unsigned int config5;
 614
 615         config5 = read_c0_config5();
 616         config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
 617         write_c0_config5(config5);
 618
 619         if (config5 & MIPS_CONF5_EVA)
 620                 c->options |= MIPS_CPU_EVA;
 621         if (config5 & MIPS_CONF5_MRP)
 622                 c->options |= MIPS_CPU_MAAR;
 623         if (config5 & MIPS_CONF5_LLB)
 624                 c->options |= MIPS_CPU_RW_LLB;
 625 #ifdef CONFIG_XPA
 626         if (config5 & MIPS_CONF5_MVH)
 627                 c->options |= MIPS_CPU_XPA;
 628 #endif
 629
 630         return config5 & MIPS_CONF_M;
 631 }
 632
 633 static void decode_configs(struct cpuinfo_mips *c)
 634 {
 635         int ok;
 636
 637         /* MIPS32 or MIPS64 compliant CPU.  */
 638         c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
 639                      MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
 640
 641         c->scache.flags = MIPS_CACHE_NOT_PRESENT;
 642
 643         /* Enable FTLB if present and not disabled */
 644         set_ftlb_enable(c, !mips_ftlb_disabled);
 645
 646         ok = decode_config0(c);                 /* Read Config registers.  */
 647         BUG_ON(!ok);                            /* Arch spec violation!  */
 648         if (ok)
 649                 ok = decode_config1(c);
 650         if (ok)
 651                 ok = decode_config2(c);
 652         if (ok)
 653                 ok = decode_config3(c);
 654         if (ok)
 655                 ok = decode_config4(c);
 656         if (ok)
 657                 ok = decode_config5(c);
 658
 659         mips_probe_watch_registers(c);
 660
 661         if (cpu_has_rixi) {
 662                 /* Enable the RIXI exceptions */
 663                 set_c0_pagegrain(PG_IEC);
 664                 back_to_back_c0_hazard();
 665                 /* Verify the IEC bit is set */
 666                 if (read_c0_pagegrain() & PG_IEC)
 667                         c->options |= MIPS_CPU_RIXIEX;
 668         }
 669
 670 #ifndef CONFIG_MIPS_CPS
 671         if (cpu_has_mips_r2_r6) {
 672                 c->core = get_ebase_cpunum();
 673                 if (cpu_has_mipsmt)
 674                         c->core >>= fls(core_nvpes()) - 1;
 675         }
 676 #endif
 677 }
 678
 679 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
 680                 | MIPS_CPU_COUNTER)
 681
 682 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
 683 {
 684         switch (c->processor_id & PRID_IMP_MASK) {
 685         case PRID_IMP_R2000:
 686                 c->cputype = CPU_R2000;
 687                 __cpu_name[cpu] = "R2000";
 688                 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
 689                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 690                              MIPS_CPU_NOFPUEX;
 691                 if (__cpu_has_fpu())
 692                         c->options |= MIPS_CPU_FPU;
 693                 c->tlbsize = 64;
 694                 break;
 695         case PRID_IMP_R3000:
 696                 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
 697                         if (cpu_has_confreg()) {
 698                                 c->cputype = CPU_R3081E;
 699                                 __cpu_name[cpu] = "R3081";
 700                         } else {
 701                                 c->cputype = CPU_R3000A;
 702                                 __cpu_name[cpu] = "R3000A";
 703                         }
 704                 } else {
 705                         c->cputype = CPU_R3000;
 706                         __cpu_name[cpu] = "R3000";
 707                 }
 708                 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
 709                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 710                              MIPS_CPU_NOFPUEX;
 711                 if (__cpu_has_fpu())
 712                         c->options |= MIPS_CPU_FPU;
 713                 c->tlbsize = 64;
 714                 break;
 715         case PRID_IMP_R4000:
 716                 if (read_c0_config() & CONF_SC) {
 717                         if ((c->processor_id & PRID_REV_MASK) >=
 718                             PRID_REV_R4400) {
 719                                 c->cputype = CPU_R4400PC;
 720                                 __cpu_name[cpu] = "R4400PC";
 721                         } else {
 722                                 c->cputype = CPU_R4000PC;
 723                                 __cpu_name[cpu] = "R4000PC";
 724                         }
 725                 } else {
 726                         int cca = read_c0_config() & CONF_CM_CMASK;
 727                         int mc;
 728
 729                         /*
 730                          * SC and MC versions can't be reliably told apart,
 731                          * but only the latter support coherent caching
 732                          * modes so assume the firmware has set the KSEG0
 733                          * coherency attribute reasonably (if uncached, we
 734                          * assume SC).
 735                          */
 736                         switch (cca) {
 737                         case CONF_CM_CACHABLE_CE:
 738                         case CONF_CM_CACHABLE_COW:
 739                         case CONF_CM_CACHABLE_CUW:
 740                                 mc = 1;
 741                                 break;
 742                         default:
 743                                 mc = 0;
 744                                 break;
 745                         }
 746                         if ((c->processor_id & PRID_REV_MASK) >=
 747                             PRID_REV_R4400) {
 748                                 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
 749                                 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
 750                         } else {
 751                                 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
 752                                 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
 753                         }
 754                 }
 755
 756                 set_isa(c, MIPS_CPU_ISA_III);
 757                 c->fpu_msk31 |= FPU_CSR_CONDX;
 758                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 759                              MIPS_CPU_WATCH | MIPS_CPU_VCE |
 760                              MIPS_CPU_LLSC;
 761                 c->tlbsize = 48;
 762                 break;
 763         case PRID_IMP_VR41XX:
 764                 set_isa(c, MIPS_CPU_ISA_III);
 765                 c->fpu_msk31 |= FPU_CSR_CONDX;
 766                 c->options = R4K_OPTS;
 767                 c->tlbsize = 32;
 768                 switch (c->processor_id & 0xf0) {
 769                 case PRID_REV_VR4111:
 770                         c->cputype = CPU_VR4111;
 771                         __cpu_name[cpu] = "NEC VR4111";
 772                         break;
 773                 case PRID_REV_VR4121:
 774                         c->cputype = CPU_VR4121;
 775                         __cpu_name[cpu] = "NEC VR4121";
 776                         break;
 777                 case PRID_REV_VR4122:
 778                         if ((c->processor_id & 0xf) < 0x3) {
 779                                 c->cputype = CPU_VR4122;
 780                                 __cpu_name[cpu] = "NEC VR4122";
 781                         } else {
 782                                 c->cputype = CPU_VR4181A;
 783                                 __cpu_name[cpu] = "NEC VR4181A";
 784                         }
 785                         break;
 786                 case PRID_REV_VR4130:
 787                         if ((c->processor_id & 0xf) < 0x4) {
 788                                 c->cputype = CPU_VR4131;
 789                                 __cpu_name[cpu] = "NEC VR4131";
 790                         } else {
 791                                 c->cputype = CPU_VR4133;
 792                                 c->options |= MIPS_CPU_LLSC;
 793                                 __cpu_name[cpu] = "NEC VR4133";
 794                         }
 795                         break;
 796                 default:
 797                         printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
 798                         c->cputype = CPU_VR41XX;
 799                         __cpu_name[cpu] = "NEC Vr41xx";
 800                         break;
 801                 }
 802                 break;
 803         case PRID_IMP_R4300:
 804                 c->cputype = CPU_R4300;
 805                 __cpu_name[cpu] = "R4300";
 806                 set_isa(c, MIPS_CPU_ISA_III);
 807                 c->fpu_msk31 |= FPU_CSR_CONDX;
 808                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 809                              MIPS_CPU_LLSC;
 810                 c->tlbsize = 32;
 811                 break;
 812         case PRID_IMP_R4600:
 813                 c->cputype = CPU_R4600;
 814                 __cpu_name[cpu] = "R4600";
 815                 set_isa(c, MIPS_CPU_ISA_III);
 816                 c->fpu_msk31 |= FPU_CSR_CONDX;
 817                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 818                              MIPS_CPU_LLSC;
 819                 c->tlbsize = 48;
 820                 break;
 821         #if 0
 822         case PRID_IMP_R4650:
 823                 /*
 824                  * This processor doesn't have an MMU, so it's not
 825                  * "real easy" to run Linux on it. It is left purely
 826                  * for documentation.  Commented out because it shares
 827                  * it's c0_prid id number with the TX3900.
 828                  */
 829                 c->cputype = CPU_R4650;
 830                 __cpu_name[cpu] = "R4650";
 831                 set_isa(c, MIPS_CPU_ISA_III);
 832                 c->fpu_msk31 |= FPU_CSR_CONDX;
 833                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
 834                 c->tlbsize = 48;
 835                 break;
 836         #endif
 837         case PRID_IMP_TX39:
 838                 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
 839                 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
 840
 841                 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
 842                         c->cputype = CPU_TX3927;
 843                         __cpu_name[cpu] = "TX3927";
 844                         c->tlbsize = 64;
 845                 } else {
 846                         switch (c->processor_id & PRID_REV_MASK) {
 847                         case PRID_REV_TX3912:
 848                                 c->cputype = CPU_TX3912;
 849                                 __cpu_name[cpu] = "TX3912";
 850                                 c->tlbsize = 32;
 851                                 break;
 852                         case PRID_REV_TX3922:
 853                                 c->cputype = CPU_TX3922;
 854                                 __cpu_name[cpu] = "TX3922";
 855                                 c->tlbsize = 64;
 856                                 break;
 857                         }
 858                 }
 859                 break;
 860         case PRID_IMP_R4700:
 861                 c->cputype = CPU_R4700;
 862                 __cpu_name[cpu] = "R4700";
 863                 set_isa(c, MIPS_CPU_ISA_III);
 864                 c->fpu_msk31 |= FPU_CSR_CONDX;
 865                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 866                              MIPS_CPU_LLSC;
 867                 c->tlbsize = 48;
 868                 break;
 869         case PRID_IMP_TX49:
 870                 c->cputype = CPU_TX49XX;
 871                 __cpu_name[cpu] = "R49XX";
 872                 set_isa(c, MIPS_CPU_ISA_III);
 873                 c->fpu_msk31 |= FPU_CSR_CONDX;
 874                 c->options = R4K_OPTS | MIPS_CPU_LLSC;
 875                 if (!(c->processor_id & 0x08))
 876                         c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
 877                 c->tlbsize = 48;
 878                 break;
 879         case PRID_IMP_R5000:
 880                 c->cputype = CPU_R5000;
 881                 __cpu_name[cpu] = "R5000";
 882                 set_isa(c, MIPS_CPU_ISA_IV);
 883                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 884                              MIPS_CPU_LLSC;
 885                 c->tlbsize = 48;
 886                 break;
 887         case PRID_IMP_R5432:
 888                 c->cputype = CPU_R5432;
 889                 __cpu_name[cpu] = "R5432";
 890                 set_isa(c, MIPS_CPU_ISA_IV);
 891                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 892                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 893                 c->tlbsize = 48;
 894                 break;
 895         case PRID_IMP_R5500:
 896                 c->cputype = CPU_R5500;
 897                 __cpu_name[cpu] = "R5500";
 898                 set_isa(c, MIPS_CPU_ISA_IV);
 899                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 900                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 901                 c->tlbsize = 48;
 902                 break;
 903         case PRID_IMP_NEVADA:
 904                 c->cputype = CPU_NEVADA;
 905                 __cpu_name[cpu] = "Nevada";
 906                 set_isa(c, MIPS_CPU_ISA_IV);
 907                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 908                              MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
 909                 c->tlbsize = 48;
 910                 break;
 911         case PRID_IMP_R6000:
 912                 c->cputype = CPU_R6000;
 913                 __cpu_name[cpu] = "R6000";
 914                 set_isa(c, MIPS_CPU_ISA_II);
 915                 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
 916                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 917                              MIPS_CPU_LLSC;
 918                 c->tlbsize = 32;
 919                 break;
 920         case PRID_IMP_R6000A:
 921                 c->cputype = CPU_R6000A;
 922                 __cpu_name[cpu] = "R6000A";
 923                 set_isa(c, MIPS_CPU_ISA_II);
 924                 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
 925                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 926                              MIPS_CPU_LLSC;
 927                 c->tlbsize = 32;
 928                 break;
 929         case PRID_IMP_RM7000:
 930                 c->cputype = CPU_RM7000;
 931                 __cpu_name[cpu] = "RM7000";
 932                 set_isa(c, MIPS_CPU_ISA_IV);
 933                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 934                              MIPS_CPU_LLSC;
 935                 /*
 936                  * Undocumented RM7000:  Bit 29 in the info register of
 937                  * the RM7000 v2.0 indicates if the TLB has 48 or 64
 938                  * entries.
 939                  *
 940                  * 29      1 =>    64 entry JTLB
 941                  *         0 =>    48 entry JTLB
 942                  */
 943                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 944                 break;
 945         case PRID_IMP_R8000:
 946                 c->cputype = CPU_R8000;
 947                 __cpu_name[cpu] = "RM8000";
 948                 set_isa(c, MIPS_CPU_ISA_IV);
 949                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 950                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 951                              MIPS_CPU_LLSC;
 952                 c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
 953                 break;
 954         case PRID_IMP_R10000:
 955                 c->cputype = CPU_R10000;
 956                 __cpu_name[cpu] = "R10000";
 957                 set_isa(c, MIPS_CPU_ISA_IV);
 958                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 959                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 960                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 961                              MIPS_CPU_LLSC;
 962                 c->tlbsize = 64;
 963                 break;
 964         case PRID_IMP_R12000:
 965                 c->cputype = CPU_R12000;
 966                 __cpu_name[cpu] = "R12000";
 967                 set_isa(c, MIPS_CPU_ISA_IV);
 968                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 969                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 970                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 971                              MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
 972                 c->tlbsize = 64;
 973                 break;
 974         case PRID_IMP_R14000:
 975                 if (((c->processor_id >> 4) & 0x0f) > 2) {
 976                         c->cputype = CPU_R16000;
 977                         __cpu_name[cpu] = "R16000";
 978                 } else {
 979                         c->cputype = CPU_R14000;
 980                         __cpu_name[cpu] = "R14000";
 981                 }
 982                 set_isa(c, MIPS_CPU_ISA_IV);
 983                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 984                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 985                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 986                              MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
 987                 c->tlbsize = 64;
 988                 break;
 989         case PRID_IMP_LOONGSON_64:  /* Loongson-2/3 */
 990                 switch (c->processor_id & PRID_REV_MASK) {
 991                 case PRID_REV_LOONGSON2E:
 992                         c->cputype = CPU_LOONGSON2;
 993                         __cpu_name[cpu] = "ICT Loongson-2";
 994                         set_elf_platform(cpu, "loongson2e");
 995                         set_isa(c, MIPS_CPU_ISA_III);
 996                         c->fpu_msk31 |= FPU_CSR_CONDX;
 997                         break;
 998                 case PRID_REV_LOONGSON2F:
 999                         c->cputype = CPU_LOONGSON2;
1000                         __cpu_name[cpu] = "ICT Loongson-2";
1001                         set_elf_platform(cpu, "loongson2f");
1002                         set_isa(c, MIPS_CPU_ISA_III);
1003                         c->fpu_msk31 |= FPU_CSR_CONDX;
1004                         break;
1005                 case PRID_REV_LOONGSON3A:
1006                         c->cputype = CPU_LOONGSON3;
1007                         __cpu_name[cpu] = "ICT Loongson-3";
1008                         set_elf_platform(cpu, "loongson3a");
1009                         set_isa(c, MIPS_CPU_ISA_M64R1);
1010                         break;
1011                 case PRID_REV_LOONGSON3B_R1:
1012                 case PRID_REV_LOONGSON3B_R2:
1013                         c->cputype = CPU_LOONGSON3;
1014                         __cpu_name[cpu] = "ICT Loongson-3";
1015                         set_elf_platform(cpu, "loongson3b");
1016                         set_isa(c, MIPS_CPU_ISA_M64R1);
1017                         break;
1018                 }
1019
1020                 c->options = R4K_OPTS |
1021                              MIPS_CPU_FPU | MIPS_CPU_LLSC |
1022                              MIPS_CPU_32FPR;
1023                 c->tlbsize = 64;
1024                 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1025                 break;
1026         case PRID_IMP_LOONGSON_32:  /* Loongson-1 */
1027                 decode_configs(c);
1028
1029                 c->cputype = CPU_LOONGSON1;
1030
1031                 switch (c->processor_id & PRID_REV_MASK) {
1032                 case PRID_REV_LOONGSON1B:
1033                         __cpu_name[cpu] = "Loongson 1B";
1034                         break;
1035                 }
1036
1037                 break;
1038         }
1039 }
1040
1041 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1042 {
1043         c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1044         switch (c->processor_id & PRID_IMP_MASK) {
1045         case PRID_IMP_QEMU_GENERIC:
1046                 c->writecombine = _CACHE_UNCACHED;
1047                 c->cputype = CPU_QEMU_GENERIC;
1048                 __cpu_name[cpu] = "MIPS GENERIC QEMU";
1049                 break;
1050         case PRID_IMP_4KC:
1051                 c->cputype = CPU_4KC;
1052                 c->writecombine = _CACHE_UNCACHED;
1053                 __cpu_name[cpu] = "MIPS 4Kc";
1054                 break;
1055         case PRID_IMP_4KEC:
1056         case PRID_IMP_4KECR2:
1057                 c->cputype = CPU_4KEC;
1058                 c->writecombine = _CACHE_UNCACHED;
1059                 __cpu_name[cpu] = "MIPS 4KEc";
1060                 break;
1061         case PRID_IMP_4KSC:
1062         case PRID_IMP_4KSD:
1063                 c->cputype = CPU_4KSC;
1064                 c->writecombine = _CACHE_UNCACHED;
1065                 __cpu_name[cpu] = "MIPS 4KSc";
1066                 break;
1067         case PRID_IMP_5KC:
1068                 c->cputype = CPU_5KC;
1069                 c->writecombine = _CACHE_UNCACHED;
1070                 __cpu_name[cpu] = "MIPS 5Kc";
1071                 break;
1072         case PRID_IMP_5KE:
1073                 c->cputype = CPU_5KE;
1074                 c->writecombine = _CACHE_UNCACHED;
1075                 __cpu_name[cpu] = "MIPS 5KE";
1076                 break;
1077         case PRID_IMP_20KC:
1078                 c->cputype = CPU_20KC;
1079                 c->writecombine = _CACHE_UNCACHED;
1080                 __cpu_name[cpu] = "MIPS 20Kc";
1081                 break;
1082         case PRID_IMP_24K:
1083                 c->cputype = CPU_24K;
1084                 c->writecombine = _CACHE_UNCACHED;
1085                 __cpu_name[cpu] = "MIPS 24Kc";
1086                 break;
1087         case PRID_IMP_24KE:
1088                 c->cputype = CPU_24K;
1089                 c->writecombine = _CACHE_UNCACHED;
1090                 __cpu_name[cpu] = "MIPS 24KEc";
1091                 break;
1092         case PRID_IMP_25KF:
1093                 c->cputype = CPU_25KF;
1094                 c->writecombine = _CACHE_UNCACHED;
1095                 __cpu_name[cpu] = "MIPS 25Kc";
1096                 break;
1097         case PRID_IMP_34K:
1098                 c->cputype = CPU_34K;
1099                 c->writecombine = _CACHE_UNCACHED;
1100                 __cpu_name[cpu] = "MIPS 34Kc";
1101                 break;
1102         case PRID_IMP_74K:
1103                 c->cputype = CPU_74K;
1104                 c->writecombine = _CACHE_UNCACHED;
1105                 __cpu_name[cpu] = "MIPS 74Kc";
1106                 break;
1107         case PRID_IMP_M14KC:
1108                 c->cputype = CPU_M14KC;
1109                 c->writecombine = _CACHE_UNCACHED;
1110                 __cpu_name[cpu] = "MIPS M14Kc";
1111                 break;
1112         case PRID_IMP_M14KEC:
1113                 c->cputype = CPU_M14KEC;
1114                 c->writecombine = _CACHE_UNCACHED;
1115                 __cpu_name[cpu] = "MIPS M14KEc";
1116                 break;
1117         case PRID_IMP_1004K:
1118                 c->cputype = CPU_1004K;
1119                 c->writecombine = _CACHE_UNCACHED;
1120                 __cpu_name[cpu] = "MIPS 1004Kc";
1121                 break;
1122         case PRID_IMP_1074K:
1123                 c->cputype = CPU_1074K;
1124                 c->writecombine = _CACHE_UNCACHED;
1125                 __cpu_name[cpu] = "MIPS 1074Kc";
1126                 break;
1127         case PRID_IMP_INTERAPTIV_UP:
1128                 c->cputype = CPU_INTERAPTIV;
1129                 __cpu_name[cpu] = "MIPS interAptiv";
1130                 break;
1131         case PRID_IMP_INTERAPTIV_MP:
1132                 c->cputype = CPU_INTERAPTIV;
1133                 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1134                 break;
1135         case PRID_IMP_PROAPTIV_UP:
1136                 c->cputype = CPU_PROAPTIV;
1137                 __cpu_name[cpu] = "MIPS proAptiv";
1138                 break;
1139         case PRID_IMP_PROAPTIV_MP:
1140                 c->cputype = CPU_PROAPTIV;
1141                 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1142                 break;
1143         case PRID_IMP_P5600:
1144                 c->cputype = CPU_P5600;
1145                 __cpu_name[cpu] = "MIPS P5600";
1146                 break;
1147         case PRID_IMP_I6400:
1148                 c->cputype = CPU_I6400;
1149                 __cpu_name[cpu] = "MIPS I6400";
1150                 break;
1151         case PRID_IMP_M5150:
1152                 c->cputype = CPU_M5150;
1153                 __cpu_name[cpu] = "MIPS M5150";
1154                 break;
1155         }
1156
1157         decode_configs(c);
1158
1159         spram_config();
1160 }
1161
1162 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1163 {
1164         decode_configs(c);
1165         switch (c->processor_id & PRID_IMP_MASK) {
1166         case PRID_IMP_AU1_REV1:
1167         case PRID_IMP_AU1_REV2:
1168                 c->cputype = CPU_ALCHEMY;
1169                 switch ((c->processor_id >> 24) & 0xff) {
1170                 case 0:
1171                         __cpu_name[cpu] = "Au1000";
1172                         break;
1173                 case 1:
1174                         __cpu_name[cpu] = "Au1500";
1175                         break;
1176                 case 2:
1177                         __cpu_name[cpu] = "Au1100";
1178                         break;
1179                 case 3:
1180                         __cpu_name[cpu] = "Au1550";
1181                         break;
1182                 case 4:
1183                         __cpu_name[cpu] = "Au1200";
1184                         if ((c->processor_id & PRID_REV_MASK) == 2)
1185                                 __cpu_name[cpu] = "Au1250";
1186                         break;
1187                 case 5:
1188                         __cpu_name[cpu] = "Au1210";
1189                         break;
1190                 default:
1191                         __cpu_name[cpu] = "Au1xxx";
1192                         break;
1193                 }
1194                 break;
1195         }
1196 }
1197
1198 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1199 {
1200         decode_configs(c);
1201
1202         c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1203         switch (c->processor_id & PRID_IMP_MASK) {
1204         case PRID_IMP_SB1:
1205                 c->cputype = CPU_SB1;
1206                 __cpu_name[cpu] = "SiByte SB1";
1207                 /* FPU in pass1 is known to have issues. */
1208                 if ((c->processor_id & PRID_REV_MASK) < 0x02)
1209                         c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1210                 break;
1211         case PRID_IMP_SB1A:
1212                 c->cputype = CPU_SB1A;
1213                 __cpu_name[cpu] = "SiByte SB1A";
1214                 break;
1215         }
1216 }
1217
1218 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1219 {
1220         decode_configs(c);
1221         switch (c->processor_id & PRID_IMP_MASK) {
1222         case PRID_IMP_SR71000:
1223                 c->cputype = CPU_SR71000;
1224                 __cpu_name[cpu] = "Sandcraft SR71000";
1225                 c->scache.ways = 8;
1226                 c->tlbsize = 64;
1227                 break;
1228         }
1229 }
1230
1231 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
1232 {
1233         decode_configs(c);
1234         switch (c->processor_id & PRID_IMP_MASK) {
1235         case PRID_IMP_PR4450:
1236                 c->cputype = CPU_PR4450;
1237                 __cpu_name[cpu] = "Philips PR4450";
1238                 set_isa(c, MIPS_CPU_ISA_M32R1);
1239                 break;
1240         }
1241 }
1242
1243 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1244 {
1245         decode_configs(c);
1246         switch (c->processor_id & PRID_IMP_MASK) {
1247         case PRID_IMP_BMIPS32_REV4:
1248         case PRID_IMP_BMIPS32_REV8:
1249                 c->cputype = CPU_BMIPS32;
1250                 __cpu_name[cpu] = "Broadcom BMIPS32";
1251                 set_elf_platform(cpu, "bmips32");
1252                 break;
1253         case PRID_IMP_BMIPS3300:
1254         case PRID_IMP_BMIPS3300_ALT:
1255         case PRID_IMP_BMIPS3300_BUG:
1256                 c->cputype = CPU_BMIPS3300;
1257                 __cpu_name[cpu] = "Broadcom BMIPS3300";
1258                 set_elf_platform(cpu, "bmips3300");
1259                 break;
1260         case PRID_IMP_BMIPS43XX: {
1261                 int rev = c->processor_id & PRID_REV_MASK;
1262
1263                 if (rev >= PRID_REV_BMIPS4380_LO &&
1264                                 rev <= PRID_REV_BMIPS4380_HI) {
1265                         c->cputype = CPU_BMIPS4380;
1266                         __cpu_name[cpu] = "Broadcom BMIPS4380";
1267                         set_elf_platform(cpu, "bmips4380");
1268                 } else {
1269                         c->cputype = CPU_BMIPS4350;
1270                         __cpu_name[cpu] = "Broadcom BMIPS4350";
1271                         set_elf_platform(cpu, "bmips4350");
1272                 }
1273                 break;
1274         }
1275         case PRID_IMP_BMIPS5000:
1276         case PRID_IMP_BMIPS5200:
1277                 c->cputype = CPU_BMIPS5000;
1278                 __cpu_name[cpu] = "Broadcom BMIPS5000";
1279                 set_elf_platform(cpu, "bmips5000");
1280                 c->options |= MIPS_CPU_ULRI;
1281                 break;
1282         }
1283 }
1284
1285 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1286 {
1287         decode_configs(c);
1288         switch (c->processor_id & PRID_IMP_MASK) {
1289         case PRID_IMP_CAVIUM_CN38XX:
1290         case PRID_IMP_CAVIUM_CN31XX:
1291         case PRID_IMP_CAVIUM_CN30XX:
1292                 c->cputype = CPU_CAVIUM_OCTEON;
1293                 __cpu_name[cpu] = "Cavium Octeon";
1294                 goto platform;
1295         case PRID_IMP_CAVIUM_CN58XX:
1296         case PRID_IMP_CAVIUM_CN56XX:
1297         case PRID_IMP_CAVIUM_CN50XX:
1298         case PRID_IMP_CAVIUM_CN52XX:
1299                 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1300                 __cpu_name[cpu] = "Cavium Octeon+";
1301 platform:
1302                 set_elf_platform(cpu, "octeon");
1303                 break;
1304         case PRID_IMP_CAVIUM_CN61XX:
1305         case PRID_IMP_CAVIUM_CN63XX:
1306         case PRID_IMP_CAVIUM_CN66XX:
1307         case PRID_IMP_CAVIUM_CN68XX:
1308         case PRID_IMP_CAVIUM_CNF71XX:
1309                 c->cputype = CPU_CAVIUM_OCTEON2;
1310                 __cpu_name[cpu] = "Cavium Octeon II";
1311                 set_elf_platform(cpu, "octeon2");
1312                 break;
1313         case PRID_IMP_CAVIUM_CN70XX:
1314         case PRID_IMP_CAVIUM_CN78XX:
1315                 c->cputype = CPU_CAVIUM_OCTEON3;
1316                 __cpu_name[cpu] = "Cavium Octeon III";
1317                 set_elf_platform(cpu, "octeon3");
1318                 break;
1319         default:
1320                 printk(KERN_INFO "Unknown Octeon chip!\n");
1321                 c->cputype = CPU_UNKNOWN;
1322                 break;
1323         }
1324 }
1325
1326 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1327 {
1328         decode_configs(c);
1329         /* JZRISC does not implement the CP0 counter. */
1330         c->options &= ~MIPS_CPU_COUNTER;
1331         BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
1332         switch (c->processor_id & PRID_IMP_MASK) {
1333         case PRID_IMP_JZRISC:
1334                 c->cputype = CPU_JZRISC;
1335                 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1336                 __cpu_name[cpu] = "Ingenic JZRISC";
1337                 break;
1338         default:
1339                 panic("Unknown Ingenic Processor ID!");
1340                 break;
1341         }
1342 }
1343
1344 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1345 {
1346         decode_configs(c);
1347
1348         if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
1349                 c->cputype = CPU_ALCHEMY;
1350                 __cpu_name[cpu] = "Au1300";
1351                 /* following stuff is not for Alchemy */
1352                 return;
1353         }
1354
1355         c->options = (MIPS_CPU_TLB       |
1356                         MIPS_CPU_4KEX    |
1357                         MIPS_CPU_COUNTER |
1358                         MIPS_CPU_DIVEC   |
1359                         MIPS_CPU_WATCH   |
1360                         MIPS_CPU_EJTAG   |
1361                         MIPS_CPU_LLSC);
1362
1363         switch (c->processor_id & PRID_IMP_MASK) {
1364         case PRID_IMP_NETLOGIC_XLP2XX:
1365         case PRID_IMP_NETLOGIC_XLP9XX:
1366         case PRID_IMP_NETLOGIC_XLP5XX:
1367                 c->cputype = CPU_XLP;
1368                 __cpu_name[cpu] = "Broadcom XLPII";
1369                 break;
1370
1371         case PRID_IMP_NETLOGIC_XLP8XX:
1372         case PRID_IMP_NETLOGIC_XLP3XX:
1373                 c->cputype = CPU_XLP;
1374                 __cpu_name[cpu] = "Netlogic XLP";
1375                 break;
1376
1377         case PRID_IMP_NETLOGIC_XLR732:
1378         case PRID_IMP_NETLOGIC_XLR716:
1379         case PRID_IMP_NETLOGIC_XLR532:
1380         case PRID_IMP_NETLOGIC_XLR308:
1381         case PRID_IMP_NETLOGIC_XLR532C:
1382         case PRID_IMP_NETLOGIC_XLR516C:
1383         case PRID_IMP_NETLOGIC_XLR508C:
1384         case PRID_IMP_NETLOGIC_XLR308C:
1385                 c->cputype = CPU_XLR;
1386                 __cpu_name[cpu] = "Netlogic XLR";
1387                 break;
1388
1389         case PRID_IMP_NETLOGIC_XLS608:
1390         case PRID_IMP_NETLOGIC_XLS408:
1391         case PRID_IMP_NETLOGIC_XLS404:
1392         case PRID_IMP_NETLOGIC_XLS208:
1393         case PRID_IMP_NETLOGIC_XLS204:
1394         case PRID_IMP_NETLOGIC_XLS108:
1395         case PRID_IMP_NETLOGIC_XLS104:
1396         case PRID_IMP_NETLOGIC_XLS616B:
1397         case PRID_IMP_NETLOGIC_XLS608B:
1398         case PRID_IMP_NETLOGIC_XLS416B:
1399         case PRID_IMP_NETLOGIC_XLS412B:
1400         case PRID_IMP_NETLOGIC_XLS408B:
1401         case PRID_IMP_NETLOGIC_XLS404B:
1402                 c->cputype = CPU_XLR;
1403                 __cpu_name[cpu] = "Netlogic XLS";
1404                 break;
1405
1406         default:
1407                 pr_info("Unknown Netlogic chip id [%02x]!\n",
1408                        c->processor_id);
1409                 c->cputype = CPU_XLR;
1410                 break;
1411         }
1412
1413         if (c->cputype == CPU_XLP) {
1414                 set_isa(c, MIPS_CPU_ISA_M64R2);
1415                 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1416                 /* This will be updated again after all threads are woken up */
1417                 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1418         } else {
1419                 set_isa(c, MIPS_CPU_ISA_M64R1);
1420                 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1421         }
1422         c->kscratch_mask = 0xf;
1423 }
1424
1425 #ifdef CONFIG_64BIT
1426 /* For use by uaccess.h */
1427 u64 __ua_limit;
1428 EXPORT_SYMBOL(__ua_limit);
1429 #endif
1430
1431 const char *__cpu_name[NR_CPUS];
1432 const char *__elf_platform;
1433
1434 void cpu_probe(void)
1435 {
1436         struct cpuinfo_mips *c = &current_cpu_data;
1437         unsigned int cpu = smp_processor_id();
1438
1439         c->processor_id = PRID_IMP_UNKNOWN;
1440         c->fpu_id       = FPIR_IMP_NONE;
1441         c->cputype      = CPU_UNKNOWN;
1442         c->writecombine = _CACHE_UNCACHED;
1443
1444         c->fpu_csr31    = FPU_CSR_RN;
1445         c->fpu_msk31    = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
1446
1447         c->processor_id = read_c0_prid();
1448         switch (c->processor_id & PRID_COMP_MASK) {
1449         case PRID_COMP_LEGACY:
1450                 cpu_probe_legacy(c, cpu);
1451                 break;
1452         case PRID_COMP_MIPS:
1453                 cpu_probe_mips(c, cpu);
1454                 break;
1455         case PRID_COMP_ALCHEMY:
1456                 cpu_probe_alchemy(c, cpu);
1457                 break;
1458         case PRID_COMP_SIBYTE:
1459                 cpu_probe_sibyte(c, cpu);
1460                 break;
1461         case PRID_COMP_BROADCOM:
1462                 cpu_probe_broadcom(c, cpu);
1463                 break;
1464         case PRID_COMP_SANDCRAFT:
1465                 cpu_probe_sandcraft(c, cpu);
1466                 break;
1467         case PRID_COMP_NXP:
1468                 cpu_probe_nxp(c, cpu);
1469                 break;
1470         case PRID_COMP_CAVIUM:
1471                 cpu_probe_cavium(c, cpu);
1472                 break;
1473         case PRID_COMP_INGENIC_D0:
1474         case PRID_COMP_INGENIC_D1:
1475         case PRID_COMP_INGENIC_E1:
1476                 cpu_probe_ingenic(c, cpu);
1477                 break;
1478         case PRID_COMP_NETLOGIC:
1479                 cpu_probe_netlogic(c, cpu);
1480                 break;
1481         }
1482
1483         BUG_ON(!__cpu_name[cpu]);
1484         BUG_ON(c->cputype == CPU_UNKNOWN);
1485
1486         /*
1487          * Platform code can force the cpu type to optimize code
1488          * generation. In that case be sure the cpu type is correctly
1489          * manually setup otherwise it could trigger some nasty bugs.
1490          */
1491         BUG_ON(current_cpu_type() != c->cputype);
1492
1493         if (mips_fpu_disabled)
1494                 c->options &= ~MIPS_CPU_FPU;
1495
1496         if (mips_dsp_disabled)
1497                 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
1498
1499         if (mips_htw_disabled) {
1500                 c->options &= ~MIPS_CPU_HTW;
1501                 write_c0_pwctl(read_c0_pwctl() &
1502                                ~(1 << MIPS_PWCTL_PWEN_SHIFT));
1503         }
1504
1505         if (c->options & MIPS_CPU_FPU)
1506                 cpu_set_fpu_opts(c);
1507         else
1508                 cpu_set_nofpu_opts(c);
1509
1510         if (cpu_has_bp_ghist)
1511                 write_c0_r10k_diag(read_c0_r10k_diag() |
1512                                    R10K_DIAG_E_GHIST);
1513
1514         if (cpu_has_mips_r2_r6) {
1515                 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1516                 /* R2 has Performance Counter Interrupt indicator */
1517                 c->options |= MIPS_CPU_PCI;
1518         }
1519         else
1520                 c->srsets = 1;
1521
1522         if (cpu_has_msa) {
1523                 c->msa_id = cpu_get_msa_id();
1524                 WARN(c->msa_id & MSA_IR_WRPF,
1525                      "Vector register partitioning unimplemented!");
1526         }
1527
1528         cpu_probe_vmbits(c);
1529
1530 #ifdef CONFIG_64BIT
1531         if (cpu == 0)
1532                 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1533 #endif
1534 }
1535
1536 void cpu_report(void)
1537 {
1538         struct cpuinfo_mips *c = &current_cpu_data;
1539
1540         pr_info("CPU%d revision is: %08x (%s)\n",
1541                 smp_processor_id(), c->processor_id, cpu_name_string());
1542         if (c->options & MIPS_CPU_FPU)
1543                 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1544         if (cpu_has_msa)
1545                 pr_info("MSA revision is: %08x\n", c->msa_id);
1546 }