2 * offset.c: Calculate pt_regs and task_struct offsets.
4 * Copyright (C) 1996 David S. Miller
5 * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002, 2003 Ralf Baechle
6 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8 * Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
9 * Copyright (C) 2000 MIPS Technologies, Inc.
11 #include <linux/compat.h>
12 #include <linux/types.h>
13 #include <linux/sched.h>
15 #include <linux/kbuild.h>
16 #include <linux/suspend.h>
17 #include <asm/ptrace.h>
18 #include <asm/processor.h>
19 #include <asm/smp-cps.h>
21 #include <linux/kvm_host.h>
23 void output_ptreg_defines(void)
25 COMMENT("MIPS pt_regs offsets.");
26 OFFSET(PT_R0, pt_regs, regs[0]);
27 OFFSET(PT_R1, pt_regs, regs[1]);
28 OFFSET(PT_R2, pt_regs, regs[2]);
29 OFFSET(PT_R3, pt_regs, regs[3]);
30 OFFSET(PT_R4, pt_regs, regs[4]);
31 OFFSET(PT_R5, pt_regs, regs[5]);
32 OFFSET(PT_R6, pt_regs, regs[6]);
33 OFFSET(PT_R7, pt_regs, regs[7]);
34 OFFSET(PT_R8, pt_regs, regs[8]);
35 OFFSET(PT_R9, pt_regs, regs[9]);
36 OFFSET(PT_R10, pt_regs, regs[10]);
37 OFFSET(PT_R11, pt_regs, regs[11]);
38 OFFSET(PT_R12, pt_regs, regs[12]);
39 OFFSET(PT_R13, pt_regs, regs[13]);
40 OFFSET(PT_R14, pt_regs, regs[14]);
41 OFFSET(PT_R15, pt_regs, regs[15]);
42 OFFSET(PT_R16, pt_regs, regs[16]);
43 OFFSET(PT_R17, pt_regs, regs[17]);
44 OFFSET(PT_R18, pt_regs, regs[18]);
45 OFFSET(PT_R19, pt_regs, regs[19]);
46 OFFSET(PT_R20, pt_regs, regs[20]);
47 OFFSET(PT_R21, pt_regs, regs[21]);
48 OFFSET(PT_R22, pt_regs, regs[22]);
49 OFFSET(PT_R23, pt_regs, regs[23]);
50 OFFSET(PT_R24, pt_regs, regs[24]);
51 OFFSET(PT_R25, pt_regs, regs[25]);
52 OFFSET(PT_R26, pt_regs, regs[26]);
53 OFFSET(PT_R27, pt_regs, regs[27]);
54 OFFSET(PT_R28, pt_regs, regs[28]);
55 OFFSET(PT_R29, pt_regs, regs[29]);
56 OFFSET(PT_R30, pt_regs, regs[30]);
57 OFFSET(PT_R31, pt_regs, regs[31]);
58 OFFSET(PT_LO, pt_regs, lo);
59 OFFSET(PT_HI, pt_regs, hi);
60 #ifdef CONFIG_CPU_HAS_SMARTMIPS
61 OFFSET(PT_ACX, pt_regs, acx);
63 OFFSET(PT_EPC, pt_regs, cp0_epc);
64 OFFSET(PT_BVADDR, pt_regs, cp0_badvaddr);
65 OFFSET(PT_STATUS, pt_regs, cp0_status);
66 OFFSET(PT_CAUSE, pt_regs, cp0_cause);
67 #ifdef CONFIG_CPU_CAVIUM_OCTEON
68 OFFSET(PT_MPL, pt_regs, mpl);
69 OFFSET(PT_MTP, pt_regs, mtp);
70 #endif /* CONFIG_CPU_CAVIUM_OCTEON */
71 DEFINE(PT_SIZE, sizeof(struct pt_regs));
75 void output_task_defines(void)
77 COMMENT("MIPS task_struct offsets.");
78 OFFSET(TASK_STATE, task_struct, state);
79 OFFSET(TASK_THREAD_INFO, task_struct, stack);
80 OFFSET(TASK_FLAGS, task_struct, flags);
81 OFFSET(TASK_MM, task_struct, mm);
82 OFFSET(TASK_PID, task_struct, pid);
83 #if defined(CONFIG_CC_STACKPROTECTOR)
84 OFFSET(TASK_STACK_CANARY, task_struct, stack_canary);
86 DEFINE(TASK_STRUCT_SIZE, sizeof(struct task_struct));
90 void output_thread_info_defines(void)
92 COMMENT("MIPS thread_info offsets.");
93 OFFSET(TI_TASK, thread_info, task);
94 OFFSET(TI_EXEC_DOMAIN, thread_info, exec_domain);
95 OFFSET(TI_FLAGS, thread_info, flags);
96 OFFSET(TI_TP_VALUE, thread_info, tp_value);
97 OFFSET(TI_CPU, thread_info, cpu);
98 OFFSET(TI_PRE_COUNT, thread_info, preempt_count);
99 OFFSET(TI_ADDR_LIMIT, thread_info, addr_limit);
100 OFFSET(TI_RESTART_BLOCK, thread_info, restart_block);
101 OFFSET(TI_REGS, thread_info, regs);
102 DEFINE(_THREAD_SIZE, THREAD_SIZE);
103 DEFINE(_THREAD_MASK, THREAD_MASK);
107 void output_thread_defines(void)
109 COMMENT("MIPS specific thread_struct offsets.");
110 OFFSET(THREAD_REG16, task_struct, thread.reg16);
111 OFFSET(THREAD_REG17, task_struct, thread.reg17);
112 OFFSET(THREAD_REG18, task_struct, thread.reg18);
113 OFFSET(THREAD_REG19, task_struct, thread.reg19);
114 OFFSET(THREAD_REG20, task_struct, thread.reg20);
115 OFFSET(THREAD_REG21, task_struct, thread.reg21);
116 OFFSET(THREAD_REG22, task_struct, thread.reg22);
117 OFFSET(THREAD_REG23, task_struct, thread.reg23);
118 OFFSET(THREAD_REG29, task_struct, thread.reg29);
119 OFFSET(THREAD_REG30, task_struct, thread.reg30);
120 OFFSET(THREAD_REG31, task_struct, thread.reg31);
121 OFFSET(THREAD_STATUS, task_struct,
123 OFFSET(THREAD_FPU, task_struct, thread.fpu);
125 OFFSET(THREAD_BVADDR, task_struct, \
126 thread.cp0_badvaddr);
127 OFFSET(THREAD_BUADDR, task_struct, \
128 thread.cp0_baduaddr);
129 OFFSET(THREAD_ECODE, task_struct, \
134 void output_thread_fpu_defines(void)
136 OFFSET(THREAD_FPR0, task_struct, thread.fpu.fpr[0]);
137 OFFSET(THREAD_FPR1, task_struct, thread.fpu.fpr[1]);
138 OFFSET(THREAD_FPR2, task_struct, thread.fpu.fpr[2]);
139 OFFSET(THREAD_FPR3, task_struct, thread.fpu.fpr[3]);
140 OFFSET(THREAD_FPR4, task_struct, thread.fpu.fpr[4]);
141 OFFSET(THREAD_FPR5, task_struct, thread.fpu.fpr[5]);
142 OFFSET(THREAD_FPR6, task_struct, thread.fpu.fpr[6]);
143 OFFSET(THREAD_FPR7, task_struct, thread.fpu.fpr[7]);
144 OFFSET(THREAD_FPR8, task_struct, thread.fpu.fpr[8]);
145 OFFSET(THREAD_FPR9, task_struct, thread.fpu.fpr[9]);
146 OFFSET(THREAD_FPR10, task_struct, thread.fpu.fpr[10]);
147 OFFSET(THREAD_FPR11, task_struct, thread.fpu.fpr[11]);
148 OFFSET(THREAD_FPR12, task_struct, thread.fpu.fpr[12]);
149 OFFSET(THREAD_FPR13, task_struct, thread.fpu.fpr[13]);
150 OFFSET(THREAD_FPR14, task_struct, thread.fpu.fpr[14]);
151 OFFSET(THREAD_FPR15, task_struct, thread.fpu.fpr[15]);
152 OFFSET(THREAD_FPR16, task_struct, thread.fpu.fpr[16]);
153 OFFSET(THREAD_FPR17, task_struct, thread.fpu.fpr[17]);
154 OFFSET(THREAD_FPR18, task_struct, thread.fpu.fpr[18]);
155 OFFSET(THREAD_FPR19, task_struct, thread.fpu.fpr[19]);
156 OFFSET(THREAD_FPR20, task_struct, thread.fpu.fpr[20]);
157 OFFSET(THREAD_FPR21, task_struct, thread.fpu.fpr[21]);
158 OFFSET(THREAD_FPR22, task_struct, thread.fpu.fpr[22]);
159 OFFSET(THREAD_FPR23, task_struct, thread.fpu.fpr[23]);
160 OFFSET(THREAD_FPR24, task_struct, thread.fpu.fpr[24]);
161 OFFSET(THREAD_FPR25, task_struct, thread.fpu.fpr[25]);
162 OFFSET(THREAD_FPR26, task_struct, thread.fpu.fpr[26]);
163 OFFSET(THREAD_FPR27, task_struct, thread.fpu.fpr[27]);
164 OFFSET(THREAD_FPR28, task_struct, thread.fpu.fpr[28]);
165 OFFSET(THREAD_FPR29, task_struct, thread.fpu.fpr[29]);
166 OFFSET(THREAD_FPR30, task_struct, thread.fpu.fpr[30]);
167 OFFSET(THREAD_FPR31, task_struct, thread.fpu.fpr[31]);
169 /* the least significant 64 bits of each FP register */
170 OFFSET(THREAD_FPR0_LS64, task_struct,
171 thread.fpu.fpr[0].val64[FPR_IDX(64, 0)]);
172 OFFSET(THREAD_FPR1_LS64, task_struct,
173 thread.fpu.fpr[1].val64[FPR_IDX(64, 0)]);
174 OFFSET(THREAD_FPR2_LS64, task_struct,
175 thread.fpu.fpr[2].val64[FPR_IDX(64, 0)]);
176 OFFSET(THREAD_FPR3_LS64, task_struct,
177 thread.fpu.fpr[3].val64[FPR_IDX(64, 0)]);
178 OFFSET(THREAD_FPR4_LS64, task_struct,
179 thread.fpu.fpr[4].val64[FPR_IDX(64, 0)]);
180 OFFSET(THREAD_FPR5_LS64, task_struct,
181 thread.fpu.fpr[5].val64[FPR_IDX(64, 0)]);
182 OFFSET(THREAD_FPR6_LS64, task_struct,
183 thread.fpu.fpr[6].val64[FPR_IDX(64, 0)]);
184 OFFSET(THREAD_FPR7_LS64, task_struct,
185 thread.fpu.fpr[7].val64[FPR_IDX(64, 0)]);
186 OFFSET(THREAD_FPR8_LS64, task_struct,
187 thread.fpu.fpr[8].val64[FPR_IDX(64, 0)]);
188 OFFSET(THREAD_FPR9_LS64, task_struct,
189 thread.fpu.fpr[9].val64[FPR_IDX(64, 0)]);
190 OFFSET(THREAD_FPR10_LS64, task_struct,
191 thread.fpu.fpr[10].val64[FPR_IDX(64, 0)]);
192 OFFSET(THREAD_FPR11_LS64, task_struct,
193 thread.fpu.fpr[11].val64[FPR_IDX(64, 0)]);
194 OFFSET(THREAD_FPR12_LS64, task_struct,
195 thread.fpu.fpr[12].val64[FPR_IDX(64, 0)]);
196 OFFSET(THREAD_FPR13_LS64, task_struct,
197 thread.fpu.fpr[13].val64[FPR_IDX(64, 0)]);
198 OFFSET(THREAD_FPR14_LS64, task_struct,
199 thread.fpu.fpr[14].val64[FPR_IDX(64, 0)]);
200 OFFSET(THREAD_FPR15_LS64, task_struct,
201 thread.fpu.fpr[15].val64[FPR_IDX(64, 0)]);
202 OFFSET(THREAD_FPR16_LS64, task_struct,
203 thread.fpu.fpr[16].val64[FPR_IDX(64, 0)]);
204 OFFSET(THREAD_FPR17_LS64, task_struct,
205 thread.fpu.fpr[17].val64[FPR_IDX(64, 0)]);
206 OFFSET(THREAD_FPR18_LS64, task_struct,
207 thread.fpu.fpr[18].val64[FPR_IDX(64, 0)]);
208 OFFSET(THREAD_FPR19_LS64, task_struct,
209 thread.fpu.fpr[19].val64[FPR_IDX(64, 0)]);
210 OFFSET(THREAD_FPR20_LS64, task_struct,
211 thread.fpu.fpr[20].val64[FPR_IDX(64, 0)]);
212 OFFSET(THREAD_FPR21_LS64, task_struct,
213 thread.fpu.fpr[21].val64[FPR_IDX(64, 0)]);
214 OFFSET(THREAD_FPR22_LS64, task_struct,
215 thread.fpu.fpr[22].val64[FPR_IDX(64, 0)]);
216 OFFSET(THREAD_FPR23_LS64, task_struct,
217 thread.fpu.fpr[23].val64[FPR_IDX(64, 0)]);
218 OFFSET(THREAD_FPR24_LS64, task_struct,
219 thread.fpu.fpr[24].val64[FPR_IDX(64, 0)]);
220 OFFSET(THREAD_FPR25_LS64, task_struct,
221 thread.fpu.fpr[25].val64[FPR_IDX(64, 0)]);
222 OFFSET(THREAD_FPR26_LS64, task_struct,
223 thread.fpu.fpr[26].val64[FPR_IDX(64, 0)]);
224 OFFSET(THREAD_FPR27_LS64, task_struct,
225 thread.fpu.fpr[27].val64[FPR_IDX(64, 0)]);
226 OFFSET(THREAD_FPR28_LS64, task_struct,
227 thread.fpu.fpr[28].val64[FPR_IDX(64, 0)]);
228 OFFSET(THREAD_FPR29_LS64, task_struct,
229 thread.fpu.fpr[29].val64[FPR_IDX(64, 0)]);
230 OFFSET(THREAD_FPR30_LS64, task_struct,
231 thread.fpu.fpr[30].val64[FPR_IDX(64, 0)]);
232 OFFSET(THREAD_FPR31_LS64, task_struct,
233 thread.fpu.fpr[31].val64[FPR_IDX(64, 0)]);
235 OFFSET(THREAD_FCR31, task_struct, thread.fpu.fcr31);
239 void output_mm_defines(void)
241 COMMENT("Size of struct page");
242 DEFINE(STRUCT_PAGE_SIZE, sizeof(struct page));
244 COMMENT("Linux mm_struct offsets.");
245 OFFSET(MM_USERS, mm_struct, mm_users);
246 OFFSET(MM_PGD, mm_struct, pgd);
247 OFFSET(MM_CONTEXT, mm_struct, context);
249 DEFINE(_PGD_T_SIZE, sizeof(pgd_t));
250 DEFINE(_PMD_T_SIZE, sizeof(pmd_t));
251 DEFINE(_PTE_T_SIZE, sizeof(pte_t));
253 DEFINE(_PGD_T_LOG2, PGD_T_LOG2);
254 #ifndef __PAGETABLE_PMD_FOLDED
255 DEFINE(_PMD_T_LOG2, PMD_T_LOG2);
257 DEFINE(_PTE_T_LOG2, PTE_T_LOG2);
259 DEFINE(_PGD_ORDER, PGD_ORDER);
260 #ifndef __PAGETABLE_PMD_FOLDED
261 DEFINE(_PMD_ORDER, PMD_ORDER);
263 DEFINE(_PTE_ORDER, PTE_ORDER);
265 DEFINE(_PMD_SHIFT, PMD_SHIFT);
266 DEFINE(_PGDIR_SHIFT, PGDIR_SHIFT);
268 DEFINE(_PTRS_PER_PGD, PTRS_PER_PGD);
269 DEFINE(_PTRS_PER_PMD, PTRS_PER_PMD);
270 DEFINE(_PTRS_PER_PTE, PTRS_PER_PTE);
272 DEFINE(_PAGE_SHIFT, PAGE_SHIFT);
273 DEFINE(_PAGE_SIZE, PAGE_SIZE);
278 void output_sc_defines(void)
280 COMMENT("Linux sigcontext offsets.");
281 OFFSET(SC_REGS, sigcontext, sc_regs);
282 OFFSET(SC_FPREGS, sigcontext, sc_fpregs);
283 OFFSET(SC_ACX, sigcontext, sc_acx);
284 OFFSET(SC_MDHI, sigcontext, sc_mdhi);
285 OFFSET(SC_MDLO, sigcontext, sc_mdlo);
286 OFFSET(SC_PC, sigcontext, sc_pc);
287 OFFSET(SC_FPC_CSR, sigcontext, sc_fpc_csr);
288 OFFSET(SC_FPC_EIR, sigcontext, sc_fpc_eir);
289 OFFSET(SC_HI1, sigcontext, sc_hi1);
290 OFFSET(SC_LO1, sigcontext, sc_lo1);
291 OFFSET(SC_HI2, sigcontext, sc_hi2);
292 OFFSET(SC_LO2, sigcontext, sc_lo2);
293 OFFSET(SC_HI3, sigcontext, sc_hi3);
294 OFFSET(SC_LO3, sigcontext, sc_lo3);
295 OFFSET(SC_MSAREGS, sigcontext, sc_msaregs);
301 void output_sc_defines(void)
303 COMMENT("Linux sigcontext offsets.");
304 OFFSET(SC_REGS, sigcontext, sc_regs);
305 OFFSET(SC_FPREGS, sigcontext, sc_fpregs);
306 OFFSET(SC_MDHI, sigcontext, sc_mdhi);
307 OFFSET(SC_MDLO, sigcontext, sc_mdlo);
308 OFFSET(SC_PC, sigcontext, sc_pc);
309 OFFSET(SC_FPC_CSR, sigcontext, sc_fpc_csr);
310 OFFSET(SC_MSAREGS, sigcontext, sc_msaregs);
315 #ifdef CONFIG_MIPS32_COMPAT
316 void output_sc32_defines(void)
318 COMMENT("Linux 32-bit sigcontext offsets.");
319 OFFSET(SC32_FPREGS, sigcontext32, sc_fpregs);
320 OFFSET(SC32_FPC_CSR, sigcontext32, sc_fpc_csr);
321 OFFSET(SC32_FPC_EIR, sigcontext32, sc_fpc_eir);
322 OFFSET(SC32_MSAREGS, sigcontext32, sc_msaregs);
327 void output_signal_defined(void)
329 COMMENT("Linux signal numbers.");
330 DEFINE(_SIGHUP, SIGHUP);
331 DEFINE(_SIGINT, SIGINT);
332 DEFINE(_SIGQUIT, SIGQUIT);
333 DEFINE(_SIGILL, SIGILL);
334 DEFINE(_SIGTRAP, SIGTRAP);
335 DEFINE(_SIGIOT, SIGIOT);
336 DEFINE(_SIGABRT, SIGABRT);
337 DEFINE(_SIGEMT, SIGEMT);
338 DEFINE(_SIGFPE, SIGFPE);
339 DEFINE(_SIGKILL, SIGKILL);
340 DEFINE(_SIGBUS, SIGBUS);
341 DEFINE(_SIGSEGV, SIGSEGV);
342 DEFINE(_SIGSYS, SIGSYS);
343 DEFINE(_SIGPIPE, SIGPIPE);
344 DEFINE(_SIGALRM, SIGALRM);
345 DEFINE(_SIGTERM, SIGTERM);
346 DEFINE(_SIGUSR1, SIGUSR1);
347 DEFINE(_SIGUSR2, SIGUSR2);
348 DEFINE(_SIGCHLD, SIGCHLD);
349 DEFINE(_SIGPWR, SIGPWR);
350 DEFINE(_SIGWINCH, SIGWINCH);
351 DEFINE(_SIGURG, SIGURG);
352 DEFINE(_SIGIO, SIGIO);
353 DEFINE(_SIGSTOP, SIGSTOP);
354 DEFINE(_SIGTSTP, SIGTSTP);
355 DEFINE(_SIGCONT, SIGCONT);
356 DEFINE(_SIGTTIN, SIGTTIN);
357 DEFINE(_SIGTTOU, SIGTTOU);
358 DEFINE(_SIGVTALRM, SIGVTALRM);
359 DEFINE(_SIGPROF, SIGPROF);
360 DEFINE(_SIGXCPU, SIGXCPU);
361 DEFINE(_SIGXFSZ, SIGXFSZ);
365 #ifdef CONFIG_CPU_CAVIUM_OCTEON
366 void output_octeon_cop2_state_defines(void)
368 COMMENT("Octeon specific octeon_cop2_state offsets.");
369 OFFSET(OCTEON_CP2_CRC_IV, octeon_cop2_state, cop2_crc_iv);
370 OFFSET(OCTEON_CP2_CRC_LENGTH, octeon_cop2_state, cop2_crc_length);
371 OFFSET(OCTEON_CP2_CRC_POLY, octeon_cop2_state, cop2_crc_poly);
372 OFFSET(OCTEON_CP2_LLM_DAT, octeon_cop2_state, cop2_llm_dat);
373 OFFSET(OCTEON_CP2_3DES_IV, octeon_cop2_state, cop2_3des_iv);
374 OFFSET(OCTEON_CP2_3DES_KEY, octeon_cop2_state, cop2_3des_key);
375 OFFSET(OCTEON_CP2_3DES_RESULT, octeon_cop2_state, cop2_3des_result);
376 OFFSET(OCTEON_CP2_AES_INP0, octeon_cop2_state, cop2_aes_inp0);
377 OFFSET(OCTEON_CP2_AES_IV, octeon_cop2_state, cop2_aes_iv);
378 OFFSET(OCTEON_CP2_AES_KEY, octeon_cop2_state, cop2_aes_key);
379 OFFSET(OCTEON_CP2_AES_KEYLEN, octeon_cop2_state, cop2_aes_keylen);
380 OFFSET(OCTEON_CP2_AES_RESULT, octeon_cop2_state, cop2_aes_result);
381 OFFSET(OCTEON_CP2_GFM_MULT, octeon_cop2_state, cop2_gfm_mult);
382 OFFSET(OCTEON_CP2_GFM_POLY, octeon_cop2_state, cop2_gfm_poly);
383 OFFSET(OCTEON_CP2_GFM_RESULT, octeon_cop2_state, cop2_gfm_result);
384 OFFSET(OCTEON_CP2_HSH_DATW, octeon_cop2_state, cop2_hsh_datw);
385 OFFSET(OCTEON_CP2_HSH_IVW, octeon_cop2_state, cop2_hsh_ivw);
386 OFFSET(THREAD_CP2, task_struct, thread.cp2);
387 OFFSET(THREAD_CVMSEG, task_struct, thread.cvmseg.cvmseg);
392 #ifdef CONFIG_HIBERNATION
393 void output_pbe_defines(void)
395 COMMENT(" Linux struct pbe offsets. ");
396 OFFSET(PBE_ADDRESS, pbe, address);
397 OFFSET(PBE_ORIG_ADDRESS, pbe, orig_address);
398 OFFSET(PBE_NEXT, pbe, next);
399 DEFINE(PBE_SIZE, sizeof(struct pbe));
404 void output_kvm_defines(void)
406 COMMENT(" KVM/MIPS Specfic offsets. ");
407 DEFINE(VCPU_ARCH_SIZE, sizeof(struct kvm_vcpu_arch));
408 OFFSET(VCPU_RUN, kvm_vcpu, run);
409 OFFSET(VCPU_HOST_ARCH, kvm_vcpu, arch);
411 OFFSET(VCPU_HOST_EBASE, kvm_vcpu_arch, host_ebase);
412 OFFSET(VCPU_GUEST_EBASE, kvm_vcpu_arch, guest_ebase);
414 OFFSET(VCPU_HOST_STACK, kvm_vcpu_arch, host_stack);
415 OFFSET(VCPU_HOST_GP, kvm_vcpu_arch, host_gp);
417 OFFSET(VCPU_HOST_CP0_BADVADDR, kvm_vcpu_arch, host_cp0_badvaddr);
418 OFFSET(VCPU_HOST_CP0_CAUSE, kvm_vcpu_arch, host_cp0_cause);
419 OFFSET(VCPU_HOST_EPC, kvm_vcpu_arch, host_cp0_epc);
420 OFFSET(VCPU_HOST_ENTRYHI, kvm_vcpu_arch, host_cp0_entryhi);
422 OFFSET(VCPU_GUEST_INST, kvm_vcpu_arch, guest_inst);
424 OFFSET(VCPU_R0, kvm_vcpu_arch, gprs[0]);
425 OFFSET(VCPU_R1, kvm_vcpu_arch, gprs[1]);
426 OFFSET(VCPU_R2, kvm_vcpu_arch, gprs[2]);
427 OFFSET(VCPU_R3, kvm_vcpu_arch, gprs[3]);
428 OFFSET(VCPU_R4, kvm_vcpu_arch, gprs[4]);
429 OFFSET(VCPU_R5, kvm_vcpu_arch, gprs[5]);
430 OFFSET(VCPU_R6, kvm_vcpu_arch, gprs[6]);
431 OFFSET(VCPU_R7, kvm_vcpu_arch, gprs[7]);
432 OFFSET(VCPU_R8, kvm_vcpu_arch, gprs[8]);
433 OFFSET(VCPU_R9, kvm_vcpu_arch, gprs[9]);
434 OFFSET(VCPU_R10, kvm_vcpu_arch, gprs[10]);
435 OFFSET(VCPU_R11, kvm_vcpu_arch, gprs[11]);
436 OFFSET(VCPU_R12, kvm_vcpu_arch, gprs[12]);
437 OFFSET(VCPU_R13, kvm_vcpu_arch, gprs[13]);
438 OFFSET(VCPU_R14, kvm_vcpu_arch, gprs[14]);
439 OFFSET(VCPU_R15, kvm_vcpu_arch, gprs[15]);
440 OFFSET(VCPU_R16, kvm_vcpu_arch, gprs[16]);
441 OFFSET(VCPU_R17, kvm_vcpu_arch, gprs[17]);
442 OFFSET(VCPU_R18, kvm_vcpu_arch, gprs[18]);
443 OFFSET(VCPU_R19, kvm_vcpu_arch, gprs[19]);
444 OFFSET(VCPU_R20, kvm_vcpu_arch, gprs[20]);
445 OFFSET(VCPU_R21, kvm_vcpu_arch, gprs[21]);
446 OFFSET(VCPU_R22, kvm_vcpu_arch, gprs[22]);
447 OFFSET(VCPU_R23, kvm_vcpu_arch, gprs[23]);
448 OFFSET(VCPU_R24, kvm_vcpu_arch, gprs[24]);
449 OFFSET(VCPU_R25, kvm_vcpu_arch, gprs[25]);
450 OFFSET(VCPU_R26, kvm_vcpu_arch, gprs[26]);
451 OFFSET(VCPU_R27, kvm_vcpu_arch, gprs[27]);
452 OFFSET(VCPU_R28, kvm_vcpu_arch, gprs[28]);
453 OFFSET(VCPU_R29, kvm_vcpu_arch, gprs[29]);
454 OFFSET(VCPU_R30, kvm_vcpu_arch, gprs[30]);
455 OFFSET(VCPU_R31, kvm_vcpu_arch, gprs[31]);
456 OFFSET(VCPU_LO, kvm_vcpu_arch, lo);
457 OFFSET(VCPU_HI, kvm_vcpu_arch, hi);
458 OFFSET(VCPU_PC, kvm_vcpu_arch, pc);
459 OFFSET(VCPU_COP0, kvm_vcpu_arch, cop0);
460 OFFSET(VCPU_GUEST_KERNEL_ASID, kvm_vcpu_arch, guest_kernel_asid);
461 OFFSET(VCPU_GUEST_USER_ASID, kvm_vcpu_arch, guest_user_asid);
463 OFFSET(COP0_TLB_HI, mips_coproc, reg[MIPS_CP0_TLB_HI][0]);
464 OFFSET(COP0_STATUS, mips_coproc, reg[MIPS_CP0_STATUS][0]);
468 #ifdef CONFIG_MIPS_CPS
469 void output_cps_defines(void)
471 COMMENT(" MIPS CPS offsets. ");
472 OFFSET(BOOTCFG_CORE, boot_config, core);
473 OFFSET(BOOTCFG_VPE, boot_config, vpe);
474 OFFSET(BOOTCFG_PC, boot_config, pc);
475 OFFSET(BOOTCFG_SP, boot_config, sp);
476 OFFSET(BOOTCFG_GP, boot_config, gp);