2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
7 * Copyright (C) 2000 Silicon Graphics, Inc.
8 * Modified for further R[236]000 support by Paul M. Antoine, 1996.
9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
10 * Copyright (C) 2000, 07 MIPS Technologies, Inc.
11 * Copyright (C) 2003, 2004 Maciej W. Rozycki
13 #ifndef _ASM_MIPSREGS_H
14 #define _ASM_MIPSREGS_H
16 #include <linux/linkage.h>
17 #include <linux/types.h>
18 #include <asm/hazards.h>
22 * The following macros are especially useful for __asm__
29 #define STR(x) __STR(x)
38 #define _ULCAST_ (unsigned long)
42 * Coprocessor 0 register names
46 #define CP0_ENTRYLO0 $2
47 #define CP0_ENTRYLO1 $3
49 #define CP0_CONTEXT $4
50 #define CP0_PAGEMASK $5
53 #define CP0_HWRENA $7, 0
54 #define CP0_BADVADDR $8
55 #define CP0_BADINSTR $8, 1
57 #define CP0_ENTRYHI $10
58 #define CP0_COMPARE $11
59 #define CP0_STATUS $12
63 #define CP0_EBASE $15, 1
64 #define CP0_CMGCRBASE $15, 3
65 #define CP0_CONFIG $16
66 #define CP0_CONFIG3 $16, 3
67 #define CP0_CONFIG5 $16, 5
68 #define CP0_LLADDR $17
69 #define CP0_WATCHLO $18
70 #define CP0_WATCHHI $19
71 #define CP0_XCONTEXT $20
72 #define CP0_FRAMEMASK $21
73 #define CP0_DIAGNOSTIC $22
76 #define CP0_PERFORMANCE $25
78 #define CP0_CACHEERR $27
81 #define CP0_ERROREPC $30
82 #define CP0_DESAVE $31
85 * R4640/R4650 cp0 register names. These registers are listed
86 * here only for completeness; without MMU these CPUs are not useable
87 * by Linux. A future ELKS port might take make Linux run on them
95 #define CP0_IWATCH $18
96 #define CP0_DWATCH $19
99 * Coprocessor 0 Set 1 register names
101 #define CP0_S1_DERRADDR0 $26
102 #define CP0_S1_DERRADDR1 $27
103 #define CP0_S1_INTCONTROL $20
106 * Coprocessor 0 Set 2 register names
108 #define CP0_S2_SRSCTL $12 /* MIPSR2 */
111 * Coprocessor 0 Set 3 register names
113 #define CP0_S3_SRSMAP $12 /* MIPSR2 */
118 #define CP0_TX39_CACHE $7
121 /* Generic EntryLo bit definitions */
122 #define ENTRYLO_G (_ULCAST_(1) << 0)
123 #define ENTRYLO_V (_ULCAST_(1) << 1)
124 #define ENTRYLO_D (_ULCAST_(1) << 2)
125 #define ENTRYLO_C_SHIFT 3
126 #define ENTRYLO_C (_ULCAST_(7) << ENTRYLO_C_SHIFT)
128 /* R3000 EntryLo bit definitions */
129 #define R3K_ENTRYLO_G (_ULCAST_(1) << 8)
130 #define R3K_ENTRYLO_V (_ULCAST_(1) << 9)
131 #define R3K_ENTRYLO_D (_ULCAST_(1) << 10)
132 #define R3K_ENTRYLO_N (_ULCAST_(1) << 11)
134 /* MIPS32/64 EntryLo bit definitions */
135 #define MIPS_ENTRYLO_PFN_SHIFT 6
136 #define MIPS_ENTRYLO_XI (_ULCAST_(1) << (BITS_PER_LONG - 2))
137 #define MIPS_ENTRYLO_RI (_ULCAST_(1) << (BITS_PER_LONG - 1))
140 * Values for PageMask register
142 #ifdef CONFIG_CPU_VR41XX
144 /* Why doesn't stupidity hurt ... */
146 #define PM_1K 0x00000000
147 #define PM_4K 0x00001800
148 #define PM_16K 0x00007800
149 #define PM_64K 0x0001f800
150 #define PM_256K 0x0007f800
154 #define PM_4K 0x00000000
155 #define PM_8K 0x00002000
156 #define PM_16K 0x00006000
157 #define PM_32K 0x0000e000
158 #define PM_64K 0x0001e000
159 #define PM_128K 0x0003e000
160 #define PM_256K 0x0007e000
161 #define PM_512K 0x000fe000
162 #define PM_1M 0x001fe000
163 #define PM_2M 0x003fe000
164 #define PM_4M 0x007fe000
165 #define PM_8M 0x00ffe000
166 #define PM_16M 0x01ffe000
167 #define PM_32M 0x03ffe000
168 #define PM_64M 0x07ffe000
169 #define PM_256M 0x1fffe000
170 #define PM_1G 0x7fffe000
175 * Default page size for a given kernel configuration
177 #ifdef CONFIG_PAGE_SIZE_4KB
178 #define PM_DEFAULT_MASK PM_4K
179 #elif defined(CONFIG_PAGE_SIZE_8KB)
180 #define PM_DEFAULT_MASK PM_8K
181 #elif defined(CONFIG_PAGE_SIZE_16KB)
182 #define PM_DEFAULT_MASK PM_16K
183 #elif defined(CONFIG_PAGE_SIZE_32KB)
184 #define PM_DEFAULT_MASK PM_32K
185 #elif defined(CONFIG_PAGE_SIZE_64KB)
186 #define PM_DEFAULT_MASK PM_64K
188 #error Bad page size configuration!
192 * Default huge tlb size for a given kernel configuration
194 #ifdef CONFIG_PAGE_SIZE_4KB
195 #define PM_HUGE_MASK PM_1M
196 #elif defined(CONFIG_PAGE_SIZE_8KB)
197 #define PM_HUGE_MASK PM_4M
198 #elif defined(CONFIG_PAGE_SIZE_16KB)
199 #define PM_HUGE_MASK PM_16M
200 #elif defined(CONFIG_PAGE_SIZE_32KB)
201 #define PM_HUGE_MASK PM_64M
202 #elif defined(CONFIG_PAGE_SIZE_64KB)
203 #define PM_HUGE_MASK PM_256M
204 #elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
205 #error Bad page size configuration for hugetlbfs!
209 * Values used for computation of new tlb entries
224 #define PG_RIE (_ULCAST_(1) << 31)
225 #define PG_XIE (_ULCAST_(1) << 30)
226 #define PG_ELPA (_ULCAST_(1) << 29)
227 #define PG_ESP (_ULCAST_(1) << 28)
228 #define PG_IEC (_ULCAST_(1) << 27)
230 /* MIPS32/64 EntryHI bit definitions */
231 #define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10)
234 * R4x00 interrupt enable / cause bits
236 #define IE_SW0 (_ULCAST_(1) << 8)
237 #define IE_SW1 (_ULCAST_(1) << 9)
238 #define IE_IRQ0 (_ULCAST_(1) << 10)
239 #define IE_IRQ1 (_ULCAST_(1) << 11)
240 #define IE_IRQ2 (_ULCAST_(1) << 12)
241 #define IE_IRQ3 (_ULCAST_(1) << 13)
242 #define IE_IRQ4 (_ULCAST_(1) << 14)
243 #define IE_IRQ5 (_ULCAST_(1) << 15)
246 * R4x00 interrupt cause bits
248 #define C_SW0 (_ULCAST_(1) << 8)
249 #define C_SW1 (_ULCAST_(1) << 9)
250 #define C_IRQ0 (_ULCAST_(1) << 10)
251 #define C_IRQ1 (_ULCAST_(1) << 11)
252 #define C_IRQ2 (_ULCAST_(1) << 12)
253 #define C_IRQ3 (_ULCAST_(1) << 13)
254 #define C_IRQ4 (_ULCAST_(1) << 14)
255 #define C_IRQ5 (_ULCAST_(1) << 15)
258 * Bitfields in the R4xx0 cp0 status register
260 #define ST0_IE 0x00000001
261 #define ST0_EXL 0x00000002
262 #define ST0_ERL 0x00000004
263 #define ST0_KSU 0x00000018
264 # define KSU_USER 0x00000010
265 # define KSU_SUPERVISOR 0x00000008
266 # define KSU_KERNEL 0x00000000
267 #define ST0_UX 0x00000020
268 #define ST0_SX 0x00000040
269 #define ST0_KX 0x00000080
270 #define ST0_DE 0x00010000
271 #define ST0_CE 0x00020000
274 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
275 * cacheops in userspace. This bit exists only on RM7000 and RM9000
278 #define ST0_CO 0x08000000
281 * Bitfields in the R[23]000 cp0 status register.
283 #define ST0_IEC 0x00000001
284 #define ST0_KUC 0x00000002
285 #define ST0_IEP 0x00000004
286 #define ST0_KUP 0x00000008
287 #define ST0_IEO 0x00000010
288 #define ST0_KUO 0x00000020
289 /* bits 6 & 7 are reserved on R[23]000 */
290 #define ST0_ISC 0x00010000
291 #define ST0_SWC 0x00020000
292 #define ST0_CM 0x00080000
295 * Bits specific to the R4640/R4650
297 #define ST0_UM (_ULCAST_(1) << 4)
298 #define ST0_IL (_ULCAST_(1) << 23)
299 #define ST0_DL (_ULCAST_(1) << 24)
302 * Enable the MIPS MDMX and DSP ASEs
304 #define ST0_MX 0x01000000
307 * Status register bits available in all MIPS CPUs.
309 #define ST0_IM 0x0000ff00
310 #define STATUSB_IP0 8
311 #define STATUSF_IP0 (_ULCAST_(1) << 8)
312 #define STATUSB_IP1 9
313 #define STATUSF_IP1 (_ULCAST_(1) << 9)
314 #define STATUSB_IP2 10
315 #define STATUSF_IP2 (_ULCAST_(1) << 10)
316 #define STATUSB_IP3 11
317 #define STATUSF_IP3 (_ULCAST_(1) << 11)
318 #define STATUSB_IP4 12
319 #define STATUSF_IP4 (_ULCAST_(1) << 12)
320 #define STATUSB_IP5 13
321 #define STATUSF_IP5 (_ULCAST_(1) << 13)
322 #define STATUSB_IP6 14
323 #define STATUSF_IP6 (_ULCAST_(1) << 14)
324 #define STATUSB_IP7 15
325 #define STATUSF_IP7 (_ULCAST_(1) << 15)
326 #define STATUSB_IP8 0
327 #define STATUSF_IP8 (_ULCAST_(1) << 0)
328 #define STATUSB_IP9 1
329 #define STATUSF_IP9 (_ULCAST_(1) << 1)
330 #define STATUSB_IP10 2
331 #define STATUSF_IP10 (_ULCAST_(1) << 2)
332 #define STATUSB_IP11 3
333 #define STATUSF_IP11 (_ULCAST_(1) << 3)
334 #define STATUSB_IP12 4
335 #define STATUSF_IP12 (_ULCAST_(1) << 4)
336 #define STATUSB_IP13 5
337 #define STATUSF_IP13 (_ULCAST_(1) << 5)
338 #define STATUSB_IP14 6
339 #define STATUSF_IP14 (_ULCAST_(1) << 6)
340 #define STATUSB_IP15 7
341 #define STATUSF_IP15 (_ULCAST_(1) << 7)
342 #define ST0_CH 0x00040000
343 #define ST0_NMI 0x00080000
344 #define ST0_SR 0x00100000
345 #define ST0_TS 0x00200000
346 #define ST0_BEV 0x00400000
347 #define ST0_RE 0x02000000
348 #define ST0_FR 0x04000000
349 #define ST0_CU 0xf0000000
350 #define ST0_CU0 0x10000000
351 #define ST0_CU1 0x20000000
352 #define ST0_CU2 0x40000000
353 #define ST0_CU3 0x80000000
354 #define ST0_XX 0x80000000 /* MIPS IV naming */
357 * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
359 #define INTCTLB_IPFDC 23
360 #define INTCTLF_IPFDC (_ULCAST_(7) << INTCTLB_IPFDC)
361 #define INTCTLB_IPPCI 26
362 #define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI)
363 #define INTCTLB_IPTI 29
364 #define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI)
367 * Bitfields and bit numbers in the coprocessor 0 cause register.
369 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
371 #define CAUSEB_EXCCODE 2
372 #define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
374 #define CAUSEF_IP (_ULCAST_(255) << 8)
376 #define CAUSEF_IP0 (_ULCAST_(1) << 8)
378 #define CAUSEF_IP1 (_ULCAST_(1) << 9)
379 #define CAUSEB_IP2 10
380 #define CAUSEF_IP2 (_ULCAST_(1) << 10)
381 #define CAUSEB_IP3 11
382 #define CAUSEF_IP3 (_ULCAST_(1) << 11)
383 #define CAUSEB_IP4 12
384 #define CAUSEF_IP4 (_ULCAST_(1) << 12)
385 #define CAUSEB_IP5 13
386 #define CAUSEF_IP5 (_ULCAST_(1) << 13)
387 #define CAUSEB_IP6 14
388 #define CAUSEF_IP6 (_ULCAST_(1) << 14)
389 #define CAUSEB_IP7 15
390 #define CAUSEF_IP7 (_ULCAST_(1) << 15)
391 #define CAUSEB_FDCI 21
392 #define CAUSEF_FDCI (_ULCAST_(1) << 21)
394 #define CAUSEF_IV (_ULCAST_(1) << 23)
395 #define CAUSEB_PCI 26
396 #define CAUSEF_PCI (_ULCAST_(1) << 26)
398 #define CAUSEF_DC (_ULCAST_(1) << 27)
400 #define CAUSEF_CE (_ULCAST_(3) << 28)
402 #define CAUSEF_TI (_ULCAST_(1) << 30)
404 #define CAUSEF_BD (_ULCAST_(1) << 31)
407 * Cause.ExcCode trap codes.
409 #define EXCCODE_INT 0 /* Interrupt pending */
410 #define EXCCODE_MOD 1 /* TLB modified fault */
411 #define EXCCODE_TLBL 2 /* TLB miss on load or ifetch */
412 #define EXCCODE_TLBS 3 /* TLB miss on a store */
413 #define EXCCODE_ADEL 4 /* Address error on a load or ifetch */
414 #define EXCCODE_ADES 5 /* Address error on a store */
415 #define EXCCODE_IBE 6 /* Bus error on an ifetch */
416 #define EXCCODE_DBE 7 /* Bus error on a load or store */
417 #define EXCCODE_SYS 8 /* System call */
418 #define EXCCODE_BP 9 /* Breakpoint */
419 #define EXCCODE_RI 10 /* Reserved instruction exception */
420 #define EXCCODE_CPU 11 /* Coprocessor unusable */
421 #define EXCCODE_OV 12 /* Arithmetic overflow */
422 #define EXCCODE_TR 13 /* Trap instruction */
423 #define EXCCODE_VCEI 14 /* Virtual coherency exception */
424 #define EXCCODE_MSAFPE 14 /* MSA floating point exception */
425 #define EXCCODE_FPE 15 /* Floating point exception */
426 #define EXCCODE_MSADIS 21 /* MSA disabled exception */
427 #define EXCCODE_WATCH 23 /* Watch address reference */
428 #define EXCCODE_VCED 31 /* Virtual coherency data */
431 * Bits in the coprocessor 0 config register.
434 #define CONF_CM_CACHABLE_NO_WA 0
435 #define CONF_CM_CACHABLE_WA 1
436 #define CONF_CM_UNCACHED 2
437 #define CONF_CM_CACHABLE_NONCOHERENT 3
438 #define CONF_CM_CACHABLE_CE 4
439 #define CONF_CM_CACHABLE_COW 5
440 #define CONF_CM_CACHABLE_CUW 6
441 #define CONF_CM_CACHABLE_ACCELERATED 7
442 #define CONF_CM_CMASK 7
443 #define CONF_BE (_ULCAST_(1) << 15)
445 /* Bits common to various processors. */
446 #define CONF_CU (_ULCAST_(1) << 3)
447 #define CONF_DB (_ULCAST_(1) << 4)
448 #define CONF_IB (_ULCAST_(1) << 5)
449 #define CONF_DC (_ULCAST_(7) << 6)
450 #define CONF_IC (_ULCAST_(7) << 9)
451 #define CONF_EB (_ULCAST_(1) << 13)
452 #define CONF_EM (_ULCAST_(1) << 14)
453 #define CONF_SM (_ULCAST_(1) << 16)
454 #define CONF_SC (_ULCAST_(1) << 17)
455 #define CONF_EW (_ULCAST_(3) << 18)
456 #define CONF_EP (_ULCAST_(15)<< 24)
457 #define CONF_EC (_ULCAST_(7) << 28)
458 #define CONF_CM (_ULCAST_(1) << 31)
460 /* Bits specific to the R4xx0. */
461 #define R4K_CONF_SW (_ULCAST_(1) << 20)
462 #define R4K_CONF_SS (_ULCAST_(1) << 21)
463 #define R4K_CONF_SB (_ULCAST_(3) << 22)
465 /* Bits specific to the R5000. */
466 #define R5K_CONF_SE (_ULCAST_(1) << 12)
467 #define R5K_CONF_SS (_ULCAST_(3) << 20)
469 /* Bits specific to the RM7000. */
470 #define RM7K_CONF_SE (_ULCAST_(1) << 3)
471 #define RM7K_CONF_TE (_ULCAST_(1) << 12)
472 #define RM7K_CONF_CLK (_ULCAST_(1) << 16)
473 #define RM7K_CONF_TC (_ULCAST_(1) << 17)
474 #define RM7K_CONF_SI (_ULCAST_(3) << 20)
475 #define RM7K_CONF_SC (_ULCAST_(1) << 31)
477 /* Bits specific to the R10000. */
478 #define R10K_CONF_DN (_ULCAST_(3) << 3)
479 #define R10K_CONF_CT (_ULCAST_(1) << 5)
480 #define R10K_CONF_PE (_ULCAST_(1) << 6)
481 #define R10K_CONF_PM (_ULCAST_(3) << 7)
482 #define R10K_CONF_EC (_ULCAST_(15)<< 9)
483 #define R10K_CONF_SB (_ULCAST_(1) << 13)
484 #define R10K_CONF_SK (_ULCAST_(1) << 14)
485 #define R10K_CONF_SS (_ULCAST_(7) << 16)
486 #define R10K_CONF_SC (_ULCAST_(7) << 19)
487 #define R10K_CONF_DC (_ULCAST_(7) << 26)
488 #define R10K_CONF_IC (_ULCAST_(7) << 29)
490 /* Bits specific to the VR41xx. */
491 #define VR41_CONF_CS (_ULCAST_(1) << 12)
492 #define VR41_CONF_P4K (_ULCAST_(1) << 13)
493 #define VR41_CONF_BP (_ULCAST_(1) << 16)
494 #define VR41_CONF_M16 (_ULCAST_(1) << 20)
495 #define VR41_CONF_AD (_ULCAST_(1) << 23)
497 /* Bits specific to the R30xx. */
498 #define R30XX_CONF_FDM (_ULCAST_(1) << 19)
499 #define R30XX_CONF_REV (_ULCAST_(1) << 22)
500 #define R30XX_CONF_AC (_ULCAST_(1) << 23)
501 #define R30XX_CONF_RF (_ULCAST_(1) << 24)
502 #define R30XX_CONF_HALT (_ULCAST_(1) << 25)
503 #define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
504 #define R30XX_CONF_DBR (_ULCAST_(1) << 29)
505 #define R30XX_CONF_SB (_ULCAST_(1) << 30)
506 #define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
508 /* Bits specific to the TX49. */
509 #define TX49_CONF_DC (_ULCAST_(1) << 16)
510 #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
511 #define TX49_CONF_HALT (_ULCAST_(1) << 18)
512 #define TX49_CONF_CWFON (_ULCAST_(1) << 27)
514 /* Bits specific to the MIPS32/64 PRA. */
515 #define MIPS_CONF_MT (_ULCAST_(7) << 7)
516 #define MIPS_CONF_MT_TLB (_ULCAST_(1) << 7)
517 #define MIPS_CONF_MT_FTLB (_ULCAST_(4) << 7)
518 #define MIPS_CONF_AR (_ULCAST_(7) << 10)
519 #define MIPS_CONF_AT (_ULCAST_(3) << 13)
520 #define MIPS_CONF_M (_ULCAST_(1) << 31)
523 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
525 #define MIPS_CONF1_FP (_ULCAST_(1) << 0)
526 #define MIPS_CONF1_EP (_ULCAST_(1) << 1)
527 #define MIPS_CONF1_CA (_ULCAST_(1) << 2)
528 #define MIPS_CONF1_WR (_ULCAST_(1) << 3)
529 #define MIPS_CONF1_PC (_ULCAST_(1) << 4)
530 #define MIPS_CONF1_MD (_ULCAST_(1) << 5)
531 #define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
532 #define MIPS_CONF1_DA_SHF 7
533 #define MIPS_CONF1_DA_SZ 3
534 #define MIPS_CONF1_DA (_ULCAST_(7) << 7)
535 #define MIPS_CONF1_DL_SHF 10
536 #define MIPS_CONF1_DL_SZ 3
537 #define MIPS_CONF1_DL (_ULCAST_(7) << 10)
538 #define MIPS_CONF1_DS_SHF 13
539 #define MIPS_CONF1_DS_SZ 3
540 #define MIPS_CONF1_DS (_ULCAST_(7) << 13)
541 #define MIPS_CONF1_IA_SHF 16
542 #define MIPS_CONF1_IA_SZ 3
543 #define MIPS_CONF1_IA (_ULCAST_(7) << 16)
544 #define MIPS_CONF1_IL_SHF 19
545 #define MIPS_CONF1_IL_SZ 3
546 #define MIPS_CONF1_IL (_ULCAST_(7) << 19)
547 #define MIPS_CONF1_IS_SHF 22
548 #define MIPS_CONF1_IS_SZ 3
549 #define MIPS_CONF1_IS (_ULCAST_(7) << 22)
550 #define MIPS_CONF1_TLBS_SHIFT (25)
551 #define MIPS_CONF1_TLBS_SIZE (6)
552 #define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
554 #define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
555 #define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
556 #define MIPS_CONF2_SS (_ULCAST_(15)<< 8)
557 #define MIPS_CONF2_SU (_ULCAST_(15)<< 12)
558 #define MIPS_CONF2_TA (_ULCAST_(15)<< 16)
559 #define MIPS_CONF2_TL (_ULCAST_(15)<< 20)
560 #define MIPS_CONF2_TS (_ULCAST_(15)<< 24)
561 #define MIPS_CONF2_TU (_ULCAST_(7) << 28)
563 #define MIPS_CONF3_TL (_ULCAST_(1) << 0)
564 #define MIPS_CONF3_SM (_ULCAST_(1) << 1)
565 #define MIPS_CONF3_MT (_ULCAST_(1) << 2)
566 #define MIPS_CONF3_CDMM (_ULCAST_(1) << 3)
567 #define MIPS_CONF3_SP (_ULCAST_(1) << 4)
568 #define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
569 #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
570 #define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
571 #define MIPS_CONF3_ITL (_ULCAST_(1) << 8)
572 #define MIPS_CONF3_CTXTC (_ULCAST_(1) << 9)
573 #define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
574 #define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11)
575 #define MIPS_CONF3_RXI (_ULCAST_(1) << 12)
576 #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
577 #define MIPS_CONF3_ISA (_ULCAST_(3) << 14)
578 #define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16)
579 #define MIPS_CONF3_MCU (_ULCAST_(1) << 17)
580 #define MIPS_CONF3_MMAR (_ULCAST_(7) << 18)
581 #define MIPS_CONF3_IPLW (_ULCAST_(3) << 21)
582 #define MIPS_CONF3_VZ (_ULCAST_(1) << 23)
583 #define MIPS_CONF3_PW (_ULCAST_(1) << 24)
584 #define MIPS_CONF3_SC (_ULCAST_(1) << 25)
585 #define MIPS_CONF3_BI (_ULCAST_(1) << 26)
586 #define MIPS_CONF3_BP (_ULCAST_(1) << 27)
587 #define MIPS_CONF3_MSA (_ULCAST_(1) << 28)
588 #define MIPS_CONF3_CMGCR (_ULCAST_(1) << 29)
589 #define MIPS_CONF3_BPG (_ULCAST_(1) << 30)
591 #define MIPS_CONF4_MMUSIZEEXT_SHIFT (0)
592 #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
593 #define MIPS_CONF4_FTLBSETS_SHIFT (0)
594 #define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
595 #define MIPS_CONF4_FTLBWAYS_SHIFT (4)
596 #define MIPS_CONF4_FTLBWAYS (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
597 #define MIPS_CONF4_FTLBPAGESIZE_SHIFT (8)
598 /* bits 10:8 in FTLB-only configurations */
599 #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
600 /* bits 12:8 in VTLB-FTLB only configurations */
601 #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
602 #define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
603 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
604 #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT (_ULCAST_(2) << 14)
605 #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT (_ULCAST_(3) << 14)
606 #define MIPS_CONF4_KSCREXIST (_ULCAST_(255) << 16)
607 #define MIPS_CONF4_VTLBSIZEEXT_SHIFT (24)
608 #define MIPS_CONF4_VTLBSIZEEXT (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
609 #define MIPS_CONF4_AE (_ULCAST_(1) << 28)
610 #define MIPS_CONF4_IE (_ULCAST_(3) << 29)
611 #define MIPS_CONF4_TLBINV (_ULCAST_(2) << 29)
613 #define MIPS_CONF5_NF (_ULCAST_(1) << 0)
614 #define MIPS_CONF5_UFR (_ULCAST_(1) << 2)
615 #define MIPS_CONF5_MRP (_ULCAST_(1) << 3)
616 #define MIPS_CONF5_LLB (_ULCAST_(1) << 4)
617 #define MIPS_CONF5_MVH (_ULCAST_(1) << 5)
618 #define MIPS_CONF5_FRE (_ULCAST_(1) << 8)
619 #define MIPS_CONF5_UFE (_ULCAST_(1) << 9)
620 #define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27)
621 #define MIPS_CONF5_EVA (_ULCAST_(1) << 28)
622 #define MIPS_CONF5_CV (_ULCAST_(1) << 29)
623 #define MIPS_CONF5_K (_ULCAST_(1) << 30)
625 #define MIPS_CONF6_SYND (_ULCAST_(1) << 13)
626 /* proAptiv FTLB on/off bit */
627 #define MIPS_CONF6_FTLBEN (_ULCAST_(1) << 15)
628 /* FTLB probability bits */
629 #define MIPS_CONF6_FTLBP_SHIFT (16)
631 #define MIPS_CONF7_WII (_ULCAST_(1) << 31)
633 #define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
635 #define MIPS_CONF7_IAR (_ULCAST_(1) << 10)
636 #define MIPS_CONF7_AR (_ULCAST_(1) << 16)
637 /* FTLB probability bits for R6 */
638 #define MIPS_CONF7_FTLBP_SHIFT (18)
640 /* MAAR bit definitions */
641 #define MIPS_MAAR_ADDR ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
642 #define MIPS_MAAR_ADDR_SHIFT 12
643 #define MIPS_MAAR_S (_ULCAST_(1) << 1)
644 #define MIPS_MAAR_V (_ULCAST_(1) << 0)
646 /* CMGCRBase bit definitions */
647 #define MIPS_CMGCRB_BASE 11
648 #define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
651 * Bits in the MIPS32 Memory Segmentation registers.
653 #define MIPS_SEGCFG_PA_SHIFT 9
654 #define MIPS_SEGCFG_PA (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
655 #define MIPS_SEGCFG_AM_SHIFT 4
656 #define MIPS_SEGCFG_AM (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
657 #define MIPS_SEGCFG_EU_SHIFT 3
658 #define MIPS_SEGCFG_EU (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
659 #define MIPS_SEGCFG_C_SHIFT 0
660 #define MIPS_SEGCFG_C (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
662 #define MIPS_SEGCFG_UUSK _ULCAST_(7)
663 #define MIPS_SEGCFG_USK _ULCAST_(5)
664 #define MIPS_SEGCFG_MUSUK _ULCAST_(4)
665 #define MIPS_SEGCFG_MUSK _ULCAST_(3)
666 #define MIPS_SEGCFG_MSK _ULCAST_(2)
667 #define MIPS_SEGCFG_MK _ULCAST_(1)
668 #define MIPS_SEGCFG_UK _ULCAST_(0)
670 #define MIPS_PWFIELD_GDI_SHIFT 24
671 #define MIPS_PWFIELD_GDI_MASK 0x3f000000
672 #define MIPS_PWFIELD_UDI_SHIFT 18
673 #define MIPS_PWFIELD_UDI_MASK 0x00fc0000
674 #define MIPS_PWFIELD_MDI_SHIFT 12
675 #define MIPS_PWFIELD_MDI_MASK 0x0003f000
676 #define MIPS_PWFIELD_PTI_SHIFT 6
677 #define MIPS_PWFIELD_PTI_MASK 0x00000fc0
678 #define MIPS_PWFIELD_PTEI_SHIFT 0
679 #define MIPS_PWFIELD_PTEI_MASK 0x0000003f
681 #define MIPS_PWSIZE_GDW_SHIFT 24
682 #define MIPS_PWSIZE_GDW_MASK 0x3f000000
683 #define MIPS_PWSIZE_UDW_SHIFT 18
684 #define MIPS_PWSIZE_UDW_MASK 0x00fc0000
685 #define MIPS_PWSIZE_MDW_SHIFT 12
686 #define MIPS_PWSIZE_MDW_MASK 0x0003f000
687 #define MIPS_PWSIZE_PTW_SHIFT 6
688 #define MIPS_PWSIZE_PTW_MASK 0x00000fc0
689 #define MIPS_PWSIZE_PTEW_SHIFT 0
690 #define MIPS_PWSIZE_PTEW_MASK 0x0000003f
692 #define MIPS_PWCTL_PWEN_SHIFT 31
693 #define MIPS_PWCTL_PWEN_MASK 0x80000000
694 #define MIPS_PWCTL_DPH_SHIFT 7
695 #define MIPS_PWCTL_DPH_MASK 0x00000080
696 #define MIPS_PWCTL_HUGEPG_SHIFT 6
697 #define MIPS_PWCTL_HUGEPG_MASK 0x00000060
698 #define MIPS_PWCTL_PSN_SHIFT 0
699 #define MIPS_PWCTL_PSN_MASK 0x0000003f
701 /* CDMMBase register bit definitions */
702 #define MIPS_CDMMBASE_SIZE_SHIFT 0
703 #define MIPS_CDMMBASE_SIZE (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
704 #define MIPS_CDMMBASE_CI (_ULCAST_(1) << 9)
705 #define MIPS_CDMMBASE_EN (_ULCAST_(1) << 10)
706 #define MIPS_CDMMBASE_ADDR_SHIFT 11
707 #define MIPS_CDMMBASE_ADDR_START 15
710 * Bitfields in the TX39 family CP0 Configuration Register 3
712 #define TX39_CONF_ICS_SHIFT 19
713 #define TX39_CONF_ICS_MASK 0x00380000
714 #define TX39_CONF_ICS_1KB 0x00000000
715 #define TX39_CONF_ICS_2KB 0x00080000
716 #define TX39_CONF_ICS_4KB 0x00100000
717 #define TX39_CONF_ICS_8KB 0x00180000
718 #define TX39_CONF_ICS_16KB 0x00200000
720 #define TX39_CONF_DCS_SHIFT 16
721 #define TX39_CONF_DCS_MASK 0x00070000
722 #define TX39_CONF_DCS_1KB 0x00000000
723 #define TX39_CONF_DCS_2KB 0x00010000
724 #define TX39_CONF_DCS_4KB 0x00020000
725 #define TX39_CONF_DCS_8KB 0x00030000
726 #define TX39_CONF_DCS_16KB 0x00040000
728 #define TX39_CONF_CWFON 0x00004000
729 #define TX39_CONF_WBON 0x00002000
730 #define TX39_CONF_RF_SHIFT 10
731 #define TX39_CONF_RF_MASK 0x00000c00
732 #define TX39_CONF_DOZE 0x00000200
733 #define TX39_CONF_HALT 0x00000100
734 #define TX39_CONF_LOCK 0x00000080
735 #define TX39_CONF_ICE 0x00000020
736 #define TX39_CONF_DCE 0x00000010
737 #define TX39_CONF_IRSIZE_SHIFT 2
738 #define TX39_CONF_IRSIZE_MASK 0x0000000c
739 #define TX39_CONF_DRSIZE_SHIFT 0
740 #define TX39_CONF_DRSIZE_MASK 0x00000003
743 * Interesting Bits in the R10K CP0 Branch Diagnostic Register
745 /* Disable Branch Target Address Cache */
746 #define R10K_DIAG_D_BTAC (_ULCAST_(1) << 27)
747 /* Enable Branch Prediction Global History */
748 #define R10K_DIAG_E_GHIST (_ULCAST_(1) << 26)
749 /* Disable Branch Return Cache */
750 #define R10K_DIAG_D_BRC (_ULCAST_(1) << 22)
753 * Coprocessor 1 (FPU) register names
755 #define CP1_REVISION $0
761 #define CP1_STATUS $31
765 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
767 #define MIPS_FPIR_S (_ULCAST_(1) << 16)
768 #define MIPS_FPIR_D (_ULCAST_(1) << 17)
769 #define MIPS_FPIR_PS (_ULCAST_(1) << 18)
770 #define MIPS_FPIR_3D (_ULCAST_(1) << 19)
771 #define MIPS_FPIR_W (_ULCAST_(1) << 20)
772 #define MIPS_FPIR_L (_ULCAST_(1) << 21)
773 #define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
774 #define MIPS_FPIR_HAS2008 (_ULCAST_(1) << 23)
775 #define MIPS_FPIR_UFRP (_ULCAST_(1) << 28)
776 #define MIPS_FPIR_FREP (_ULCAST_(1) << 29)
779 * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
781 #define MIPS_FCCR_CONDX_S 0
782 #define MIPS_FCCR_CONDX (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
783 #define MIPS_FCCR_COND0_S 0
784 #define MIPS_FCCR_COND0 (_ULCAST_(1) << MIPS_FCCR_COND0_S)
785 #define MIPS_FCCR_COND1_S 1
786 #define MIPS_FCCR_COND1 (_ULCAST_(1) << MIPS_FCCR_COND1_S)
787 #define MIPS_FCCR_COND2_S 2
788 #define MIPS_FCCR_COND2 (_ULCAST_(1) << MIPS_FCCR_COND2_S)
789 #define MIPS_FCCR_COND3_S 3
790 #define MIPS_FCCR_COND3 (_ULCAST_(1) << MIPS_FCCR_COND3_S)
791 #define MIPS_FCCR_COND4_S 4
792 #define MIPS_FCCR_COND4 (_ULCAST_(1) << MIPS_FCCR_COND4_S)
793 #define MIPS_FCCR_COND5_S 5
794 #define MIPS_FCCR_COND5 (_ULCAST_(1) << MIPS_FCCR_COND5_S)
795 #define MIPS_FCCR_COND6_S 6
796 #define MIPS_FCCR_COND6 (_ULCAST_(1) << MIPS_FCCR_COND6_S)
797 #define MIPS_FCCR_COND7_S 7
798 #define MIPS_FCCR_COND7 (_ULCAST_(1) << MIPS_FCCR_COND7_S)
801 * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
803 #define MIPS_FENR_FS_S 2
804 #define MIPS_FENR_FS (_ULCAST_(1) << MIPS_FENR_FS_S)
807 * FPU Status Register Values
809 #define FPU_CSR_COND_S 23 /* $fcc0 */
810 #define FPU_CSR_COND (_ULCAST_(1) << FPU_CSR_COND_S)
812 #define FPU_CSR_FS_S 24 /* flush denormalised results to 0 */
813 #define FPU_CSR_FS (_ULCAST_(1) << FPU_CSR_FS_S)
815 #define FPU_CSR_CONDX_S 25 /* $fcc[7:1] */
816 #define FPU_CSR_CONDX (_ULCAST_(127) << FPU_CSR_CONDX_S)
817 #define FPU_CSR_COND1_S 25 /* $fcc1 */
818 #define FPU_CSR_COND1 (_ULCAST_(1) << FPU_CSR_COND1_S)
819 #define FPU_CSR_COND2_S 26 /* $fcc2 */
820 #define FPU_CSR_COND2 (_ULCAST_(1) << FPU_CSR_COND2_S)
821 #define FPU_CSR_COND3_S 27 /* $fcc3 */
822 #define FPU_CSR_COND3 (_ULCAST_(1) << FPU_CSR_COND3_S)
823 #define FPU_CSR_COND4_S 28 /* $fcc4 */
824 #define FPU_CSR_COND4 (_ULCAST_(1) << FPU_CSR_COND4_S)
825 #define FPU_CSR_COND5_S 29 /* $fcc5 */
826 #define FPU_CSR_COND5 (_ULCAST_(1) << FPU_CSR_COND5_S)
827 #define FPU_CSR_COND6_S 30 /* $fcc6 */
828 #define FPU_CSR_COND6 (_ULCAST_(1) << FPU_CSR_COND6_S)
829 #define FPU_CSR_COND7_S 31 /* $fcc7 */
830 #define FPU_CSR_COND7 (_ULCAST_(1) << FPU_CSR_COND7_S)
833 * Bits 22:20 of the FPU Status Register will be read as 0,
834 * and should be written as zero.
836 #define FPU_CSR_RSVD (_ULCAST_(7) << 20)
838 #define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
839 #define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
842 * X the exception cause indicator
843 * E the exception enable
844 * S the sticky/flag bit
846 #define FPU_CSR_ALL_X 0x0003f000
847 #define FPU_CSR_UNI_X 0x00020000
848 #define FPU_CSR_INV_X 0x00010000
849 #define FPU_CSR_DIV_X 0x00008000
850 #define FPU_CSR_OVF_X 0x00004000
851 #define FPU_CSR_UDF_X 0x00002000
852 #define FPU_CSR_INE_X 0x00001000
854 #define FPU_CSR_ALL_E 0x00000f80
855 #define FPU_CSR_INV_E 0x00000800
856 #define FPU_CSR_DIV_E 0x00000400
857 #define FPU_CSR_OVF_E 0x00000200
858 #define FPU_CSR_UDF_E 0x00000100
859 #define FPU_CSR_INE_E 0x00000080
861 #define FPU_CSR_ALL_S 0x0000007c
862 #define FPU_CSR_INV_S 0x00000040
863 #define FPU_CSR_DIV_S 0x00000020
864 #define FPU_CSR_OVF_S 0x00000010
865 #define FPU_CSR_UDF_S 0x00000008
866 #define FPU_CSR_INE_S 0x00000004
868 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
869 #define FPU_CSR_RM 0x00000003
870 #define FPU_CSR_RN 0x0 /* nearest */
871 #define FPU_CSR_RZ 0x1 /* towards zero */
872 #define FPU_CSR_RU 0x2 /* towards +Infinity */
873 #define FPU_CSR_RD 0x3 /* towards -Infinity */
879 * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
881 #if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
882 defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
883 #define get_isa16_mode(x) ((x) & 0x1)
884 #define msk_isa16_mode(x) ((x) & ~0x1)
885 #define set_isa16_mode(x) do { (x) |= 0x1; } while(0)
887 #define get_isa16_mode(x) 0
888 #define msk_isa16_mode(x) (x)
889 #define set_isa16_mode(x) do { } while(0)
893 * microMIPS instructions can be 16-bit or 32-bit in length. This
894 * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
896 static inline int mm_insn_16bit(u16 insn)
898 u16 opcode = (insn >> 10) & 0x7;
900 return (opcode >= 1 && opcode <= 3) ? 1 : 0;
904 * TLB Invalidate Flush
906 static inline void tlbinvf(void)
908 __asm__ __volatile__(
911 ".word 0x42000004\n\t" /* tlbinvf */
917 * Functions to access the R10000 performance counters. These are basically
918 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
919 * performance counter number encoded into bits 1 ... 5 of the instruction.
920 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
921 * disassembler these will look like an access to sel 0 or 1.
923 #define read_r10k_perf_cntr(counter) \
925 unsigned int __res; \
926 __asm__ __volatile__( \
934 #define write_r10k_perf_cntr(counter,val) \
936 __asm__ __volatile__( \
939 : "r" (val), "i" (counter)); \
942 #define read_r10k_perf_event(counter) \
944 unsigned int __res; \
945 __asm__ __volatile__( \
953 #define write_r10k_perf_cntl(counter,val) \
955 __asm__ __volatile__( \
958 : "r" (val), "i" (counter)); \
963 * Macros to access the system control coprocessor
966 #define __read_32bit_c0_register(source, sel) \
967 ({ unsigned int __res; \
969 __asm__ __volatile__( \
970 "mfc0\t%0, " #source "\n\t" \
973 __asm__ __volatile__( \
975 "mfc0\t%0, " #source ", " #sel "\n\t" \
981 #define __read_64bit_c0_register(source, sel) \
982 ({ unsigned long long __res; \
983 if (sizeof(unsigned long) == 4) \
984 __res = __read_64bit_c0_split(source, sel); \
986 __asm__ __volatile__( \
988 "dmfc0\t%0, " #source "\n\t" \
992 __asm__ __volatile__( \
994 "dmfc0\t%0, " #source ", " #sel "\n\t" \
1000 #define __write_32bit_c0_register(register, sel, value) \
1003 __asm__ __volatile__( \
1004 "mtc0\t%z0, " #register "\n\t" \
1005 : : "Jr" ((unsigned int)(value))); \
1007 __asm__ __volatile__( \
1008 ".set\tmips32\n\t" \
1009 "mtc0\t%z0, " #register ", " #sel "\n\t" \
1011 : : "Jr" ((unsigned int)(value))); \
1014 #define __write_64bit_c0_register(register, sel, value) \
1016 if (sizeof(unsigned long) == 4) \
1017 __write_64bit_c0_split(register, sel, value); \
1018 else if (sel == 0) \
1019 __asm__ __volatile__( \
1021 "dmtc0\t%z0, " #register "\n\t" \
1023 : : "Jr" (value)); \
1025 __asm__ __volatile__( \
1026 ".set\tmips64\n\t" \
1027 "dmtc0\t%z0, " #register ", " #sel "\n\t" \
1029 : : "Jr" (value)); \
1032 #define __read_ulong_c0_register(reg, sel) \
1033 ((sizeof(unsigned long) == 4) ? \
1034 (unsigned long) __read_32bit_c0_register(reg, sel) : \
1035 (unsigned long) __read_64bit_c0_register(reg, sel))
1037 #define __write_ulong_c0_register(reg, sel, val) \
1039 if (sizeof(unsigned long) == 4) \
1040 __write_32bit_c0_register(reg, sel, val); \
1042 __write_64bit_c0_register(reg, sel, val); \
1046 * On RM7000/RM9000 these are uses to access cop0 set 1 registers
1048 #define __read_32bit_c0_ctrl_register(source) \
1049 ({ unsigned int __res; \
1050 __asm__ __volatile__( \
1051 "cfc0\t%0, " #source "\n\t" \
1056 #define __write_32bit_c0_ctrl_register(register, value) \
1058 __asm__ __volatile__( \
1059 "ctc0\t%z0, " #register "\n\t" \
1060 : : "Jr" ((unsigned int)(value))); \
1064 * These versions are only needed for systems with more than 38 bits of
1065 * physical address space running the 32-bit kernel. That's none atm :-)
1067 #define __read_64bit_c0_split(source, sel) \
1069 unsigned long long __val; \
1070 unsigned long __flags; \
1072 local_irq_save(__flags); \
1074 __asm__ __volatile__( \
1075 ".set\tmips64\n\t" \
1076 "dmfc0\t%M0, " #source "\n\t" \
1077 "dsll\t%L0, %M0, 32\n\t" \
1078 "dsra\t%M0, %M0, 32\n\t" \
1079 "dsra\t%L0, %L0, 32\n\t" \
1083 __asm__ __volatile__( \
1084 ".set\tmips64\n\t" \
1085 "dmfc0\t%M0, " #source ", " #sel "\n\t" \
1086 "dsll\t%L0, %M0, 32\n\t" \
1087 "dsra\t%M0, %M0, 32\n\t" \
1088 "dsra\t%L0, %L0, 32\n\t" \
1091 local_irq_restore(__flags); \
1096 #define __write_64bit_c0_split(source, sel, val) \
1098 unsigned long __flags; \
1100 local_irq_save(__flags); \
1102 __asm__ __volatile__( \
1103 ".set\tmips64\n\t" \
1104 "dsll\t%L0, %L0, 32\n\t" \
1105 "dsrl\t%L0, %L0, 32\n\t" \
1106 "dsll\t%M0, %M0, 32\n\t" \
1107 "or\t%L0, %L0, %M0\n\t" \
1108 "dmtc0\t%L0, " #source "\n\t" \
1112 __asm__ __volatile__( \
1113 ".set\tmips64\n\t" \
1114 "dsll\t%L0, %L0, 32\n\t" \
1115 "dsrl\t%L0, %L0, 32\n\t" \
1116 "dsll\t%M0, %M0, 32\n\t" \
1117 "or\t%L0, %L0, %M0\n\t" \
1118 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
1121 local_irq_restore(__flags); \
1124 #define __readx_32bit_c0_register(source) \
1126 unsigned int __res; \
1128 __asm__ __volatile__( \
1131 " .set mips32r2 \n" \
1133 " # mfhc0 $1, %1 \n" \
1134 " .word (0x40410000 | ((%1 & 0x1f) << 11)) \n" \
1142 #define __writex_32bit_c0_register(register, value) \
1144 __asm__ __volatile__( \
1147 " .set mips32r2 \n" \
1149 " # mthc0 $1, %1 \n" \
1151 " .word (0x40c10000 | ((%1 & 0x1f) << 11)) \n" \
1154 : "r" (value), "i" (register)); \
1157 #define read_c0_index() __read_32bit_c0_register($0, 0)
1158 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
1160 #define read_c0_random() __read_32bit_c0_register($1, 0)
1161 #define write_c0_random(val) __write_32bit_c0_register($1, 0, val)
1163 #define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
1164 #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
1166 #define readx_c0_entrylo0() __readx_32bit_c0_register(2)
1167 #define writex_c0_entrylo0(val) __writex_32bit_c0_register(2, val)
1169 #define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
1170 #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
1172 #define readx_c0_entrylo1() __readx_32bit_c0_register(3)
1173 #define writex_c0_entrylo1(val) __writex_32bit_c0_register(3, val)
1175 #define read_c0_conf() __read_32bit_c0_register($3, 0)
1176 #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
1178 #define read_c0_context() __read_ulong_c0_register($4, 0)
1179 #define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
1181 #define read_c0_userlocal() __read_ulong_c0_register($4, 2)
1182 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
1184 #define read_c0_pagemask() __read_32bit_c0_register($5, 0)
1185 #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
1187 #define read_c0_pagegrain() __read_32bit_c0_register($5, 1)
1188 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
1190 #define read_c0_wired() __read_32bit_c0_register($6, 0)
1191 #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
1193 #define read_c0_info() __read_32bit_c0_register($7, 0)
1195 #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
1196 #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
1198 #define read_c0_badvaddr() __read_ulong_c0_register($8, 0)
1199 #define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val)
1201 #define read_c0_count() __read_32bit_c0_register($9, 0)
1202 #define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
1204 #define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */
1205 #define write_c0_count2(val) __write_32bit_c0_register($9, 6, val)
1207 #define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */
1208 #define write_c0_count3(val) __write_32bit_c0_register($9, 7, val)
1210 #define read_c0_entryhi() __read_ulong_c0_register($10, 0)
1211 #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
1213 #define read_c0_compare() __read_32bit_c0_register($11, 0)
1214 #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
1216 #define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */
1217 #define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val)
1219 #define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */
1220 #define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val)
1222 #define read_c0_status() __read_32bit_c0_register($12, 0)
1224 #define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
1226 #define read_c0_cause() __read_32bit_c0_register($13, 0)
1227 #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
1229 #define read_c0_epc() __read_ulong_c0_register($14, 0)
1230 #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
1232 #define read_c0_prid() __read_32bit_c0_register($15, 0)
1234 #define read_c0_cmgcrbase() __read_ulong_c0_register($15, 3)
1236 #define read_c0_config() __read_32bit_c0_register($16, 0)
1237 #define read_c0_config1() __read_32bit_c0_register($16, 1)
1238 #define read_c0_config2() __read_32bit_c0_register($16, 2)
1239 #define read_c0_config3() __read_32bit_c0_register($16, 3)
1240 #define read_c0_config4() __read_32bit_c0_register($16, 4)
1241 #define read_c0_config5() __read_32bit_c0_register($16, 5)
1242 #define read_c0_config6() __read_32bit_c0_register($16, 6)
1243 #define read_c0_config7() __read_32bit_c0_register($16, 7)
1244 #define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
1245 #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
1246 #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
1247 #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
1248 #define write_c0_config4(val) __write_32bit_c0_register($16, 4, val)
1249 #define write_c0_config5(val) __write_32bit_c0_register($16, 5, val)
1250 #define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
1251 #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
1253 #define read_c0_lladdr() __read_ulong_c0_register($17, 0)
1254 #define write_c0_lladdr(val) __write_ulong_c0_register($17, 0, val)
1255 #define read_c0_maar() __read_ulong_c0_register($17, 1)
1256 #define write_c0_maar(val) __write_ulong_c0_register($17, 1, val)
1257 #define read_c0_maari() __read_32bit_c0_register($17, 2)
1258 #define write_c0_maari(val) __write_32bit_c0_register($17, 2, val)
1261 * The WatchLo register. There may be up to 8 of them.
1263 #define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
1264 #define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
1265 #define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
1266 #define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
1267 #define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
1268 #define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
1269 #define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
1270 #define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
1271 #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
1272 #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
1273 #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
1274 #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
1275 #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
1276 #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
1277 #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
1278 #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
1281 * The WatchHi register. There may be up to 8 of them.
1283 #define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
1284 #define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
1285 #define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
1286 #define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
1287 #define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
1288 #define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
1289 #define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
1290 #define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
1292 #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
1293 #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
1294 #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
1295 #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
1296 #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
1297 #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
1298 #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
1299 #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
1301 #define read_c0_xcontext() __read_ulong_c0_register($20, 0)
1302 #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
1304 #define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20)
1305 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
1307 #define read_c0_framemask() __read_32bit_c0_register($21, 0)
1308 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1310 #define read_c0_diag() __read_32bit_c0_register($22, 0)
1311 #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
1313 /* R10K CP0 Branch Diagnostic register is 64bits wide */
1314 #define read_c0_r10k_diag() __read_64bit_c0_register($22, 0)
1315 #define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val)
1317 #define read_c0_diag1() __read_32bit_c0_register($22, 1)
1318 #define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val)
1320 #define read_c0_diag2() __read_32bit_c0_register($22, 2)
1321 #define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val)
1323 #define read_c0_diag3() __read_32bit_c0_register($22, 3)
1324 #define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val)
1326 #define read_c0_diag4() __read_32bit_c0_register($22, 4)
1327 #define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val)
1329 #define read_c0_diag5() __read_32bit_c0_register($22, 5)
1330 #define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val)
1332 #define read_c0_debug() __read_32bit_c0_register($23, 0)
1333 #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
1335 #define read_c0_depc() __read_ulong_c0_register($24, 0)
1336 #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
1339 * MIPS32 / MIPS64 performance counters
1341 #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0)
1342 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1343 #define read_c0_perfcntr0() __read_32bit_c0_register($25, 1)
1344 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1345 #define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1)
1346 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1347 #define read_c0_perfctrl1() __read_32bit_c0_register($25, 2)
1348 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1349 #define read_c0_perfcntr1() __read_32bit_c0_register($25, 3)
1350 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1351 #define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3)
1352 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1353 #define read_c0_perfctrl2() __read_32bit_c0_register($25, 4)
1354 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1355 #define read_c0_perfcntr2() __read_32bit_c0_register($25, 5)
1356 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1357 #define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5)
1358 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1359 #define read_c0_perfctrl3() __read_32bit_c0_register($25, 6)
1360 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1361 #define read_c0_perfcntr3() __read_32bit_c0_register($25, 7)
1362 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1363 #define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7)
1364 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1366 #define read_c0_ecc() __read_32bit_c0_register($26, 0)
1367 #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
1369 #define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
1370 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1372 #define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
1374 #define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
1375 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1377 #define read_c0_taglo() __read_32bit_c0_register($28, 0)
1378 #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
1380 #define read_c0_dtaglo() __read_32bit_c0_register($28, 2)
1381 #define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val)
1383 #define read_c0_ddatalo() __read_32bit_c0_register($28, 3)
1384 #define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val)
1386 #define read_c0_staglo() __read_32bit_c0_register($28, 4)
1387 #define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val)
1389 #define read_c0_taghi() __read_32bit_c0_register($29, 0)
1390 #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
1392 #define read_c0_errorepc() __read_ulong_c0_register($30, 0)
1393 #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
1396 #define read_c0_hwrena() __read_32bit_c0_register($7, 0)
1397 #define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val)
1399 #define read_c0_intctl() __read_32bit_c0_register($12, 1)
1400 #define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val)
1402 #define read_c0_srsctl() __read_32bit_c0_register($12, 2)
1403 #define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val)
1405 #define read_c0_srsmap() __read_32bit_c0_register($12, 3)
1406 #define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val)
1408 #define read_c0_ebase() __read_32bit_c0_register($15, 1)
1409 #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
1411 #define read_c0_cdmmbase() __read_ulong_c0_register($15, 2)
1412 #define write_c0_cdmmbase(val) __write_ulong_c0_register($15, 2, val)
1415 #define read_c0_segctl0() __read_32bit_c0_register($5, 2)
1416 #define write_c0_segctl0(val) __write_32bit_c0_register($5, 2, val)
1418 #define read_c0_segctl1() __read_32bit_c0_register($5, 3)
1419 #define write_c0_segctl1(val) __write_32bit_c0_register($5, 3, val)
1421 #define read_c0_segctl2() __read_32bit_c0_register($5, 4)
1422 #define write_c0_segctl2(val) __write_32bit_c0_register($5, 4, val)
1424 /* Hardware Page Table Walker */
1425 #define read_c0_pwbase() __read_ulong_c0_register($5, 5)
1426 #define write_c0_pwbase(val) __write_ulong_c0_register($5, 5, val)
1428 #define read_c0_pwfield() __read_ulong_c0_register($5, 6)
1429 #define write_c0_pwfield(val) __write_ulong_c0_register($5, 6, val)
1431 #define read_c0_pwsize() __read_ulong_c0_register($5, 7)
1432 #define write_c0_pwsize(val) __write_ulong_c0_register($5, 7, val)
1434 #define read_c0_pwctl() __read_32bit_c0_register($6, 6)
1435 #define write_c0_pwctl(val) __write_32bit_c0_register($6, 6, val)
1437 /* Cavium OCTEON (cnMIPS) */
1438 #define read_c0_cvmcount() __read_ulong_c0_register($9, 6)
1439 #define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val)
1441 #define read_c0_cvmctl() __read_64bit_c0_register($9, 7)
1442 #define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val)
1444 #define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7)
1445 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1447 * The cacheerr registers are not standardized. On OCTEON, they are
1450 #define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0)
1451 #define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val)
1453 #define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1)
1454 #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val)
1457 #define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0)
1458 #define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val)
1460 #define read_c0_brcm_bus_pll() __read_32bit_c0_register($22, 4)
1461 #define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val)
1463 #define read_c0_brcm_reset() __read_32bit_c0_register($22, 5)
1464 #define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val)
1467 #define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1)
1468 #define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val)
1470 #define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2)
1471 #define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val)
1473 #define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3)
1474 #define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val)
1476 #define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5)
1477 #define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val)
1479 #define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6)
1480 #define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val)
1483 #define read_c0_brcm_config() __read_32bit_c0_register($22, 0)
1484 #define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val)
1486 #define read_c0_brcm_mode() __read_32bit_c0_register($22, 1)
1487 #define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val)
1489 #define read_c0_brcm_action() __read_32bit_c0_register($22, 2)
1490 #define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val)
1492 #define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3)
1493 #define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val)
1495 #define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4)
1496 #define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val)
1498 #define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7)
1499 #define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val)
1502 * Macros to access the floating point coprocessor control registers
1504 #define _read_32bit_cp1_register(source, gas_hardfloat) \
1506 unsigned int __res; \
1508 __asm__ __volatile__( \
1510 " .set reorder \n" \
1511 " # gas fails to assemble cfc1 for some archs, \n" \
1512 " # like Octeon. \n" \
1514 " "STR(gas_hardfloat)" \n" \
1515 " cfc1 %0,"STR(source)" \n" \
1521 #define _write_32bit_cp1_register(dest, val, gas_hardfloat) \
1523 __asm__ __volatile__( \
1525 " .set reorder \n" \
1526 " "STR(gas_hardfloat)" \n" \
1527 " ctc1 %0,"STR(dest)" \n" \
1532 #ifdef GAS_HAS_SET_HARDFLOAT
1533 #define read_32bit_cp1_register(source) \
1534 _read_32bit_cp1_register(source, .set hardfloat)
1535 #define write_32bit_cp1_register(dest, val) \
1536 _write_32bit_cp1_register(dest, val, .set hardfloat)
1538 #define read_32bit_cp1_register(source) \
1539 _read_32bit_cp1_register(source, )
1540 #define write_32bit_cp1_register(dest, val) \
1541 _write_32bit_cp1_register(dest, val, )
1545 #define rddsp(mask) \
1547 unsigned int __dspctl; \
1549 __asm__ __volatile__( \
1552 " rddsp %0, %x1 \n" \
1559 #define wrdsp(val, mask) \
1561 __asm__ __volatile__( \
1564 " wrdsp %0, %x1 \n" \
1567 : "r" (val), "i" (mask)); \
1576 " mflo %0, $ac0 \n" \
1588 " mflo %0, $ac1 \n" \
1600 " mflo %0, $ac2 \n" \
1612 " mflo %0, $ac3 \n" \
1624 " mfhi %0, $ac0 \n" \
1636 " mfhi %0, $ac1 \n" \
1648 " mfhi %0, $ac2 \n" \
1660 " mfhi %0, $ac3 \n" \
1672 " mtlo %0, $ac0 \n" \
1683 " mtlo %0, $ac1 \n" \
1694 " mtlo %0, $ac2 \n" \
1705 " mtlo %0, $ac3 \n" \
1716 " mthi %0, $ac0 \n" \
1727 " mthi %0, $ac1 \n" \
1738 " mthi %0, $ac2 \n" \
1749 " mthi %0, $ac3 \n" \
1757 #ifdef CONFIG_CPU_MICROMIPS
1758 #define rddsp(mask) \
1760 unsigned int __res; \
1762 __asm__ __volatile__( \
1765 " # rddsp $1, %x1 \n" \
1766 " .hword ((0x0020067c | (%x1 << 14)) >> 16) \n" \
1767 " .hword ((0x0020067c | (%x1 << 14)) & 0xffff) \n" \
1775 #define wrdsp(val, mask) \
1777 __asm__ __volatile__( \
1781 " # wrdsp $1, %x1 \n" \
1782 " .hword ((0x0020167c | (%x1 << 14)) >> 16) \n" \
1783 " .hword ((0x0020167c | (%x1 << 14)) & 0xffff) \n" \
1786 : "r" (val), "i" (mask)); \
1789 #define _umips_dsp_mfxxx(ins) \
1791 unsigned long __treg; \
1793 __asm__ __volatile__( \
1796 " .hword 0x0001 \n" \
1805 #define _umips_dsp_mtxxx(val, ins) \
1807 __asm__ __volatile__( \
1811 " .hword 0x0001 \n" \
1815 : "r" (val), "i" (ins)); \
1818 #define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c)
1819 #define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c)
1821 #define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c))
1822 #define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c))
1824 #define mflo0() _umips_dsp_mflo(0)
1825 #define mflo1() _umips_dsp_mflo(1)
1826 #define mflo2() _umips_dsp_mflo(2)
1827 #define mflo3() _umips_dsp_mflo(3)
1829 #define mfhi0() _umips_dsp_mfhi(0)
1830 #define mfhi1() _umips_dsp_mfhi(1)
1831 #define mfhi2() _umips_dsp_mfhi(2)
1832 #define mfhi3() _umips_dsp_mfhi(3)
1834 #define mtlo0(x) _umips_dsp_mtlo(x, 0)
1835 #define mtlo1(x) _umips_dsp_mtlo(x, 1)
1836 #define mtlo2(x) _umips_dsp_mtlo(x, 2)
1837 #define mtlo3(x) _umips_dsp_mtlo(x, 3)
1839 #define mthi0(x) _umips_dsp_mthi(x, 0)
1840 #define mthi1(x) _umips_dsp_mthi(x, 1)
1841 #define mthi2(x) _umips_dsp_mthi(x, 2)
1842 #define mthi3(x) _umips_dsp_mthi(x, 3)
1844 #else /* !CONFIG_CPU_MICROMIPS */
1845 #define rddsp(mask) \
1847 unsigned int __res; \
1849 __asm__ __volatile__( \
1852 " # rddsp $1, %x1 \n" \
1853 " .word 0x7c000cb8 | (%x1 << 16) \n" \
1861 #define wrdsp(val, mask) \
1863 __asm__ __volatile__( \
1867 " # wrdsp $1, %x1 \n" \
1868 " .word 0x7c2004f8 | (%x1 << 11) \n" \
1871 : "r" (val), "i" (mask)); \
1874 #define _dsp_mfxxx(ins) \
1876 unsigned long __treg; \
1878 __asm__ __volatile__( \
1881 " .word (0x00000810 | %1) \n" \
1889 #define _dsp_mtxxx(val, ins) \
1891 __asm__ __volatile__( \
1895 " .word (0x00200011 | %1) \n" \
1898 : "r" (val), "i" (ins)); \
1901 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
1902 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
1904 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
1905 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
1907 #define mflo0() _dsp_mflo(0)
1908 #define mflo1() _dsp_mflo(1)
1909 #define mflo2() _dsp_mflo(2)
1910 #define mflo3() _dsp_mflo(3)
1912 #define mfhi0() _dsp_mfhi(0)
1913 #define mfhi1() _dsp_mfhi(1)
1914 #define mfhi2() _dsp_mfhi(2)
1915 #define mfhi3() _dsp_mfhi(3)
1917 #define mtlo0(x) _dsp_mtlo(x, 0)
1918 #define mtlo1(x) _dsp_mtlo(x, 1)
1919 #define mtlo2(x) _dsp_mtlo(x, 2)
1920 #define mtlo3(x) _dsp_mtlo(x, 3)
1922 #define mthi0(x) _dsp_mthi(x, 0)
1923 #define mthi1(x) _dsp_mthi(x, 1)
1924 #define mthi2(x) _dsp_mthi(x, 2)
1925 #define mthi3(x) _dsp_mthi(x, 3)
1927 #endif /* CONFIG_CPU_MICROMIPS */
1933 * It is responsibility of the caller to take care of any TLB hazards.
1935 static inline void tlb_probe(void)
1937 __asm__ __volatile__(
1938 ".set noreorder\n\t"
1943 static inline void tlb_read(void)
1945 #if MIPS34K_MISSED_ITLB_WAR
1948 __asm__ __volatile__(
1950 " .set noreorder \n"
1953 " .word 0x41610001 # dvpe $1 \n"
1959 instruction_hazard();
1962 __asm__ __volatile__(
1963 ".set noreorder\n\t"
1967 #if MIPS34K_MISSED_ITLB_WAR
1968 if ((res & _ULCAST_(1)))
1969 __asm__ __volatile__(
1971 " .set noreorder \n"
1974 " .word 0x41600021 # evpe \n"
1980 static inline void tlb_write_indexed(void)
1982 __asm__ __volatile__(
1983 ".set noreorder\n\t"
1988 static inline void tlb_write_random(void)
1990 __asm__ __volatile__(
1991 ".set noreorder\n\t"
1997 * Manipulate bits in a c0 register.
1999 #define __BUILD_SET_C0(name) \
2000 static inline unsigned int \
2001 set_c0_##name(unsigned int set) \
2003 unsigned int res, new; \
2005 res = read_c0_##name(); \
2007 write_c0_##name(new); \
2012 static inline unsigned int \
2013 clear_c0_##name(unsigned int clear) \
2015 unsigned int res, new; \
2017 res = read_c0_##name(); \
2018 new = res & ~clear; \
2019 write_c0_##name(new); \
2024 static inline unsigned int \
2025 change_c0_##name(unsigned int change, unsigned int val) \
2027 unsigned int res, new; \
2029 res = read_c0_##name(); \
2030 new = res & ~change; \
2031 new |= (val & change); \
2032 write_c0_##name(new); \
2037 __BUILD_SET_C0(status)
2038 __BUILD_SET_C0(cause)
2039 __BUILD_SET_C0(config)
2040 __BUILD_SET_C0(config5)
2041 __BUILD_SET_C0(intcontrol)
2042 __BUILD_SET_C0(intctl)
2043 __BUILD_SET_C0(srsmap)
2044 __BUILD_SET_C0(pagegrain)
2045 __BUILD_SET_C0(brcm_config_0)
2046 __BUILD_SET_C0(brcm_bus_pll)
2047 __BUILD_SET_C0(brcm_reset)
2048 __BUILD_SET_C0(brcm_cmt_intr)
2049 __BUILD_SET_C0(brcm_cmt_ctrl)
2050 __BUILD_SET_C0(brcm_config)
2051 __BUILD_SET_C0(brcm_mode)
2054 * Return low 10 bits of ebase.
2055 * Note that under KVM (MIPSVZ) this returns vcpu id.
2057 static inline unsigned int get_ebase_cpunum(void)
2059 return read_c0_ebase() & 0x3ff;
2062 #endif /* !__ASSEMBLY__ */
2064 #endif /* _ASM_MIPSREGS_H */