2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7 * Authors: Sanjay Lal <sanjayl@kymasys.com>
10 #ifndef __MIPS_KVM_HOST_H__
11 #define __MIPS_KVM_HOST_H__
13 #include <linux/mutex.h>
14 #include <linux/hrtimer.h>
15 #include <linux/interrupt.h>
16 #include <linux/types.h>
17 #include <linux/kvm.h>
18 #include <linux/kvm_types.h>
19 #include <linux/threads.h>
20 #include <linux/spinlock.h>
22 /* MIPS KVM register ids */
23 #define MIPS_CP0_32(_R, _S) \
24 (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U32 | (8 * (_R) + (_S)))
26 #define MIPS_CP0_64(_R, _S) \
27 (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S)))
29 #define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0)
30 #define KVM_REG_MIPS_CP0_ENTRYLO0 MIPS_CP0_64(2, 0)
31 #define KVM_REG_MIPS_CP0_ENTRYLO1 MIPS_CP0_64(3, 0)
32 #define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0)
33 #define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2)
34 #define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0)
35 #define KVM_REG_MIPS_CP0_PAGEGRAIN MIPS_CP0_32(5, 1)
36 #define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0)
37 #define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0)
38 #define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0)
39 #define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0)
40 #define KVM_REG_MIPS_CP0_ENTRYHI MIPS_CP0_64(10, 0)
41 #define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0)
42 #define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0)
43 #define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0)
44 #define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0)
45 #define KVM_REG_MIPS_CP0_PRID MIPS_CP0_32(15, 0)
46 #define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_64(15, 1)
47 #define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0)
48 #define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1)
49 #define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2)
50 #define KVM_REG_MIPS_CP0_CONFIG3 MIPS_CP0_32(16, 3)
51 #define KVM_REG_MIPS_CP0_CONFIG4 MIPS_CP0_32(16, 4)
52 #define KVM_REG_MIPS_CP0_CONFIG5 MIPS_CP0_32(16, 5)
53 #define KVM_REG_MIPS_CP0_CONFIG7 MIPS_CP0_32(16, 7)
54 #define KVM_REG_MIPS_CP0_XCONTEXT MIPS_CP0_64(20, 0)
55 #define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0)
58 #define KVM_MAX_VCPUS 1
59 #define KVM_USER_MEM_SLOTS 8
60 /* memory slots that does not exposed to userspace */
61 #define KVM_PRIVATE_MEM_SLOTS 0
63 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
64 #define KVM_HALT_POLL_NS_DEFAULT 500000
68 /* Special address that contains the comm page, used for reducing # of traps */
69 #define KVM_GUEST_COMMPAGE_ADDR 0x0
71 #define KVM_GUEST_KERNEL_MODE(vcpu) ((kvm_read_c0_guest_status(vcpu->arch.cop0) & (ST0_EXL | ST0_ERL)) || \
72 ((kvm_read_c0_guest_status(vcpu->arch.cop0) & KSU_USER) == 0))
74 #define KVM_GUEST_KUSEG 0x00000000UL
75 #define KVM_GUEST_KSEG0 0x40000000UL
76 #define KVM_GUEST_KSEG23 0x60000000UL
77 #define KVM_GUEST_KSEGX(a) ((_ACAST32_(a)) & 0x60000000)
78 #define KVM_GUEST_CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
80 #define KVM_GUEST_CKSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
81 #define KVM_GUEST_CKSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
82 #define KVM_GUEST_CKSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
85 * Map an address to a certain kernel segment
87 #define KVM_GUEST_KSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
88 #define KVM_GUEST_KSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
89 #define KVM_GUEST_KSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
91 #define KVM_INVALID_PAGE 0xdeadbeef
92 #define KVM_INVALID_INST 0xdeadbeef
93 #define KVM_INVALID_ADDR 0xdeadbeef
96 #define CAUSEF_DC (_ULCAST_(1) << 27)
98 extern atomic_t kvm_mips_instance;
99 extern pfn_t(*kvm_mips_gfn_to_pfn) (struct kvm *kvm, gfn_t gfn);
100 extern void (*kvm_mips_release_pfn_clean) (pfn_t pfn);
101 extern bool(*kvm_mips_is_error_pfn) (pfn_t pfn);
104 u32 remote_tlb_flush;
107 struct kvm_vcpu_stat {
112 u32 cop_unusable_exits;
114 u32 tlbmiss_ld_exits;
115 u32 tlbmiss_st_exits;
116 u32 addrerr_st_exits;
117 u32 addrerr_ld_exits;
119 u32 resvd_inst_exits;
120 u32 break_inst_exits;
124 u32 msa_disabled_exits;
125 u32 flush_dcache_exits;
126 u32 halt_successful_poll;
127 u32 halt_attempted_poll;
131 enum kvm_mips_exit_types {
150 MAX_KVM_MIPS_EXIT_TYPES
153 struct kvm_arch_memory_slot {
157 /* Guest GVA->HPA page table */
158 unsigned long *guest_pmap;
159 unsigned long guest_pmap_npages;
161 /* Wired host TLB used for the commpage */
165 #define N_MIPS_COPROC_REGS 32
166 #define N_MIPS_COPROC_SEL 8
169 unsigned long reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
170 #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
171 unsigned long stat[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
176 * Coprocessor 0 register names
178 #define MIPS_CP0_TLB_INDEX 0
179 #define MIPS_CP0_TLB_RANDOM 1
180 #define MIPS_CP0_TLB_LOW 2
181 #define MIPS_CP0_TLB_LO0 2
182 #define MIPS_CP0_TLB_LO1 3
183 #define MIPS_CP0_TLB_CONTEXT 4
184 #define MIPS_CP0_TLB_PG_MASK 5
185 #define MIPS_CP0_TLB_WIRED 6
186 #define MIPS_CP0_HWRENA 7
187 #define MIPS_CP0_BAD_VADDR 8
188 #define MIPS_CP0_COUNT 9
189 #define MIPS_CP0_TLB_HI 10
190 #define MIPS_CP0_COMPARE 11
191 #define MIPS_CP0_STATUS 12
192 #define MIPS_CP0_CAUSE 13
193 #define MIPS_CP0_EXC_PC 14
194 #define MIPS_CP0_PRID 15
195 #define MIPS_CP0_CONFIG 16
196 #define MIPS_CP0_LLADDR 17
197 #define MIPS_CP0_WATCH_LO 18
198 #define MIPS_CP0_WATCH_HI 19
199 #define MIPS_CP0_TLB_XCONTEXT 20
200 #define MIPS_CP0_ECC 26
201 #define MIPS_CP0_CACHE_ERR 27
202 #define MIPS_CP0_TAG_LO 28
203 #define MIPS_CP0_TAG_HI 29
204 #define MIPS_CP0_ERROR_PC 30
205 #define MIPS_CP0_DEBUG 23
206 #define MIPS_CP0_DEPC 24
207 #define MIPS_CP0_PERFCNT 25
208 #define MIPS_CP0_ERRCTL 26
209 #define MIPS_CP0_DATA_LO 28
210 #define MIPS_CP0_DATA_HI 29
211 #define MIPS_CP0_DESAVE 31
213 #define MIPS_CP0_CONFIG_SEL 0
214 #define MIPS_CP0_CONFIG1_SEL 1
215 #define MIPS_CP0_CONFIG2_SEL 2
216 #define MIPS_CP0_CONFIG3_SEL 3
217 #define MIPS_CP0_CONFIG4_SEL 4
218 #define MIPS_CP0_CONFIG5_SEL 5
220 /* Config0 register bits */
234 /* Config1 register bits */
251 /* Config2 Register bits */
262 /* Config3 Register bits */
264 #define CP0C3_ISA_ON_EXC 16
265 #define CP0C3_ULRI 13
266 #define CP0C3_DSPP 10
275 /* MMU types, the first four entries have the same layout as the
277 enum mips_mmu_types {
290 #define T_INT 0 /* Interrupt pending */
291 #define T_TLB_MOD 1 /* TLB modified fault */
292 #define T_TLB_LD_MISS 2 /* TLB miss on load or ifetch */
293 #define T_TLB_ST_MISS 3 /* TLB miss on a store */
294 #define T_ADDR_ERR_LD 4 /* Address error on a load or ifetch */
295 #define T_ADDR_ERR_ST 5 /* Address error on a store */
296 #define T_BUS_ERR_IFETCH 6 /* Bus error on an ifetch */
297 #define T_BUS_ERR_LD_ST 7 /* Bus error on a load or store */
298 #define T_SYSCALL 8 /* System call */
299 #define T_BREAK 9 /* Breakpoint */
300 #define T_RES_INST 10 /* Reserved instruction exception */
301 #define T_COP_UNUSABLE 11 /* Coprocessor unusable */
302 #define T_OVFLOW 12 /* Arithmetic overflow */
305 * Trap definitions added for r4000 port.
307 #define T_TRAP 13 /* Trap instruction */
308 #define T_VCEI 14 /* Virtual coherency exception */
309 #define T_MSAFPE 14 /* MSA floating point exception */
310 #define T_FPE 15 /* Floating point exception */
311 #define T_MSADIS 21 /* MSA disabled exception */
312 #define T_WATCH 23 /* Watch address reference */
313 #define T_VCED 31 /* Virtual coherency data */
316 #define RESUME_FLAG_DR (1<<0) /* Reload guest nonvolatile state? */
317 #define RESUME_FLAG_HOST (1<<1) /* Resume host? */
319 #define RESUME_GUEST 0
320 #define RESUME_GUEST_DR RESUME_FLAG_DR
321 #define RESUME_HOST RESUME_FLAG_HOST
323 enum emulation_result {
324 EMULATE_DONE, /* no further processing */
325 EMULATE_DO_MMIO, /* kvm_run filled with MMIO request */
326 EMULATE_FAIL, /* can't emulate this instruction */
327 EMULATE_WAIT, /* WAIT instruction */
331 #define MIPS3_PG_G 0x00000001 /* Global; ignore ASID if in lo0 & lo1 */
332 #define MIPS3_PG_V 0x00000002 /* Valid */
333 #define MIPS3_PG_NV 0x00000000
334 #define MIPS3_PG_D 0x00000004 /* Dirty */
336 #define mips3_paddr_to_tlbpfn(x) \
337 (((unsigned long)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME)
338 #define mips3_tlbpfn_to_paddr(x) \
339 ((unsigned long)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT)
341 #define MIPS3_PG_SHIFT 6
342 #define MIPS3_PG_FRAME 0x3fffffc0
344 #define VPN2_MASK 0xffffe000
345 #define TLB_IS_GLOBAL(x) (((x).tlb_lo0 & MIPS3_PG_G) && \
346 ((x).tlb_lo1 & MIPS3_PG_G))
347 #define TLB_VPN2(x) ((x).tlb_hi & VPN2_MASK)
348 #define TLB_ASID(x) ((x).tlb_hi & ASID_MASK)
349 #define TLB_IS_VALID(x, va) (((va) & (1 << PAGE_SHIFT)) \
350 ? ((x).tlb_lo1 & MIPS3_PG_V) \
351 : ((x).tlb_lo0 & MIPS3_PG_V))
352 #define TLB_HI_VPN2_HIT(x, y) ((TLB_VPN2(x) & ~(x).tlb_mask) == \
353 ((y) & VPN2_MASK & ~(x).tlb_mask))
354 #define TLB_HI_ASID_HIT(x, y) (TLB_IS_GLOBAL(x) || \
355 TLB_ASID(x) == ((y) & ASID_MASK))
357 struct kvm_mips_tlb {
364 #define KVM_MIPS_FPU_FPU 0x1
365 #define KVM_MIPS_FPU_MSA 0x2
367 #define KVM_MIPS_GUEST_TLB_SIZE 64
368 struct kvm_vcpu_arch {
369 void *host_ebase, *guest_ebase;
370 unsigned long host_stack;
371 unsigned long host_gp;
373 /* Host CP0 registers used when handling exits from guest */
374 unsigned long host_cp0_badvaddr;
375 unsigned long host_cp0_cause;
376 unsigned long host_cp0_epc;
377 unsigned long host_cp0_entryhi;
381 unsigned long gprs[32];
387 struct mips_fpu_struct fpu;
388 /* Which FPU state is loaded (KVM_MIPS_FPU_*) */
389 unsigned int fpu_inuse;
392 struct mips_coproc *cop0;
394 /* Host KSEG0 address of the EI/DI offset */
395 void *kseg0_commpage;
397 u32 io_gpr; /* GPR used as IO source/target */
399 struct hrtimer comparecount_timer;
400 /* Count timer control KVM register */
402 /* Count bias from the raw time */
404 /* Frequency of timer in Hz */
406 /* Dynamic nanosecond bias (multiple of count_period) to avoid overflow */
409 ktime_t count_resume;
410 /* Period of timer tick in ns */
413 /* Bitmask of exceptions that are pending */
414 unsigned long pending_exceptions;
416 /* Bitmask of pending exceptions to be cleared */
417 unsigned long pending_exceptions_clr;
419 unsigned long pending_load_cause;
421 /* Save/Restore the entryhi register when are are preempted/scheduled back in */
422 unsigned long preempt_entryhi;
424 /* S/W Based TLB for guest */
425 struct kvm_mips_tlb guest_tlb[KVM_MIPS_GUEST_TLB_SIZE];
427 /* Cached guest kernel/user ASIDs */
428 uint32_t guest_user_asid[NR_CPUS];
429 uint32_t guest_kernel_asid[NR_CPUS];
430 struct mm_struct guest_kernel_mm, guest_user_mm;
442 #define kvm_read_c0_guest_index(cop0) (cop0->reg[MIPS_CP0_TLB_INDEX][0])
443 #define kvm_write_c0_guest_index(cop0, val) (cop0->reg[MIPS_CP0_TLB_INDEX][0] = val)
444 #define kvm_read_c0_guest_entrylo0(cop0) (cop0->reg[MIPS_CP0_TLB_LO0][0])
445 #define kvm_read_c0_guest_entrylo1(cop0) (cop0->reg[MIPS_CP0_TLB_LO1][0])
446 #define kvm_read_c0_guest_context(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0])
447 #define kvm_write_c0_guest_context(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0] = (val))
448 #define kvm_read_c0_guest_userlocal(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2])
449 #define kvm_write_c0_guest_userlocal(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2] = (val))
450 #define kvm_read_c0_guest_pagemask(cop0) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0])
451 #define kvm_write_c0_guest_pagemask(cop0, val) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0] = (val))
452 #define kvm_read_c0_guest_wired(cop0) (cop0->reg[MIPS_CP0_TLB_WIRED][0])
453 #define kvm_write_c0_guest_wired(cop0, val) (cop0->reg[MIPS_CP0_TLB_WIRED][0] = (val))
454 #define kvm_read_c0_guest_hwrena(cop0) (cop0->reg[MIPS_CP0_HWRENA][0])
455 #define kvm_write_c0_guest_hwrena(cop0, val) (cop0->reg[MIPS_CP0_HWRENA][0] = (val))
456 #define kvm_read_c0_guest_badvaddr(cop0) (cop0->reg[MIPS_CP0_BAD_VADDR][0])
457 #define kvm_write_c0_guest_badvaddr(cop0, val) (cop0->reg[MIPS_CP0_BAD_VADDR][0] = (val))
458 #define kvm_read_c0_guest_count(cop0) (cop0->reg[MIPS_CP0_COUNT][0])
459 #define kvm_write_c0_guest_count(cop0, val) (cop0->reg[MIPS_CP0_COUNT][0] = (val))
460 #define kvm_read_c0_guest_entryhi(cop0) (cop0->reg[MIPS_CP0_TLB_HI][0])
461 #define kvm_write_c0_guest_entryhi(cop0, val) (cop0->reg[MIPS_CP0_TLB_HI][0] = (val))
462 #define kvm_read_c0_guest_compare(cop0) (cop0->reg[MIPS_CP0_COMPARE][0])
463 #define kvm_write_c0_guest_compare(cop0, val) (cop0->reg[MIPS_CP0_COMPARE][0] = (val))
464 #define kvm_read_c0_guest_status(cop0) (cop0->reg[MIPS_CP0_STATUS][0])
465 #define kvm_write_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] = (val))
466 #define kvm_read_c0_guest_intctl(cop0) (cop0->reg[MIPS_CP0_STATUS][1])
467 #define kvm_write_c0_guest_intctl(cop0, val) (cop0->reg[MIPS_CP0_STATUS][1] = (val))
468 #define kvm_read_c0_guest_cause(cop0) (cop0->reg[MIPS_CP0_CAUSE][0])
469 #define kvm_write_c0_guest_cause(cop0, val) (cop0->reg[MIPS_CP0_CAUSE][0] = (val))
470 #define kvm_read_c0_guest_epc(cop0) (cop0->reg[MIPS_CP0_EXC_PC][0])
471 #define kvm_write_c0_guest_epc(cop0, val) (cop0->reg[MIPS_CP0_EXC_PC][0] = (val))
472 #define kvm_read_c0_guest_prid(cop0) (cop0->reg[MIPS_CP0_PRID][0])
473 #define kvm_write_c0_guest_prid(cop0, val) (cop0->reg[MIPS_CP0_PRID][0] = (val))
474 #define kvm_read_c0_guest_ebase(cop0) (cop0->reg[MIPS_CP0_PRID][1])
475 #define kvm_write_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] = (val))
476 #define kvm_read_c0_guest_config(cop0) (cop0->reg[MIPS_CP0_CONFIG][0])
477 #define kvm_read_c0_guest_config1(cop0) (cop0->reg[MIPS_CP0_CONFIG][1])
478 #define kvm_read_c0_guest_config2(cop0) (cop0->reg[MIPS_CP0_CONFIG][2])
479 #define kvm_read_c0_guest_config3(cop0) (cop0->reg[MIPS_CP0_CONFIG][3])
480 #define kvm_read_c0_guest_config4(cop0) (cop0->reg[MIPS_CP0_CONFIG][4])
481 #define kvm_read_c0_guest_config5(cop0) (cop0->reg[MIPS_CP0_CONFIG][5])
482 #define kvm_read_c0_guest_config7(cop0) (cop0->reg[MIPS_CP0_CONFIG][7])
483 #define kvm_write_c0_guest_config(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][0] = (val))
484 #define kvm_write_c0_guest_config1(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][1] = (val))
485 #define kvm_write_c0_guest_config2(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][2] = (val))
486 #define kvm_write_c0_guest_config3(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][3] = (val))
487 #define kvm_write_c0_guest_config4(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][4] = (val))
488 #define kvm_write_c0_guest_config5(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][5] = (val))
489 #define kvm_write_c0_guest_config7(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][7] = (val))
490 #define kvm_read_c0_guest_errorepc(cop0) (cop0->reg[MIPS_CP0_ERROR_PC][0])
491 #define kvm_write_c0_guest_errorepc(cop0, val) (cop0->reg[MIPS_CP0_ERROR_PC][0] = (val))
494 * Some of the guest registers may be modified asynchronously (e.g. from a
495 * hrtimer callback in hard irq context) and therefore need stronger atomicity
496 * guarantees than other registers.
499 static inline void _kvm_atomic_set_c0_guest_reg(unsigned long *reg,
504 __asm__ __volatile__(
510 : "=&r" (temp), "+m" (*reg)
512 } while (unlikely(!temp));
515 static inline void _kvm_atomic_clear_c0_guest_reg(unsigned long *reg,
520 __asm__ __volatile__(
526 : "=&r" (temp), "+m" (*reg)
528 } while (unlikely(!temp));
531 static inline void _kvm_atomic_change_c0_guest_reg(unsigned long *reg,
532 unsigned long change,
537 __asm__ __volatile__(
544 : "=&r" (temp), "+m" (*reg)
545 : "r" (~change), "r" (val & change));
546 } while (unlikely(!temp));
549 #define kvm_set_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] |= (val))
550 #define kvm_clear_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] &= ~(val))
552 /* Cause can be modified asynchronously from hardirq hrtimer callback */
553 #define kvm_set_c0_guest_cause(cop0, val) \
554 _kvm_atomic_set_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val)
555 #define kvm_clear_c0_guest_cause(cop0, val) \
556 _kvm_atomic_clear_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val)
557 #define kvm_change_c0_guest_cause(cop0, change, val) \
558 _kvm_atomic_change_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], \
561 #define kvm_set_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] |= (val))
562 #define kvm_clear_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] &= ~(val))
563 #define kvm_change_c0_guest_ebase(cop0, change, val) \
565 kvm_clear_c0_guest_ebase(cop0, change); \
566 kvm_set_c0_guest_ebase(cop0, ((val) & (change))); \
571 static inline bool kvm_mips_guest_can_have_fpu(struct kvm_vcpu_arch *vcpu)
573 return (!__builtin_constant_p(cpu_has_fpu) || cpu_has_fpu) &&
577 static inline bool kvm_mips_guest_has_fpu(struct kvm_vcpu_arch *vcpu)
579 return kvm_mips_guest_can_have_fpu(vcpu) &&
580 kvm_read_c0_guest_config1(vcpu->cop0) & MIPS_CONF1_FP;
583 static inline bool kvm_mips_guest_can_have_msa(struct kvm_vcpu_arch *vcpu)
585 return (!__builtin_constant_p(cpu_has_msa) || cpu_has_msa) &&
589 static inline bool kvm_mips_guest_has_msa(struct kvm_vcpu_arch *vcpu)
591 return kvm_mips_guest_can_have_msa(vcpu) &&
592 kvm_read_c0_guest_config3(vcpu->cop0) & MIPS_CONF3_MSA;
595 struct kvm_mips_callbacks {
596 int (*handle_cop_unusable)(struct kvm_vcpu *vcpu);
597 int (*handle_tlb_mod)(struct kvm_vcpu *vcpu);
598 int (*handle_tlb_ld_miss)(struct kvm_vcpu *vcpu);
599 int (*handle_tlb_st_miss)(struct kvm_vcpu *vcpu);
600 int (*handle_addr_err_st)(struct kvm_vcpu *vcpu);
601 int (*handle_addr_err_ld)(struct kvm_vcpu *vcpu);
602 int (*handle_syscall)(struct kvm_vcpu *vcpu);
603 int (*handle_res_inst)(struct kvm_vcpu *vcpu);
604 int (*handle_break)(struct kvm_vcpu *vcpu);
605 int (*handle_trap)(struct kvm_vcpu *vcpu);
606 int (*handle_msa_fpe)(struct kvm_vcpu *vcpu);
607 int (*handle_fpe)(struct kvm_vcpu *vcpu);
608 int (*handle_msa_disabled)(struct kvm_vcpu *vcpu);
609 int (*vm_init)(struct kvm *kvm);
610 int (*vcpu_init)(struct kvm_vcpu *vcpu);
611 int (*vcpu_setup)(struct kvm_vcpu *vcpu);
612 gpa_t (*gva_to_gpa)(gva_t gva);
613 void (*queue_timer_int)(struct kvm_vcpu *vcpu);
614 void (*dequeue_timer_int)(struct kvm_vcpu *vcpu);
615 void (*queue_io_int)(struct kvm_vcpu *vcpu,
616 struct kvm_mips_interrupt *irq);
617 void (*dequeue_io_int)(struct kvm_vcpu *vcpu,
618 struct kvm_mips_interrupt *irq);
619 int (*irq_deliver)(struct kvm_vcpu *vcpu, unsigned int priority,
621 int (*irq_clear)(struct kvm_vcpu *vcpu, unsigned int priority,
623 int (*get_one_reg)(struct kvm_vcpu *vcpu,
624 const struct kvm_one_reg *reg, s64 *v);
625 int (*set_one_reg)(struct kvm_vcpu *vcpu,
626 const struct kvm_one_reg *reg, s64 v);
627 int (*vcpu_get_regs)(struct kvm_vcpu *vcpu);
628 int (*vcpu_set_regs)(struct kvm_vcpu *vcpu);
630 extern struct kvm_mips_callbacks *kvm_mips_callbacks;
631 int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks);
633 /* Debug: dump vcpu state */
634 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu);
636 /* Trampoline ASM routine to start running in "Guest" context */
637 extern int __kvm_mips_vcpu_run(struct kvm_run *run, struct kvm_vcpu *vcpu);
639 /* FPU/MSA context management */
640 void __kvm_save_fpu(struct kvm_vcpu_arch *vcpu);
641 void __kvm_restore_fpu(struct kvm_vcpu_arch *vcpu);
642 void __kvm_restore_fcsr(struct kvm_vcpu_arch *vcpu);
643 void __kvm_save_msa(struct kvm_vcpu_arch *vcpu);
644 void __kvm_restore_msa(struct kvm_vcpu_arch *vcpu);
645 void __kvm_restore_msa_upper(struct kvm_vcpu_arch *vcpu);
646 void __kvm_restore_msacsr(struct kvm_vcpu_arch *vcpu);
647 void kvm_own_fpu(struct kvm_vcpu *vcpu);
648 void kvm_own_msa(struct kvm_vcpu *vcpu);
649 void kvm_drop_fpu(struct kvm_vcpu *vcpu);
650 void kvm_lose_fpu(struct kvm_vcpu *vcpu);
653 uint32_t kvm_get_kernel_asid(struct kvm_vcpu *vcpu);
655 uint32_t kvm_get_user_asid(struct kvm_vcpu *vcpu);
657 uint32_t kvm_get_commpage_asid (struct kvm_vcpu *vcpu);
659 extern int kvm_mips_handle_kseg0_tlb_fault(unsigned long badbaddr,
660 struct kvm_vcpu *vcpu);
662 extern int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr,
663 struct kvm_vcpu *vcpu);
665 extern int kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu *vcpu,
666 struct kvm_mips_tlb *tlb,
668 unsigned long *hpa1);
670 extern enum emulation_result kvm_mips_handle_tlbmiss(unsigned long cause,
673 struct kvm_vcpu *vcpu);
675 extern enum emulation_result kvm_mips_handle_tlbmod(unsigned long cause,
678 struct kvm_vcpu *vcpu);
680 extern void kvm_mips_dump_host_tlbs(void);
681 extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu);
682 extern void kvm_mips_flush_host_tlb(int skip_kseg0);
683 extern int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi);
684 extern int kvm_mips_host_tlb_inv_index(struct kvm_vcpu *vcpu, int index);
686 extern int kvm_mips_guest_tlb_lookup(struct kvm_vcpu *vcpu,
687 unsigned long entryhi);
688 extern int kvm_mips_host_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long vaddr);
689 extern unsigned long kvm_mips_translate_guest_kseg0_to_hpa(struct kvm_vcpu *vcpu,
691 extern void kvm_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu,
692 struct kvm_vcpu *vcpu);
693 extern void kvm_local_flush_tlb_all(void);
694 extern void kvm_mips_alloc_new_mmu_context(struct kvm_vcpu *vcpu);
695 extern void kvm_mips_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
696 extern void kvm_mips_vcpu_put(struct kvm_vcpu *vcpu);
699 uint32_t kvm_get_inst(uint32_t *opc, struct kvm_vcpu *vcpu);
700 enum emulation_result update_pc(struct kvm_vcpu *vcpu, uint32_t cause);
702 extern enum emulation_result kvm_mips_emulate_inst(unsigned long cause,
705 struct kvm_vcpu *vcpu);
707 extern enum emulation_result kvm_mips_emulate_syscall(unsigned long cause,
710 struct kvm_vcpu *vcpu);
712 extern enum emulation_result kvm_mips_emulate_tlbmiss_ld(unsigned long cause,
715 struct kvm_vcpu *vcpu);
717 extern enum emulation_result kvm_mips_emulate_tlbinv_ld(unsigned long cause,
720 struct kvm_vcpu *vcpu);
722 extern enum emulation_result kvm_mips_emulate_tlbmiss_st(unsigned long cause,
725 struct kvm_vcpu *vcpu);
727 extern enum emulation_result kvm_mips_emulate_tlbinv_st(unsigned long cause,
730 struct kvm_vcpu *vcpu);
732 extern enum emulation_result kvm_mips_emulate_tlbmod(unsigned long cause,
735 struct kvm_vcpu *vcpu);
737 extern enum emulation_result kvm_mips_emulate_fpu_exc(unsigned long cause,
740 struct kvm_vcpu *vcpu);
742 extern enum emulation_result kvm_mips_handle_ri(unsigned long cause,
745 struct kvm_vcpu *vcpu);
747 extern enum emulation_result kvm_mips_emulate_ri_exc(unsigned long cause,
750 struct kvm_vcpu *vcpu);
752 extern enum emulation_result kvm_mips_emulate_bp_exc(unsigned long cause,
755 struct kvm_vcpu *vcpu);
757 extern enum emulation_result kvm_mips_emulate_trap_exc(unsigned long cause,
760 struct kvm_vcpu *vcpu);
762 extern enum emulation_result kvm_mips_emulate_msafpe_exc(unsigned long cause,
765 struct kvm_vcpu *vcpu);
767 extern enum emulation_result kvm_mips_emulate_fpe_exc(unsigned long cause,
770 struct kvm_vcpu *vcpu);
772 extern enum emulation_result kvm_mips_emulate_msadis_exc(unsigned long cause,
775 struct kvm_vcpu *vcpu);
777 extern enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu,
778 struct kvm_run *run);
780 uint32_t kvm_mips_read_count(struct kvm_vcpu *vcpu);
781 void kvm_mips_write_count(struct kvm_vcpu *vcpu, uint32_t count);
782 void kvm_mips_write_compare(struct kvm_vcpu *vcpu, uint32_t compare);
783 void kvm_mips_init_count(struct kvm_vcpu *vcpu);
784 int kvm_mips_set_count_ctl(struct kvm_vcpu *vcpu, s64 count_ctl);
785 int kvm_mips_set_count_resume(struct kvm_vcpu *vcpu, s64 count_resume);
786 int kvm_mips_set_count_hz(struct kvm_vcpu *vcpu, s64 count_hz);
787 void kvm_mips_count_enable_cause(struct kvm_vcpu *vcpu);
788 void kvm_mips_count_disable_cause(struct kvm_vcpu *vcpu);
789 enum hrtimer_restart kvm_mips_count_timeout(struct kvm_vcpu *vcpu);
791 enum emulation_result kvm_mips_check_privilege(unsigned long cause,
794 struct kvm_vcpu *vcpu);
796 enum emulation_result kvm_mips_emulate_cache(uint32_t inst,
800 struct kvm_vcpu *vcpu);
801 enum emulation_result kvm_mips_emulate_CP0(uint32_t inst,
805 struct kvm_vcpu *vcpu);
806 enum emulation_result kvm_mips_emulate_store(uint32_t inst,
809 struct kvm_vcpu *vcpu);
810 enum emulation_result kvm_mips_emulate_load(uint32_t inst,
813 struct kvm_vcpu *vcpu);
815 unsigned int kvm_mips_config1_wrmask(struct kvm_vcpu *vcpu);
816 unsigned int kvm_mips_config3_wrmask(struct kvm_vcpu *vcpu);
817 unsigned int kvm_mips_config4_wrmask(struct kvm_vcpu *vcpu);
818 unsigned int kvm_mips_config5_wrmask(struct kvm_vcpu *vcpu);
820 /* Dynamic binary translation */
821 extern int kvm_mips_trans_cache_index(uint32_t inst, uint32_t *opc,
822 struct kvm_vcpu *vcpu);
823 extern int kvm_mips_trans_cache_va(uint32_t inst, uint32_t *opc,
824 struct kvm_vcpu *vcpu);
825 extern int kvm_mips_trans_mfc0(uint32_t inst, uint32_t *opc,
826 struct kvm_vcpu *vcpu);
827 extern int kvm_mips_trans_mtc0(uint32_t inst, uint32_t *opc,
828 struct kvm_vcpu *vcpu);
831 extern void kvm_mips_dump_stats(struct kvm_vcpu *vcpu);
832 extern unsigned long kvm_mips_get_ramsize(struct kvm *kvm);
834 static inline void kvm_arch_hardware_disable(void) {}
835 static inline void kvm_arch_hardware_unsetup(void) {}
836 static inline void kvm_arch_sync_events(struct kvm *kvm) {}
837 static inline void kvm_arch_free_memslot(struct kvm *kvm,
838 struct kvm_memory_slot *free, struct kvm_memory_slot *dont) {}
839 static inline void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots) {}
840 static inline void kvm_arch_flush_shadow_all(struct kvm *kvm) {}
841 static inline void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
842 struct kvm_memory_slot *slot) {}
843 static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {}
844 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
845 static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) {}
846 static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) {}
848 #endif /* __MIPS_KVM_HOST_H__ */