2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7 * Authors: Sanjay Lal <sanjayl@kymasys.com>
10 #ifndef __MIPS_KVM_HOST_H__
11 #define __MIPS_KVM_HOST_H__
13 #include <linux/mutex.h>
14 #include <linux/hrtimer.h>
15 #include <linux/interrupt.h>
16 #include <linux/types.h>
17 #include <linux/kvm.h>
18 #include <linux/kvm_types.h>
19 #include <linux/threads.h>
20 #include <linux/spinlock.h>
22 /* MIPS KVM register ids */
23 #define MIPS_CP0_32(_R, _S) \
24 (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U32 | (8 * (_R) + (_S)))
26 #define MIPS_CP0_64(_R, _S) \
27 (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S)))
29 #define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0)
30 #define KVM_REG_MIPS_CP0_ENTRYLO0 MIPS_CP0_64(2, 0)
31 #define KVM_REG_MIPS_CP0_ENTRYLO1 MIPS_CP0_64(3, 0)
32 #define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0)
33 #define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2)
34 #define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0)
35 #define KVM_REG_MIPS_CP0_PAGEGRAIN MIPS_CP0_32(5, 1)
36 #define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0)
37 #define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0)
38 #define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0)
39 #define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0)
40 #define KVM_REG_MIPS_CP0_ENTRYHI MIPS_CP0_64(10, 0)
41 #define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0)
42 #define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0)
43 #define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0)
44 #define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0)
45 #define KVM_REG_MIPS_CP0_PRID MIPS_CP0_32(15, 0)
46 #define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_64(15, 1)
47 #define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0)
48 #define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1)
49 #define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2)
50 #define KVM_REG_MIPS_CP0_CONFIG3 MIPS_CP0_32(16, 3)
51 #define KVM_REG_MIPS_CP0_CONFIG4 MIPS_CP0_32(16, 4)
52 #define KVM_REG_MIPS_CP0_CONFIG5 MIPS_CP0_32(16, 5)
53 #define KVM_REG_MIPS_CP0_CONFIG7 MIPS_CP0_32(16, 7)
54 #define KVM_REG_MIPS_CP0_XCONTEXT MIPS_CP0_64(20, 0)
55 #define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0)
58 #define KVM_MAX_VCPUS 1
59 #define KVM_USER_MEM_SLOTS 8
60 /* memory slots that does not exposed to userspace */
61 #define KVM_PRIVATE_MEM_SLOTS 0
63 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
64 #define KVM_HALT_POLL_NS_DEFAULT 500000
68 /* Special address that contains the comm page, used for reducing # of traps */
69 #define KVM_GUEST_COMMPAGE_ADDR 0x0
71 #define KVM_GUEST_KERNEL_MODE(vcpu) ((kvm_read_c0_guest_status(vcpu->arch.cop0) & (ST0_EXL | ST0_ERL)) || \
72 ((kvm_read_c0_guest_status(vcpu->arch.cop0) & KSU_USER) == 0))
74 #define KVM_GUEST_KUSEG 0x00000000UL
75 #define KVM_GUEST_KSEG0 0x40000000UL
76 #define KVM_GUEST_KSEG23 0x60000000UL
77 #define KVM_GUEST_KSEGX(a) ((_ACAST32_(a)) & 0x60000000)
78 #define KVM_GUEST_CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
80 #define KVM_GUEST_CKSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
81 #define KVM_GUEST_CKSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
82 #define KVM_GUEST_CKSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
85 * Map an address to a certain kernel segment
87 #define KVM_GUEST_KSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
88 #define KVM_GUEST_KSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
89 #define KVM_GUEST_KSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
91 #define KVM_INVALID_PAGE 0xdeadbeef
92 #define KVM_INVALID_INST 0xdeadbeef
93 #define KVM_INVALID_ADDR 0xdeadbeef
95 extern atomic_t kvm_mips_instance;
96 extern pfn_t(*kvm_mips_gfn_to_pfn) (struct kvm *kvm, gfn_t gfn);
97 extern void (*kvm_mips_release_pfn_clean) (pfn_t pfn);
98 extern bool(*kvm_mips_is_error_pfn) (pfn_t pfn);
101 u32 remote_tlb_flush;
104 struct kvm_vcpu_stat {
109 u32 cop_unusable_exits;
111 u32 tlbmiss_ld_exits;
112 u32 tlbmiss_st_exits;
113 u32 addrerr_st_exits;
114 u32 addrerr_ld_exits;
116 u32 resvd_inst_exits;
117 u32 break_inst_exits;
121 u32 msa_disabled_exits;
122 u32 flush_dcache_exits;
123 u32 halt_successful_poll;
124 u32 halt_attempted_poll;
128 enum kvm_mips_exit_types {
147 MAX_KVM_MIPS_EXIT_TYPES
150 struct kvm_arch_memory_slot {
154 /* Guest GVA->HPA page table */
155 unsigned long *guest_pmap;
156 unsigned long guest_pmap_npages;
158 /* Wired host TLB used for the commpage */
162 #define N_MIPS_COPROC_REGS 32
163 #define N_MIPS_COPROC_SEL 8
166 unsigned long reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
167 #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
168 unsigned long stat[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
173 * Coprocessor 0 register names
175 #define MIPS_CP0_TLB_INDEX 0
176 #define MIPS_CP0_TLB_RANDOM 1
177 #define MIPS_CP0_TLB_LOW 2
178 #define MIPS_CP0_TLB_LO0 2
179 #define MIPS_CP0_TLB_LO1 3
180 #define MIPS_CP0_TLB_CONTEXT 4
181 #define MIPS_CP0_TLB_PG_MASK 5
182 #define MIPS_CP0_TLB_WIRED 6
183 #define MIPS_CP0_HWRENA 7
184 #define MIPS_CP0_BAD_VADDR 8
185 #define MIPS_CP0_COUNT 9
186 #define MIPS_CP0_TLB_HI 10
187 #define MIPS_CP0_COMPARE 11
188 #define MIPS_CP0_STATUS 12
189 #define MIPS_CP0_CAUSE 13
190 #define MIPS_CP0_EXC_PC 14
191 #define MIPS_CP0_PRID 15
192 #define MIPS_CP0_CONFIG 16
193 #define MIPS_CP0_LLADDR 17
194 #define MIPS_CP0_WATCH_LO 18
195 #define MIPS_CP0_WATCH_HI 19
196 #define MIPS_CP0_TLB_XCONTEXT 20
197 #define MIPS_CP0_ECC 26
198 #define MIPS_CP0_CACHE_ERR 27
199 #define MIPS_CP0_TAG_LO 28
200 #define MIPS_CP0_TAG_HI 29
201 #define MIPS_CP0_ERROR_PC 30
202 #define MIPS_CP0_DEBUG 23
203 #define MIPS_CP0_DEPC 24
204 #define MIPS_CP0_PERFCNT 25
205 #define MIPS_CP0_ERRCTL 26
206 #define MIPS_CP0_DATA_LO 28
207 #define MIPS_CP0_DATA_HI 29
208 #define MIPS_CP0_DESAVE 31
210 #define MIPS_CP0_CONFIG_SEL 0
211 #define MIPS_CP0_CONFIG1_SEL 1
212 #define MIPS_CP0_CONFIG2_SEL 2
213 #define MIPS_CP0_CONFIG3_SEL 3
214 #define MIPS_CP0_CONFIG4_SEL 4
215 #define MIPS_CP0_CONFIG5_SEL 5
217 /* Config0 register bits */
231 /* Config1 register bits */
248 /* Config2 Register bits */
259 /* Config3 Register bits */
261 #define CP0C3_ISA_ON_EXC 16
262 #define CP0C3_ULRI 13
263 #define CP0C3_DSPP 10
272 /* MMU types, the first four entries have the same layout as the
274 enum mips_mmu_types {
287 #define T_INT 0 /* Interrupt pending */
288 #define T_TLB_MOD 1 /* TLB modified fault */
289 #define T_TLB_LD_MISS 2 /* TLB miss on load or ifetch */
290 #define T_TLB_ST_MISS 3 /* TLB miss on a store */
291 #define T_ADDR_ERR_LD 4 /* Address error on a load or ifetch */
292 #define T_ADDR_ERR_ST 5 /* Address error on a store */
293 #define T_BUS_ERR_IFETCH 6 /* Bus error on an ifetch */
294 #define T_BUS_ERR_LD_ST 7 /* Bus error on a load or store */
295 #define T_SYSCALL 8 /* System call */
296 #define T_BREAK 9 /* Breakpoint */
297 #define T_RES_INST 10 /* Reserved instruction exception */
298 #define T_COP_UNUSABLE 11 /* Coprocessor unusable */
299 #define T_OVFLOW 12 /* Arithmetic overflow */
302 * Trap definitions added for r4000 port.
304 #define T_TRAP 13 /* Trap instruction */
305 #define T_VCEI 14 /* Virtual coherency exception */
306 #define T_MSAFPE 14 /* MSA floating point exception */
307 #define T_FPE 15 /* Floating point exception */
308 #define T_MSADIS 21 /* MSA disabled exception */
309 #define T_WATCH 23 /* Watch address reference */
310 #define T_VCED 31 /* Virtual coherency data */
313 #define RESUME_FLAG_DR (1<<0) /* Reload guest nonvolatile state? */
314 #define RESUME_FLAG_HOST (1<<1) /* Resume host? */
316 #define RESUME_GUEST 0
317 #define RESUME_GUEST_DR RESUME_FLAG_DR
318 #define RESUME_HOST RESUME_FLAG_HOST
320 enum emulation_result {
321 EMULATE_DONE, /* no further processing */
322 EMULATE_DO_MMIO, /* kvm_run filled with MMIO request */
323 EMULATE_FAIL, /* can't emulate this instruction */
324 EMULATE_WAIT, /* WAIT instruction */
328 #define MIPS3_PG_G 0x00000001 /* Global; ignore ASID if in lo0 & lo1 */
329 #define MIPS3_PG_V 0x00000002 /* Valid */
330 #define MIPS3_PG_NV 0x00000000
331 #define MIPS3_PG_D 0x00000004 /* Dirty */
333 #define mips3_paddr_to_tlbpfn(x) \
334 (((unsigned long)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME)
335 #define mips3_tlbpfn_to_paddr(x) \
336 ((unsigned long)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT)
338 #define MIPS3_PG_SHIFT 6
339 #define MIPS3_PG_FRAME 0x3fffffc0
341 #define VPN2_MASK 0xffffe000
342 #define TLB_IS_GLOBAL(x) (((x).tlb_lo0 & MIPS3_PG_G) && \
343 ((x).tlb_lo1 & MIPS3_PG_G))
344 #define TLB_VPN2(x) ((x).tlb_hi & VPN2_MASK)
345 #define TLB_ASID(x) ((x).tlb_hi & ASID_MASK)
346 #define TLB_IS_VALID(x, va) (((va) & (1 << PAGE_SHIFT)) \
347 ? ((x).tlb_lo1 & MIPS3_PG_V) \
348 : ((x).tlb_lo0 & MIPS3_PG_V))
349 #define TLB_HI_VPN2_HIT(x, y) ((TLB_VPN2(x) & ~(x).tlb_mask) == \
350 ((y) & VPN2_MASK & ~(x).tlb_mask))
351 #define TLB_HI_ASID_HIT(x, y) (TLB_IS_GLOBAL(x) || \
352 TLB_ASID(x) == ((y) & ASID_MASK))
354 struct kvm_mips_tlb {
361 #define KVM_MIPS_FPU_FPU 0x1
362 #define KVM_MIPS_FPU_MSA 0x2
364 #define KVM_MIPS_GUEST_TLB_SIZE 64
365 struct kvm_vcpu_arch {
366 void *host_ebase, *guest_ebase;
367 unsigned long host_stack;
368 unsigned long host_gp;
370 /* Host CP0 registers used when handling exits from guest */
371 unsigned long host_cp0_badvaddr;
372 unsigned long host_cp0_cause;
373 unsigned long host_cp0_epc;
374 unsigned long host_cp0_entryhi;
378 unsigned long gprs[32];
384 struct mips_fpu_struct fpu;
385 /* Which FPU state is loaded (KVM_MIPS_FPU_*) */
386 unsigned int fpu_inuse;
389 struct mips_coproc *cop0;
391 /* Host KSEG0 address of the EI/DI offset */
392 void *kseg0_commpage;
394 u32 io_gpr; /* GPR used as IO source/target */
396 struct hrtimer comparecount_timer;
397 /* Count timer control KVM register */
399 /* Count bias from the raw time */
401 /* Frequency of timer in Hz */
403 /* Dynamic nanosecond bias (multiple of count_period) to avoid overflow */
406 ktime_t count_resume;
407 /* Period of timer tick in ns */
410 /* Bitmask of exceptions that are pending */
411 unsigned long pending_exceptions;
413 /* Bitmask of pending exceptions to be cleared */
414 unsigned long pending_exceptions_clr;
416 unsigned long pending_load_cause;
418 /* Save/Restore the entryhi register when are are preempted/scheduled back in */
419 unsigned long preempt_entryhi;
421 /* S/W Based TLB for guest */
422 struct kvm_mips_tlb guest_tlb[KVM_MIPS_GUEST_TLB_SIZE];
424 /* Cached guest kernel/user ASIDs */
425 uint32_t guest_user_asid[NR_CPUS];
426 uint32_t guest_kernel_asid[NR_CPUS];
427 struct mm_struct guest_kernel_mm, guest_user_mm;
439 #define kvm_read_c0_guest_index(cop0) (cop0->reg[MIPS_CP0_TLB_INDEX][0])
440 #define kvm_write_c0_guest_index(cop0, val) (cop0->reg[MIPS_CP0_TLB_INDEX][0] = val)
441 #define kvm_read_c0_guest_entrylo0(cop0) (cop0->reg[MIPS_CP0_TLB_LO0][0])
442 #define kvm_read_c0_guest_entrylo1(cop0) (cop0->reg[MIPS_CP0_TLB_LO1][0])
443 #define kvm_read_c0_guest_context(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0])
444 #define kvm_write_c0_guest_context(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0] = (val))
445 #define kvm_read_c0_guest_userlocal(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2])
446 #define kvm_write_c0_guest_userlocal(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2] = (val))
447 #define kvm_read_c0_guest_pagemask(cop0) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0])
448 #define kvm_write_c0_guest_pagemask(cop0, val) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0] = (val))
449 #define kvm_read_c0_guest_wired(cop0) (cop0->reg[MIPS_CP0_TLB_WIRED][0])
450 #define kvm_write_c0_guest_wired(cop0, val) (cop0->reg[MIPS_CP0_TLB_WIRED][0] = (val))
451 #define kvm_read_c0_guest_hwrena(cop0) (cop0->reg[MIPS_CP0_HWRENA][0])
452 #define kvm_write_c0_guest_hwrena(cop0, val) (cop0->reg[MIPS_CP0_HWRENA][0] = (val))
453 #define kvm_read_c0_guest_badvaddr(cop0) (cop0->reg[MIPS_CP0_BAD_VADDR][0])
454 #define kvm_write_c0_guest_badvaddr(cop0, val) (cop0->reg[MIPS_CP0_BAD_VADDR][0] = (val))
455 #define kvm_read_c0_guest_count(cop0) (cop0->reg[MIPS_CP0_COUNT][0])
456 #define kvm_write_c0_guest_count(cop0, val) (cop0->reg[MIPS_CP0_COUNT][0] = (val))
457 #define kvm_read_c0_guest_entryhi(cop0) (cop0->reg[MIPS_CP0_TLB_HI][0])
458 #define kvm_write_c0_guest_entryhi(cop0, val) (cop0->reg[MIPS_CP0_TLB_HI][0] = (val))
459 #define kvm_read_c0_guest_compare(cop0) (cop0->reg[MIPS_CP0_COMPARE][0])
460 #define kvm_write_c0_guest_compare(cop0, val) (cop0->reg[MIPS_CP0_COMPARE][0] = (val))
461 #define kvm_read_c0_guest_status(cop0) (cop0->reg[MIPS_CP0_STATUS][0])
462 #define kvm_write_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] = (val))
463 #define kvm_read_c0_guest_intctl(cop0) (cop0->reg[MIPS_CP0_STATUS][1])
464 #define kvm_write_c0_guest_intctl(cop0, val) (cop0->reg[MIPS_CP0_STATUS][1] = (val))
465 #define kvm_read_c0_guest_cause(cop0) (cop0->reg[MIPS_CP0_CAUSE][0])
466 #define kvm_write_c0_guest_cause(cop0, val) (cop0->reg[MIPS_CP0_CAUSE][0] = (val))
467 #define kvm_read_c0_guest_epc(cop0) (cop0->reg[MIPS_CP0_EXC_PC][0])
468 #define kvm_write_c0_guest_epc(cop0, val) (cop0->reg[MIPS_CP0_EXC_PC][0] = (val))
469 #define kvm_read_c0_guest_prid(cop0) (cop0->reg[MIPS_CP0_PRID][0])
470 #define kvm_write_c0_guest_prid(cop0, val) (cop0->reg[MIPS_CP0_PRID][0] = (val))
471 #define kvm_read_c0_guest_ebase(cop0) (cop0->reg[MIPS_CP0_PRID][1])
472 #define kvm_write_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] = (val))
473 #define kvm_read_c0_guest_config(cop0) (cop0->reg[MIPS_CP0_CONFIG][0])
474 #define kvm_read_c0_guest_config1(cop0) (cop0->reg[MIPS_CP0_CONFIG][1])
475 #define kvm_read_c0_guest_config2(cop0) (cop0->reg[MIPS_CP0_CONFIG][2])
476 #define kvm_read_c0_guest_config3(cop0) (cop0->reg[MIPS_CP0_CONFIG][3])
477 #define kvm_read_c0_guest_config4(cop0) (cop0->reg[MIPS_CP0_CONFIG][4])
478 #define kvm_read_c0_guest_config5(cop0) (cop0->reg[MIPS_CP0_CONFIG][5])
479 #define kvm_read_c0_guest_config7(cop0) (cop0->reg[MIPS_CP0_CONFIG][7])
480 #define kvm_write_c0_guest_config(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][0] = (val))
481 #define kvm_write_c0_guest_config1(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][1] = (val))
482 #define kvm_write_c0_guest_config2(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][2] = (val))
483 #define kvm_write_c0_guest_config3(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][3] = (val))
484 #define kvm_write_c0_guest_config4(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][4] = (val))
485 #define kvm_write_c0_guest_config5(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][5] = (val))
486 #define kvm_write_c0_guest_config7(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][7] = (val))
487 #define kvm_read_c0_guest_errorepc(cop0) (cop0->reg[MIPS_CP0_ERROR_PC][0])
488 #define kvm_write_c0_guest_errorepc(cop0, val) (cop0->reg[MIPS_CP0_ERROR_PC][0] = (val))
491 * Some of the guest registers may be modified asynchronously (e.g. from a
492 * hrtimer callback in hard irq context) and therefore need stronger atomicity
493 * guarantees than other registers.
496 static inline void _kvm_atomic_set_c0_guest_reg(unsigned long *reg,
501 __asm__ __volatile__(
507 : "=&r" (temp), "+m" (*reg)
509 } while (unlikely(!temp));
512 static inline void _kvm_atomic_clear_c0_guest_reg(unsigned long *reg,
517 __asm__ __volatile__(
523 : "=&r" (temp), "+m" (*reg)
525 } while (unlikely(!temp));
528 static inline void _kvm_atomic_change_c0_guest_reg(unsigned long *reg,
529 unsigned long change,
534 __asm__ __volatile__(
541 : "=&r" (temp), "+m" (*reg)
542 : "r" (~change), "r" (val & change));
543 } while (unlikely(!temp));
546 #define kvm_set_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] |= (val))
547 #define kvm_clear_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] &= ~(val))
549 /* Cause can be modified asynchronously from hardirq hrtimer callback */
550 #define kvm_set_c0_guest_cause(cop0, val) \
551 _kvm_atomic_set_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val)
552 #define kvm_clear_c0_guest_cause(cop0, val) \
553 _kvm_atomic_clear_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val)
554 #define kvm_change_c0_guest_cause(cop0, change, val) \
555 _kvm_atomic_change_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], \
558 #define kvm_set_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] |= (val))
559 #define kvm_clear_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] &= ~(val))
560 #define kvm_change_c0_guest_ebase(cop0, change, val) \
562 kvm_clear_c0_guest_ebase(cop0, change); \
563 kvm_set_c0_guest_ebase(cop0, ((val) & (change))); \
568 static inline bool kvm_mips_guest_can_have_fpu(struct kvm_vcpu_arch *vcpu)
570 return (!__builtin_constant_p(cpu_has_fpu) || cpu_has_fpu) &&
574 static inline bool kvm_mips_guest_has_fpu(struct kvm_vcpu_arch *vcpu)
576 return kvm_mips_guest_can_have_fpu(vcpu) &&
577 kvm_read_c0_guest_config1(vcpu->cop0) & MIPS_CONF1_FP;
580 static inline bool kvm_mips_guest_can_have_msa(struct kvm_vcpu_arch *vcpu)
582 return (!__builtin_constant_p(cpu_has_msa) || cpu_has_msa) &&
586 static inline bool kvm_mips_guest_has_msa(struct kvm_vcpu_arch *vcpu)
588 return kvm_mips_guest_can_have_msa(vcpu) &&
589 kvm_read_c0_guest_config3(vcpu->cop0) & MIPS_CONF3_MSA;
592 struct kvm_mips_callbacks {
593 int (*handle_cop_unusable)(struct kvm_vcpu *vcpu);
594 int (*handle_tlb_mod)(struct kvm_vcpu *vcpu);
595 int (*handle_tlb_ld_miss)(struct kvm_vcpu *vcpu);
596 int (*handle_tlb_st_miss)(struct kvm_vcpu *vcpu);
597 int (*handle_addr_err_st)(struct kvm_vcpu *vcpu);
598 int (*handle_addr_err_ld)(struct kvm_vcpu *vcpu);
599 int (*handle_syscall)(struct kvm_vcpu *vcpu);
600 int (*handle_res_inst)(struct kvm_vcpu *vcpu);
601 int (*handle_break)(struct kvm_vcpu *vcpu);
602 int (*handle_trap)(struct kvm_vcpu *vcpu);
603 int (*handle_msa_fpe)(struct kvm_vcpu *vcpu);
604 int (*handle_fpe)(struct kvm_vcpu *vcpu);
605 int (*handle_msa_disabled)(struct kvm_vcpu *vcpu);
606 int (*vm_init)(struct kvm *kvm);
607 int (*vcpu_init)(struct kvm_vcpu *vcpu);
608 int (*vcpu_setup)(struct kvm_vcpu *vcpu);
609 gpa_t (*gva_to_gpa)(gva_t gva);
610 void (*queue_timer_int)(struct kvm_vcpu *vcpu);
611 void (*dequeue_timer_int)(struct kvm_vcpu *vcpu);
612 void (*queue_io_int)(struct kvm_vcpu *vcpu,
613 struct kvm_mips_interrupt *irq);
614 void (*dequeue_io_int)(struct kvm_vcpu *vcpu,
615 struct kvm_mips_interrupt *irq);
616 int (*irq_deliver)(struct kvm_vcpu *vcpu, unsigned int priority,
618 int (*irq_clear)(struct kvm_vcpu *vcpu, unsigned int priority,
620 int (*get_one_reg)(struct kvm_vcpu *vcpu,
621 const struct kvm_one_reg *reg, s64 *v);
622 int (*set_one_reg)(struct kvm_vcpu *vcpu,
623 const struct kvm_one_reg *reg, s64 v);
624 int (*vcpu_get_regs)(struct kvm_vcpu *vcpu);
625 int (*vcpu_set_regs)(struct kvm_vcpu *vcpu);
627 extern struct kvm_mips_callbacks *kvm_mips_callbacks;
628 int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks);
630 /* Debug: dump vcpu state */
631 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu);
633 /* Trampoline ASM routine to start running in "Guest" context */
634 extern int __kvm_mips_vcpu_run(struct kvm_run *run, struct kvm_vcpu *vcpu);
636 /* FPU/MSA context management */
637 void __kvm_save_fpu(struct kvm_vcpu_arch *vcpu);
638 void __kvm_restore_fpu(struct kvm_vcpu_arch *vcpu);
639 void __kvm_restore_fcsr(struct kvm_vcpu_arch *vcpu);
640 void __kvm_save_msa(struct kvm_vcpu_arch *vcpu);
641 void __kvm_restore_msa(struct kvm_vcpu_arch *vcpu);
642 void __kvm_restore_msa_upper(struct kvm_vcpu_arch *vcpu);
643 void __kvm_restore_msacsr(struct kvm_vcpu_arch *vcpu);
644 void kvm_own_fpu(struct kvm_vcpu *vcpu);
645 void kvm_own_msa(struct kvm_vcpu *vcpu);
646 void kvm_drop_fpu(struct kvm_vcpu *vcpu);
647 void kvm_lose_fpu(struct kvm_vcpu *vcpu);
650 uint32_t kvm_get_kernel_asid(struct kvm_vcpu *vcpu);
652 uint32_t kvm_get_user_asid(struct kvm_vcpu *vcpu);
654 uint32_t kvm_get_commpage_asid (struct kvm_vcpu *vcpu);
656 extern int kvm_mips_handle_kseg0_tlb_fault(unsigned long badbaddr,
657 struct kvm_vcpu *vcpu);
659 extern int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr,
660 struct kvm_vcpu *vcpu);
662 extern int kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu *vcpu,
663 struct kvm_mips_tlb *tlb,
665 unsigned long *hpa1);
667 extern enum emulation_result kvm_mips_handle_tlbmiss(unsigned long cause,
670 struct kvm_vcpu *vcpu);
672 extern enum emulation_result kvm_mips_handle_tlbmod(unsigned long cause,
675 struct kvm_vcpu *vcpu);
677 extern void kvm_mips_dump_host_tlbs(void);
678 extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu);
679 extern void kvm_mips_flush_host_tlb(int skip_kseg0);
680 extern int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi);
681 extern int kvm_mips_host_tlb_inv_index(struct kvm_vcpu *vcpu, int index);
683 extern int kvm_mips_guest_tlb_lookup(struct kvm_vcpu *vcpu,
684 unsigned long entryhi);
685 extern int kvm_mips_host_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long vaddr);
686 extern unsigned long kvm_mips_translate_guest_kseg0_to_hpa(struct kvm_vcpu *vcpu,
688 extern void kvm_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu,
689 struct kvm_vcpu *vcpu);
690 extern void kvm_local_flush_tlb_all(void);
691 extern void kvm_mips_alloc_new_mmu_context(struct kvm_vcpu *vcpu);
692 extern void kvm_mips_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
693 extern void kvm_mips_vcpu_put(struct kvm_vcpu *vcpu);
696 uint32_t kvm_get_inst(uint32_t *opc, struct kvm_vcpu *vcpu);
697 enum emulation_result update_pc(struct kvm_vcpu *vcpu, uint32_t cause);
699 extern enum emulation_result kvm_mips_emulate_inst(unsigned long cause,
702 struct kvm_vcpu *vcpu);
704 extern enum emulation_result kvm_mips_emulate_syscall(unsigned long cause,
707 struct kvm_vcpu *vcpu);
709 extern enum emulation_result kvm_mips_emulate_tlbmiss_ld(unsigned long cause,
712 struct kvm_vcpu *vcpu);
714 extern enum emulation_result kvm_mips_emulate_tlbinv_ld(unsigned long cause,
717 struct kvm_vcpu *vcpu);
719 extern enum emulation_result kvm_mips_emulate_tlbmiss_st(unsigned long cause,
722 struct kvm_vcpu *vcpu);
724 extern enum emulation_result kvm_mips_emulate_tlbinv_st(unsigned long cause,
727 struct kvm_vcpu *vcpu);
729 extern enum emulation_result kvm_mips_emulate_tlbmod(unsigned long cause,
732 struct kvm_vcpu *vcpu);
734 extern enum emulation_result kvm_mips_emulate_fpu_exc(unsigned long cause,
737 struct kvm_vcpu *vcpu);
739 extern enum emulation_result kvm_mips_handle_ri(unsigned long cause,
742 struct kvm_vcpu *vcpu);
744 extern enum emulation_result kvm_mips_emulate_ri_exc(unsigned long cause,
747 struct kvm_vcpu *vcpu);
749 extern enum emulation_result kvm_mips_emulate_bp_exc(unsigned long cause,
752 struct kvm_vcpu *vcpu);
754 extern enum emulation_result kvm_mips_emulate_trap_exc(unsigned long cause,
757 struct kvm_vcpu *vcpu);
759 extern enum emulation_result kvm_mips_emulate_msafpe_exc(unsigned long cause,
762 struct kvm_vcpu *vcpu);
764 extern enum emulation_result kvm_mips_emulate_fpe_exc(unsigned long cause,
767 struct kvm_vcpu *vcpu);
769 extern enum emulation_result kvm_mips_emulate_msadis_exc(unsigned long cause,
772 struct kvm_vcpu *vcpu);
774 extern enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu,
775 struct kvm_run *run);
777 uint32_t kvm_mips_read_count(struct kvm_vcpu *vcpu);
778 void kvm_mips_write_count(struct kvm_vcpu *vcpu, uint32_t count);
779 void kvm_mips_write_compare(struct kvm_vcpu *vcpu, uint32_t compare);
780 void kvm_mips_init_count(struct kvm_vcpu *vcpu);
781 int kvm_mips_set_count_ctl(struct kvm_vcpu *vcpu, s64 count_ctl);
782 int kvm_mips_set_count_resume(struct kvm_vcpu *vcpu, s64 count_resume);
783 int kvm_mips_set_count_hz(struct kvm_vcpu *vcpu, s64 count_hz);
784 void kvm_mips_count_enable_cause(struct kvm_vcpu *vcpu);
785 void kvm_mips_count_disable_cause(struct kvm_vcpu *vcpu);
786 enum hrtimer_restart kvm_mips_count_timeout(struct kvm_vcpu *vcpu);
788 enum emulation_result kvm_mips_check_privilege(unsigned long cause,
791 struct kvm_vcpu *vcpu);
793 enum emulation_result kvm_mips_emulate_cache(uint32_t inst,
797 struct kvm_vcpu *vcpu);
798 enum emulation_result kvm_mips_emulate_CP0(uint32_t inst,
802 struct kvm_vcpu *vcpu);
803 enum emulation_result kvm_mips_emulate_store(uint32_t inst,
806 struct kvm_vcpu *vcpu);
807 enum emulation_result kvm_mips_emulate_load(uint32_t inst,
810 struct kvm_vcpu *vcpu);
812 unsigned int kvm_mips_config1_wrmask(struct kvm_vcpu *vcpu);
813 unsigned int kvm_mips_config3_wrmask(struct kvm_vcpu *vcpu);
814 unsigned int kvm_mips_config4_wrmask(struct kvm_vcpu *vcpu);
815 unsigned int kvm_mips_config5_wrmask(struct kvm_vcpu *vcpu);
817 /* Dynamic binary translation */
818 extern int kvm_mips_trans_cache_index(uint32_t inst, uint32_t *opc,
819 struct kvm_vcpu *vcpu);
820 extern int kvm_mips_trans_cache_va(uint32_t inst, uint32_t *opc,
821 struct kvm_vcpu *vcpu);
822 extern int kvm_mips_trans_mfc0(uint32_t inst, uint32_t *opc,
823 struct kvm_vcpu *vcpu);
824 extern int kvm_mips_trans_mtc0(uint32_t inst, uint32_t *opc,
825 struct kvm_vcpu *vcpu);
828 extern void kvm_mips_dump_stats(struct kvm_vcpu *vcpu);
829 extern unsigned long kvm_mips_get_ramsize(struct kvm *kvm);
831 static inline void kvm_arch_hardware_disable(void) {}
832 static inline void kvm_arch_hardware_unsetup(void) {}
833 static inline void kvm_arch_sync_events(struct kvm *kvm) {}
834 static inline void kvm_arch_free_memslot(struct kvm *kvm,
835 struct kvm_memory_slot *free, struct kvm_memory_slot *dont) {}
836 static inline void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots) {}
837 static inline void kvm_arch_flush_shadow_all(struct kvm *kvm) {}
838 static inline void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
839 struct kvm_memory_slot *slot) {}
840 static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {}
841 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
842 static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) {}
843 static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) {}
845 #endif /* __MIPS_KVM_HOST_H__ */