arch/mips/boot/dts/xilfpga/nexys4ddr.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /dts-v1/;
   3
   4 #include "microAptiv.dtsi"
   5
   6 / {
   7         compatible = "digilent,nexys4ddr";
   8
   9         memory {
  10                 device_type = "memory";
  11                 reg = <0x0 0x08000000>;
  12         };
  13
  14         cpuintc: interrupt-controller {
  15                 #address-cells = <0>;
  16                 #interrupt-cells = <1>;
  17                 interrupt-controller;
  18                 compatible = "mti,cpu-interrupt-controller";
  19         };
  20
  21         axi_intc: interrupt-controller@10200000 {
  22                 #interrupt-cells = <1>;
  23                 compatible = "xlnx,xps-intc-1.00.a";
  24                 interrupt-controller;
  25                 reg = <0x10200000 0x10000>;
  26                 xlnx,kind-of-intr = <0x0>;
  27                 xlnx,num-intr-inputs = <0x6>;
  28
  29                 interrupt-parent = <&cpuintc>;
  30                 interrupts = <6>;
  31         };
  32
  33         axi_gpio: gpio@10600000 {
  34                 #gpio-cells = <1>;
  35                 compatible = "xlnx,xps-gpio-1.00.a";
  36                 gpio-controller;
  37                 reg = <0x10600000 0x10000>;
  38                 xlnx,all-inputs = <0x0>;
  39                 xlnx,dout-default = <0x0>;
  40                 xlnx,gpio-width = <0x16>;
  41                 xlnx,interrupt-present = <0x0>;
  42                 xlnx,is-dual = <0x0>;
  43                 xlnx,tri-default = <0xffffffff>;
  44         } ;
  45
  46         axi_ethernetlite: ethernet@10e00000 {
  47                 compatible = "xlnx,xps-ethernetlite-3.00.a";
  48                 device_type = "network";
  49                 interrupt-parent = <&axi_intc>;
  50                 interrupts = <1>;
  51                 phy-handle = <&phy0>;
  52                 reg = <0x10e00000 0x10000>;
  53                 xlnx,duplex = <0x1>;
  54                 xlnx,include-global-buffers = <0x1>;
  55                 xlnx,include-internal-loopback = <0x0>;
  56                 xlnx,include-mdio = <0x1>;
  57                 xlnx,instance = "axi_ethernetlite_inst";
  58                 xlnx,rx-ping-pong = <0x1>;
  59                 xlnx,s-axi-id-width = <0x1>;
  60                 xlnx,tx-ping-pong = <0x1>;
  61                 xlnx,use-internal = <0x0>;
  62                 mdio {
  63                         #address-cells = <1>;
  64                         #size-cells = <0>;
  65                         phy0: phy@1 {
  66                                 device_type = "ethernet-phy";
  67                                 reg = <1>;
  68                         };
  69                 };
  70         };
  71
  72         axi_uart16550: serial@10400000 {
  73                 compatible = "ns16550a";
  74                 reg = <0x10400000 0x10000>;
  75
  76                 reg-shift = <2>;
  77                 reg-offset = <0x1000>;
  78
  79                 clocks  = <&ext>;
  80
  81                 interrupt-parent = <&axi_intc>;
  82                 interrupts = <0>;
  83         };
  84
  85         axi_i2c: i2c@10A00000 {
  86             compatible = "xlnx,xps-iic-2.00.a";
  87             interrupt-parent = <&axi_intc>;
  88             interrupts = <4>;
  89             reg = < 0x10A00000 0x10000 >;
  90             clocks = <&ext>;
  91             xlnx,clk-freq = <0x5f5e100>;
  92             xlnx,family = "Artix7";
  93             xlnx,gpo-width = <0x1>;
  94             xlnx,iic-freq = <0x186a0>;
  95             xlnx,scl-inertial-delay = <0x0>;
  96             xlnx,sda-inertial-delay = <0x0>;
  97             xlnx,ten-bit-adr = <0x0>;
  98             #address-cells = <1>;
  99             #size-cells = <0>;
 100
 101             ad7420@4B {
 102                 compatible = "adi,adt7420";
 103                 reg = <0x4B>;
 104             };
 105         } ;
 106 };
 107
 108 &ext {
 109         clock-frequency = <50000000>;
 110 };