1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 #include <dt-bindings/interrupt-controller/mips-gic.h>
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/clock/mt7621-clk.h>
5 #include <dt-bindings/reset/mt7621-reset.h>
10 compatible = "mediatek,mt7621-soc";
18 compatible = "mips,mips1004Kc";
24 compatible = "mips,mips1004Kc";
31 #interrupt-cells = <1>;
33 compatible = "mti,cpu-interrupt-controller";
36 mmc_fixed_3v3: regulator-3v3 {
37 compatible = "regulator-fixed";
38 regulator-name = "mmc_power";
39 regulator-min-microvolt = <3300000>;
40 regulator-max-microvolt = <3300000>;
45 mmc_fixed_1v8_io: regulator-1v8 {
46 compatible = "regulator-fixed";
47 regulator-name = "mmc_io";
48 regulator-min-microvolt = <1800000>;
49 regulator-max-microvolt = <1800000>;
54 palmbus: palmbus@1e000000 {
55 compatible = "palmbus";
56 reg = <0x1e000000 0x100000>;
57 ranges = <0x0 0x1e000000 0x0fffff>;
63 compatible = "mediatek,mt7621-sysc", "syscon";
67 ralink,memctl = <&memc>;
68 clock-output-names = "xtal", "cpu", "bus",
69 "50m", "125m", "150m",
74 compatible = "mediatek,mt7621-wdt";
80 #interrupt-cells = <2>;
81 compatible = "mediatek,mt7621-gpio";
83 gpio-ranges = <&pinctrl 0 0 95>;
86 interrupt-parent = <&gic>;
87 interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
91 compatible = "mediatek,mt7621-i2c";
94 clocks = <&sysc MT7621_CLK_I2C>;
96 resets = <&sysc MT7621_RST_I2C>;
104 pinctrl-names = "default";
105 pinctrl-0 = <&i2c_pins>;
108 memc: memory-controller@5000 {
109 compatible = "mediatek,mt7621-memc", "syscon";
110 reg = <0x5000 0x1000>;
113 serial0: serial@c00 {
114 compatible = "ns16550a";
117 clocks = <&sysc MT7621_CLK_UART1>;
119 interrupt-parent = <&gic>;
120 interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
130 compatible = "ralink,mt7621-spi";
133 clocks = <&sysc MT7621_CLK_SPI>;
136 resets = <&sysc MT7621_RST_SPI>;
139 #address-cells = <1>;
142 pinctrl-names = "default";
143 pinctrl-0 = <&spi_pins>;
148 compatible = "ralink,mt7621-pinctrl";
150 i2c_pins: i2c0-pins {
157 spi_pins: spi0-pins {
164 uart1_pins: uart1-pins {
171 uart2_pins: uart2-pins {
178 uart3_pins: uart3-pins {
185 rgmii1_pins: rgmii1-pins {
192 rgmii2_pins: rgmii2-pins {
199 mdio_pins: mdio0-pins {
206 pcie_pins: pcie0-pins {
213 nand_pins: nand0-pins {
225 sdhci_pins: sdhci0-pins {
236 compatible = "mediatek,mt7620-mmc";
237 reg = <0x1e130000 0x4000>;
240 max-frequency = <48000000>;
243 vmmc-supply = <&mmc_fixed_3v3>;
244 vqmmc-supply = <&mmc_fixed_1v8_io>;
247 pinctrl-names = "default", "state_uhs";
248 pinctrl-0 = <&sdhci_pins>;
249 pinctrl-1 = <&sdhci_pins>;
251 clocks = <&sysc MT7621_CLK_SHXC>,
252 <&sysc MT7621_CLK_50M>;
253 clock-names = "source", "hclk";
255 interrupt-parent = <&gic>;
256 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
260 compatible = "mediatek,mt8173-xhci", "mediatek,mtk-xhci";
261 reg = <0x1e1c0000 0x1000
263 reg-names = "mac", "ippc";
265 clocks = <&sysc MT7621_CLK_XTAL>;
266 clock-names = "sys_ck";
268 interrupt-parent = <&gic>;
269 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
272 gic: interrupt-controller@1fbc0000 {
273 compatible = "mti,gic";
274 reg = <0x1fbc0000 0x2000>;
276 interrupt-controller;
277 #interrupt-cells = <3>;
279 mti,reserved-cpu-vectors = <7>;
282 compatible = "mti,gic-timer";
283 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
284 clocks = <&sysc MT7621_CLK_CPU>;
289 compatible = "mti,mips-cpc";
290 reg = <0x1fbf0000 0x8000>;
293 cdmm: cdmm@1fbf8000 {
294 compatible = "mti,mips-cdmm";
295 reg = <0x1fbf8000 0x8000>;
298 ethernet: ethernet@1e100000 {
299 compatible = "mediatek,mt7621-eth";
300 reg = <0x1e100000 0x10000>;
302 clocks = <&sysc MT7621_CLK_FE>,
303 <&sysc MT7621_CLK_ETH>;
304 clock-names = "fe", "ethif";
306 #address-cells = <1>;
309 resets = <&sysc MT7621_RST_FE &sysc MT7621_RST_ETH>;
310 reset-names = "fe", "eth";
312 interrupt-parent = <&gic>;
313 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
315 mediatek,ethsys = <&sysc>;
317 pinctrl-names = "default";
318 pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>, <&rgmii2_pins>;
321 compatible = "mediatek,eth-mac";
333 compatible = "mediatek,eth-mac";
340 #address-cells = <1>;
344 compatible = "mediatek,mt7621";
347 resets = <&sysc MT7621_RST_MCM>;
349 interrupt-controller;
350 #interrupt-cells = <1>;
351 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
354 #address-cells = <1>;
403 pcie: pcie@1e140000 {
404 compatible = "mediatek,mt7621-pci";
405 reg = <0x1e140000 0x100>, /* host-pci bridge registers */
406 <0x1e142000 0x100>, /* pcie port 0 RC control registers */
407 <0x1e143000 0x100>, /* pcie port 1 RC control registers */
408 <0x1e144000 0x100>; /* pcie port 2 RC control registers */
409 #address-cells = <3>;
412 pinctrl-names = "default";
413 pinctrl-0 = <&pcie_pins>;
417 ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */
418 <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */
420 #interrupt-cells = <1>;
421 interrupt-map-mask = <0xF800 0 0 0>;
422 interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
423 <0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
424 <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
428 reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
431 reg = <0x0000 0 0 0 0>;
432 #address-cells = <3>;
435 #interrupt-cells = <1>;
436 interrupt-map-mask = <0 0 0 0>;
437 interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
438 resets = <&sysc MT7621_RST_PCIE0>;
439 clocks = <&sysc MT7621_CLK_PCIE0>;
440 phys = <&pcie0_phy 1>;
441 phy-names = "pcie-phy0";
446 reg = <0x0800 0 0 0 0>;
447 #address-cells = <3>;
450 #interrupt-cells = <1>;
451 interrupt-map-mask = <0 0 0 0>;
452 interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
453 resets = <&sysc MT7621_RST_PCIE1>;
454 clocks = <&sysc MT7621_CLK_PCIE1>;
455 phys = <&pcie0_phy 1>;
456 phy-names = "pcie-phy1";
461 reg = <0x1000 0 0 0 0>;
462 #address-cells = <3>;
465 #interrupt-cells = <1>;
466 interrupt-map-mask = <0 0 0 0>;
467 interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
468 resets = <&sysc MT7621_RST_PCIE2>;
469 clocks = <&sysc MT7621_CLK_PCIE2>;
470 phys = <&pcie2_phy 0>;
471 phy-names = "pcie-phy2";
476 pcie0_phy: pcie-phy@1e149000 {
477 compatible = "mediatek,mt7621-pci-phy";
478 reg = <0x1e149000 0x0700>;
479 clocks = <&sysc MT7621_CLK_XTAL>;
483 pcie2_phy: pcie-phy@1e14a000 {
484 compatible = "mediatek,mt7621-pci-phy";
485 reg = <0x1e14a000 0x0700>;
486 clocks = <&sysc MT7621_CLK_XTAL>;