1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2017 Microsemi Corporation */
7 compatible = "mscc,ocelot";
14 compatible = "mips,mips24KEc";
25 cpuintc: interrupt-controller {
27 #interrupt-cells = <1>;
29 compatible = "mti,cpu-interrupt-controller";
33 compatible = "fixed-clock";
35 clock-frequency = <500000000>;
39 compatible = "fixed-factor-clock";
47 compatible = "simple-bus";
50 ranges = <0 0x70000000 0x2000000>;
52 interrupt-parent = <&intc>;
55 compatible = "mscc,ocelot-cpu-syscon", "syscon";
59 intc: interrupt-controller@70 {
60 compatible = "mscc,ocelot-icpu-intr";
62 #interrupt-cells = <1>;
64 interrupt-parent = <&cpuintc>;
68 uart0: serial@100000 {
69 pinctrl-0 = <&uart_pins>;
70 pinctrl-names = "default";
71 compatible = "ns16550a";
72 reg = <0x100000 0x20>;
82 compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
83 pinctrl-0 = <&i2c_pins>;
84 pinctrl-names = "default";
85 reg = <0x100400 0x100>, <0x198 0x8>;
94 uart2: serial@100800 {
95 pinctrl-0 = <&uart2_pins>;
96 pinctrl-names = "default";
97 compatible = "ns16550a";
98 reg = <0x100800 0x20>;
108 compatible = "mscc,ocelot-spi", "snps,dw-apb-ssi";
109 #address-cells = <1>;
111 reg = <0x101000 0x100>, <0x3c 0x18>;
119 compatible = "mscc,vsc7514-switch";
120 reg = <0x1010000 0x10000>,
136 reg-names = "sys", "rew", "qs", "port0", "port1",
137 "port2", "port3", "port4", "port5", "port6",
138 "port7", "port8", "port9", "port10", "qsys",
140 interrupts = <21 22>;
141 interrupt-names = "xtr", "inj";
144 #address-cells = <1>;
184 compatible = "mscc,ocelot-chip-reset";
185 reg = <0x1070008 0x4>;
188 gpio: pinctrl@1070034 {
189 compatible = "mscc,ocelot-pinctrl";
190 reg = <0x1070034 0x68>;
193 gpio-ranges = <&gpio 0 0 22>;
194 interrupt-controller;
196 #interrupt-cells = <2>;
199 pins = "GPIO_16", "GPIO_17";
203 uart_pins: uart-pins {
204 pins = "GPIO_6", "GPIO_7";
208 uart2_pins: uart2-pins {
209 pins = "GPIO_12", "GPIO_13";
214 pins = "GPIO_14", "GPIO_15";
220 mdio0: mdio@107009c {
221 #address-cells = <1>;
223 compatible = "mscc,ocelot-miim";
224 reg = <0x107009c 0x24>, <0x10700f0 0x8>;
228 phy0: ethernet-phy@0 {
231 phy1: ethernet-phy@1 {
234 phy2: ethernet-phy@2 {
237 phy3: ethernet-phy@3 {
242 mdio1: mdio@10700c0 {
243 #address-cells = <1>;
245 compatible = "mscc,ocelot-miim";
246 reg = <0x10700c0 0x24>;
248 pinctrl-names = "default";
249 pinctrl-0 = <&miim1>;
253 hsio: syscon@10d0000 {
254 compatible = "mscc,ocelot-hsio", "syscon", "simple-mfd";
255 reg = <0x10d0000 0x10000>;
258 compatible = "mscc,vsc7514-serdes";