2 * Atheros AR71XX/AR724X/AR913X common routines
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
7 * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/err.h>
18 #include <linux/clk.h>
19 #include <linux/clkdev.h>
20 #include <linux/clk-provider.h>
22 #include <asm/div64.h>
24 #include <asm/mach-ath79/ath79.h>
25 #include <asm/mach-ath79/ar71xx_regs.h>
28 #define AR71XX_BASE_FREQ 40000000
29 #define AR724X_BASE_FREQ 40000000
31 static struct clk *clks[3];
32 static struct clk_onecell_data clk_data = {
34 .clk_num = ARRAY_SIZE(clks),
37 static struct clk *__init ath79_add_sys_clkdev(
38 const char *id, unsigned long rate)
43 clk = clk_register_fixed_rate(NULL, id, NULL, CLK_IS_ROOT, rate);
45 panic("failed to allocate %s clock structure", id);
47 err = clk_register_clkdev(clk, id, NULL);
49 panic("unable to register %s clock device", id);
54 static void __init ar71xx_clocks_init(void)
56 unsigned long ref_rate;
57 unsigned long cpu_rate;
58 unsigned long ddr_rate;
59 unsigned long ahb_rate;
64 ref_rate = AR71XX_BASE_FREQ;
66 pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
68 div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1;
69 freq = div * ref_rate;
71 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
72 cpu_rate = freq / div;
74 div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
75 ddr_rate = freq / div;
77 div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
78 ahb_rate = cpu_rate / div;
80 ath79_add_sys_clkdev("ref", ref_rate);
81 clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
82 clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
83 clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
85 clk_add_alias("wdt", NULL, "ahb", NULL);
86 clk_add_alias("uart", NULL, "ahb", NULL);
89 static void __init ar724x_clocks_init(void)
91 unsigned long ref_rate;
92 unsigned long cpu_rate;
93 unsigned long ddr_rate;
94 unsigned long ahb_rate;
99 ref_rate = AR724X_BASE_FREQ;
100 pll = ath79_pll_rr(AR724X_PLL_REG_CPU_CONFIG);
102 div = ((pll >> AR724X_PLL_FB_SHIFT) & AR724X_PLL_FB_MASK);
103 freq = div * ref_rate;
105 div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2;
110 div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
111 ddr_rate = freq / div;
113 div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
114 ahb_rate = cpu_rate / div;
116 ath79_add_sys_clkdev("ref", ref_rate);
117 clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
118 clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
119 clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
121 clk_add_alias("wdt", NULL, "ahb", NULL);
122 clk_add_alias("uart", NULL, "ahb", NULL);
125 static void __init ar933x_clocks_init(void)
127 unsigned long ref_rate;
128 unsigned long cpu_rate;
129 unsigned long ddr_rate;
130 unsigned long ahb_rate;
136 t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
137 if (t & AR933X_BOOTSTRAP_REF_CLK_40)
138 ref_rate = (40 * 1000 * 1000);
140 ref_rate = (25 * 1000 * 1000);
142 clock_ctrl = ath79_pll_rr(AR933X_PLL_CLOCK_CTRL_REG);
143 if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
148 cpu_config = ath79_pll_rr(AR933X_PLL_CPU_CONFIG_REG);
150 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
151 AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
154 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
155 AR933X_PLL_CPU_CONFIG_NINT_MASK;
158 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
159 AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
165 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
166 AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
169 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
170 AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
173 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
174 AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
178 ath79_add_sys_clkdev("ref", ref_rate);
179 clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
180 clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
181 clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
183 clk_add_alias("wdt", NULL, "ahb", NULL);
184 clk_add_alias("uart", NULL, "ref", NULL);
187 static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
188 u32 frac, u32 out_div)
200 do_div(t, ref_div * frac);
203 ret /= (1 << out_div);
207 static void __init ar934x_clocks_init(void)
209 unsigned long ref_rate;
210 unsigned long cpu_rate;
211 unsigned long ddr_rate;
212 unsigned long ahb_rate;
213 u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv;
214 u32 cpu_pll, ddr_pll;
216 void __iomem *dpll_base;
218 dpll_base = ioremap(AR934X_SRIF_BASE, AR934X_SRIF_SIZE);
220 bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
221 if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40)
222 ref_rate = 40 * 1000 * 1000;
224 ref_rate = 25 * 1000 * 1000;
226 pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG);
227 if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
228 out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
229 AR934X_SRIF_DPLL2_OUTDIV_MASK;
230 pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL1_REG);
231 nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
232 AR934X_SRIF_DPLL1_NINT_MASK;
233 nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
234 ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
235 AR934X_SRIF_DPLL1_REFDIV_MASK;
238 pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG);
239 out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
240 AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
241 ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
242 AR934X_PLL_CPU_CONFIG_REFDIV_MASK;
243 nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &
244 AR934X_PLL_CPU_CONFIG_NINT_MASK;
245 nfrac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
246 AR934X_PLL_CPU_CONFIG_NFRAC_MASK;
250 cpu_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
251 nfrac, frac, out_div);
253 pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG);
254 if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
255 out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
256 AR934X_SRIF_DPLL2_OUTDIV_MASK;
257 pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL1_REG);
258 nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
259 AR934X_SRIF_DPLL1_NINT_MASK;
260 nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
261 ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
262 AR934X_SRIF_DPLL1_REFDIV_MASK;
265 pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG);
266 out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
267 AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
268 ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
269 AR934X_PLL_DDR_CONFIG_REFDIV_MASK;
270 nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &
271 AR934X_PLL_DDR_CONFIG_NINT_MASK;
272 nfrac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
273 AR934X_PLL_DDR_CONFIG_NFRAC_MASK;
277 ddr_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
278 nfrac, frac, out_div);
280 clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
282 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &
283 AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;
285 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS)
287 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL)
288 cpu_rate = cpu_pll / (postdiv + 1);
290 cpu_rate = ddr_pll / (postdiv + 1);
292 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) &
293 AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK;
295 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS)
297 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL)
298 ddr_rate = ddr_pll / (postdiv + 1);
300 ddr_rate = cpu_pll / (postdiv + 1);
302 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) &
303 AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK;
305 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS)
307 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL)
308 ahb_rate = ddr_pll / (postdiv + 1);
310 ahb_rate = cpu_pll / (postdiv + 1);
312 ath79_add_sys_clkdev("ref", ref_rate);
313 clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
314 clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
315 clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
317 clk_add_alias("wdt", NULL, "ref", NULL);
318 clk_add_alias("uart", NULL, "ref", NULL);
323 static void __init qca955x_clocks_init(void)
325 unsigned long ref_rate;
326 unsigned long cpu_rate;
327 unsigned long ddr_rate;
328 unsigned long ahb_rate;
329 u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
330 u32 cpu_pll, ddr_pll;
333 bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
334 if (bootstrap & QCA955X_BOOTSTRAP_REF_CLK_40)
335 ref_rate = 40 * 1000 * 1000;
337 ref_rate = 25 * 1000 * 1000;
339 pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG);
340 out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
341 QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
342 ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
343 QCA955X_PLL_CPU_CONFIG_REFDIV_MASK;
344 nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) &
345 QCA955X_PLL_CPU_CONFIG_NINT_MASK;
346 frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
347 QCA955X_PLL_CPU_CONFIG_NFRAC_MASK;
349 cpu_pll = nint * ref_rate / ref_div;
350 cpu_pll += frac * ref_rate / (ref_div * (1 << 6));
351 cpu_pll /= (1 << out_div);
353 pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG);
354 out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
355 QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK;
356 ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
357 QCA955X_PLL_DDR_CONFIG_REFDIV_MASK;
358 nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) &
359 QCA955X_PLL_DDR_CONFIG_NINT_MASK;
360 frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
361 QCA955X_PLL_DDR_CONFIG_NFRAC_MASK;
363 ddr_pll = nint * ref_rate / ref_div;
364 ddr_pll += frac * ref_rate / (ref_div * (1 << 10));
365 ddr_pll /= (1 << out_div);
367 clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG);
369 postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
370 QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
372 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
374 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
375 cpu_rate = ddr_pll / (postdiv + 1);
377 cpu_rate = cpu_pll / (postdiv + 1);
379 postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
380 QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
382 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
384 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
385 ddr_rate = cpu_pll / (postdiv + 1);
387 ddr_rate = ddr_pll / (postdiv + 1);
389 postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
390 QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
392 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
394 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
395 ahb_rate = ddr_pll / (postdiv + 1);
397 ahb_rate = cpu_pll / (postdiv + 1);
399 ath79_add_sys_clkdev("ref", ref_rate);
400 clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
401 clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
402 clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
404 clk_add_alias("wdt", NULL, "ref", NULL);
405 clk_add_alias("uart", NULL, "ref", NULL);
408 void __init ath79_clocks_init(void)
411 ar71xx_clocks_init();
412 else if (soc_is_ar724x() || soc_is_ar913x())
413 ar724x_clocks_init();
414 else if (soc_is_ar933x())
415 ar933x_clocks_init();
416 else if (soc_is_ar934x())
417 ar934x_clocks_init();
418 else if (soc_is_qca955x())
419 qca955x_clocks_init();
427 ath79_get_sys_clk_rate(const char *id)
432 clk = clk_get(NULL, id);
434 panic("unable to get %s clock, err=%d", id, (int) PTR_ERR(clk));
436 rate = clk_get_rate(clk);
443 static void __init ath79_clocks_init_dt(struct device_node *np)
445 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
448 CLK_OF_DECLARE(ar7100, "qca,ar7100-pll", ath79_clocks_init_dt);
449 CLK_OF_DECLARE(ar7240, "qca,ar7240-pll", ath79_clocks_init_dt);
450 CLK_OF_DECLARE(ar9130, "qca,ar9130-pll", ath79_clocks_init_dt);
451 CLK_OF_DECLARE(ar9330, "qca,ar9330-pll", ath79_clocks_init_dt);
452 CLK_OF_DECLARE(ar9340, "qca,ar9340-pll", ath79_clocks_init_dt);
453 CLK_OF_DECLARE(ar9550, "qca,qca9550-pll", ath79_clocks_init_dt);